From 38d26fa60f652cbfa8b0a1d63ed4ee8230f5a30b Mon Sep 17 00:00:00 2001 From: uweigand Date: Wed, 14 Dec 2005 16:10:10 +0000 Subject: [PATCH] 2005-12-14 Adrian Straetling * config/s390/s390.md ("d0", "1"): New mode attributes. ("di3", "si3"): Merge. ("*di3_and", "*si3_and"): Merge. ("ashrdi3", "ashrsi3"): Merge. ("*ashrdi3_cc", "*ashrsi3_cc"): Merge. ("*ashrdi3_cc_and", "*ashrsi3_cc_and"): Merge. ("*ashrdi3_cconly", "*ashrsi3_cconly"): Merge. ("*ashrdi3_cconly_and", "*ashrsi3_cconly_and"): Merge. ("*ashrdi3", "*ashrsi3"): Merge. ("*ashrdi3_and", "*ashrsi3_and"): Merge. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@108516 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 13 +++ gcc/config/s390/s390.md | 250 +++++++++++++++--------------------------------- 2 files changed, 92 insertions(+), 171 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 68b7795..a50c1e3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,18 @@ 2005-12-14 Adrian Straetling + * config/s390/s390.md ("d0", "1"): New mode attributes. + ("di3", "si3"): Merge. + ("*di3_and", "*si3_and"): Merge. + ("ashrdi3", "ashrsi3"): Merge. + ("*ashrdi3_cc", "*ashrsi3_cc"): Merge. + ("*ashrdi3_cc_and", "*ashrsi3_cc_and"): Merge. + ("*ashrdi3_cconly", "*ashrsi3_cconly"): Merge. + ("*ashrdi3_cconly_and", "*ashrsi3_cconly_and"): Merge. + ("*ashrdi3", "*ashrsi3"): Merge. + ("*ashrdi3_and", "*ashrsi3_and"): Merge. + +2005-12-14 Adrian Straetling + * config/s390/s390.md ("extenddi2", "extendsi2"): Merge. ("*extendqidi2_extimm", "*extendqisi2_extimm"): Merge. ("*extendqidi2", "*extendqisi2") Merge. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 3c634b3..274c233 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -299,6 +299,16 @@ ;; and "meebr" in SFmode. This is needed for the 'mul3' pattern. (define_mode_attr dee [(DF "d") (SF "ee")]) +;; In GPR and P templates, a constraint like "" will expand to "d" in DImode +;; and "0" in SImode. This allows to combine instructions of which the 31bit +;; version only operates on one register. +(define_mode_attr d0 [(DI "d") (SI "0")]) + +;; In combination with d0 this allows to combine instructions of which the 31bit +;; version only operates on one register. The DImode version needs an additional +;; register for the assembler output. +(define_mode_attr 1 [(DI "%1,") (SI "")]) + ;; In SHIFT templates, a string like "sdl" will expand to "sldl" in ;; 'ashift' and "srdl" in 'lshiftrt'. (define_code_attr lr [(ashift "l") (lshiftrt "r")]) @@ -6208,13 +6218,13 @@ ;; ; -; (ashl|lshr)di3 instruction pattern(s). +; (ashl|lshr)(di|si)3 instruction pattern(s). ; -(define_expand "di3" - [(set (match_operand:DI 0 "register_operand" "") - (SHIFT:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] +(define_expand "3" + [(set (match_operand:DSI 0 "register_operand" "") + (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] "" "") @@ -6227,13 +6237,13 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*di3_64" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "TARGET_64BIT" - "slg\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") +(define_insn "*3" + [(set (match_operand:GPR 0 "register_operand" "=d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] + "" + "sl\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) (define_insn "*di3_31_and" @@ -6246,25 +6256,25 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*di3_64_and" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" - "slg\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") +(define_insn "*3_and" + [(set (match_operand:GPR 0 "register_operand" "=d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") + (match_operand:SI 3 "const_int_operand" "n"))))] + "(INTVAL (operands[3]) & 63) == 63" + "sl\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) ; -; ashrdi3 instruction pattern(s). +; ashr(di|si)3 instruction pattern(s). ; -(define_expand "ashrdi3" +(define_expand "ashr3" [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) + [(set (match_operand:DSI 0 "register_operand" "") + (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "" "") @@ -6302,37 +6312,37 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashrdi3_cc_64" +(define_insn "*ashr3_cc" [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") + (set (match_operand:GPR 0 "register_operand" "=d") + (ashiftrt:GPR (match_dup 1) (match_dup 2)))] + "s390_match_ccmode(insn, CCSmode)" + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashrdi3_cconly_64" +(define_insn "*ashr3_cconly" [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") + (clobber (match_scratch:GPR 0 "=d"))] + "s390_match_ccmode(insn, CCSmode)" + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashrdi3_64" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) +(define_insn "*ashr3" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") + "" + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -6376,142 +6386,40 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashrdi3_cc_64_and" +(define_insn "*ashr3_cc_and" [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") + (match_operand:SI 3 "const_int_operand" "n"))) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] - "TARGET_64BIT && s390_match_ccmode(insn, CCSmode) - && (INTVAL (operands[3]) & 63) == 63" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_cconly_64_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) - (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "TARGET_64BIT && s390_match_ccmode(insn, CCSmode) - && (INTVAL (operands[3]) & 63) == 63" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_64_and" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n")))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" - "srag\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -; -; (ashl|lshr)si3 instruction pattern(s). -; - -(define_insn "si3" - [(set (match_operand:SI 0 "register_operand" "=d") - (SHIFT:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "" - "sl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*si3_and" - [(set (match_operand:SI 0 "register_operand" "=d") - (SHIFT:SI (match_operand:SI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "(INTVAL (operands[3]) & 63) == 63" - "sl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -; -; ashrsi3 instruction pattern(s). -; - -(define_insn "*ashrsi3_cc" - [(set (reg CC_REGNUM) - (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) - (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCSmode)" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - - -(define_insn "*ashrsi3_cconly" - [(set (reg CC_REGNUM) - (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=d"))] - "s390_match_ccmode(insn, CCSmode)" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) - (clobber (reg:CC CC_REGNUM))] - "" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -; with implicit ANDs - -(define_insn "*ashrsi3_cc_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) - (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d") - (ashiftrt:SI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] + (set (match_operand:GPR 0 "register_operand" "=d") + (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) - -(define_insn "*ashrsi3_cconly_and" +(define_insn "*ashr3_cconly_and" [(set (reg CC_REGNUM) - (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") + (match_operand:SI 3 "const_int_operand" "n"))) (const_int 0))) - (clobber (match_scratch:SI 0 "=d"))] + (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashrsi3_and" - [(set (match_operand:SI 0 "register_operand" "=d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n")))) +(define_insn "*ashr3_and" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") + (match_operand:SI 3 "const_int_operand" "n")))) (clobber (reg:CC CC_REGNUM))] "(INTVAL (operands[3]) & 63) == 63" - "sra\t%0,%Y2" - [(set_attr "op_type" "RS") + "sra\t%0,<1>%Y2" + [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -- 2.7.4