From 38aa386e96e96ad1a2cd9191c47d1603f2f2e1bd Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 14 Jun 2019 15:07:24 +0200 Subject: [PATCH] radv: store the FCE predicate for each mip Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 19 ++++++++++++------- src/amd/vulkan/radv_meta_clear.c | 9 ++++++++- src/amd/vulkan/radv_meta_fast_clear.c | 2 +- src/amd/vulkan/radv_private.h | 12 +++++++++++- 4 files changed, 32 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index cdc88f5..e29ee70 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1607,22 +1607,27 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, */ void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, bool value) + struct radv_image *image, + const VkImageSubresourceRange *range, bool value) { uint64_t pred_val = value; - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->fce_pred_offset; + uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel); + uint32_t level_count = radv_get_levelCount(image, range); + uint32_t count = 2 * level_count; assert(radv_image_has_dcc(image)); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_PFP)); radeon_emit(cmd_buffer->cs, va); radeon_emit(cmd_buffer->cs, va >> 32); - radeon_emit(cmd_buffer->cs, pred_val); - radeon_emit(cmd_buffer->cs, pred_val >> 32); + + for (uint32_t l = 0; l < level_count; l++) { + radeon_emit(cmd_buffer->cs, pred_val); + radeon_emit(cmd_buffer->cs, pred_val >> 32); + } } /** @@ -4937,7 +4942,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, radv_initialize_dcc(cmd_buffer, image, value); - radv_update_fce_metadata(cmd_buffer, image, + radv_update_fce_metadata(cmd_buffer, image, range, need_decompress_pass); } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index c3678a7..269d047 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1521,6 +1521,13 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, uint32_t reset_value; bool can_avoid_fast_clear_elim; bool need_decompress_pass = false; + VkImageSubresourceRange range = { + .aspectMask = iview->aspect_mask, + .baseMipLevel = iview->base_mip, + .levelCount = iview->level_count, + .baseArrayLayer = iview->base_layer, + .layerCount = iview->layer_count, + }; vi_get_fast_clear_parameters(iview->vk_format, &clear_value, &reset_value, @@ -1538,7 +1545,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value); - radv_update_fce_metadata(cmd_buffer, iview->image, + radv_update_fce_metadata(cmd_buffer, iview->image, &range, need_decompress_pass); } else { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index 176f980..46472ba 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -712,7 +712,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, /* Clear the image's fast-clear eliminate predicate because * FMASK and DCC also imply a fast-clear eliminate. */ - radv_update_fce_metadata(cmd_buffer, image, false); + radv_update_fce_metadata(cmd_buffer, image, subresourceRange, false); /* Mark the image as being decompressed. */ if (decompress_dcc) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 3307551..e9ad3d2 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1257,7 +1257,8 @@ void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint32_t color_values[2]); void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, bool value); + struct radv_image *image, + const VkImageSubresourceRange *range, bool value); void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, bool value); @@ -1690,6 +1691,15 @@ radv_image_get_fast_clear_va(const struct radv_image *image, return va; } +static inline uint64_t +radv_image_get_fce_pred_va(const struct radv_image *image, + uint32_t base_level) +{ + uint64_t va = radv_buffer_get_va(image->bo); + va += image->offset + image->fce_pred_offset + base_level * 8; + return va; +} + unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family); static inline uint32_t -- 2.7.4