From 3895dd7675197167789e3b346057be417eede943 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Christoph=20M=C3=BCllner?= Date: Mon, 5 Dec 2022 14:03:36 +0100 Subject: [PATCH] riscv: attr: Synchronize comments with code MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The comment above the enumeration of existing attributes got out of order and a few entries were forgotten. This patch synchronizes the comments according to the list. This commit does not include any functional change. gcc/ChangeLog: * config/riscv/riscv.md: Sync comments with code. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index df57e2b..a8bb331 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -220,7 +220,6 @@ ;; mfc transfer from coprocessor ;; const load constant ;; arith integer arithmetic instructions -;; auipc integer addition to PC ;; logical integer logical instructions ;; shift integer shift instructions ;; slt set less than instructions @@ -236,9 +235,13 @@ ;; fcvt floating point convert ;; fsqrt floating point square root ;; multi multiword sequence (or user asm statements) +;; auipc integer addition to PC +;; sfb_alu SFB ALU instruction ;; nop no operation ;; ghost an instruction that produces no real code ;; bitmanip bit manipulation instructions +;; rotate rotation instructions +;; atomic atomic instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read -- 2.7.4