From 387e818cda0ffde86f624228c3da1ab28f453685 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 30 Mar 2022 10:21:16 +0200 Subject: [PATCH] store-merging: Avoid ICEs on roughly ~0ULL/8 sized stores [PR105094] On the following testcase on 64-bit targets, store-merging sees a MEM_REF store from {} ctor with "negative" bitsize where bitoff + bitsize wraps around to very small end offset. This later confuses the code so that it allocates just a few bytes of memory but fills in huge amounts of it. Later on there is a param_store_merging_max_size size check but due to the wrap-around we pass that. The following patch punts on such large bitsizes. 2022-03-30 Jakub Jelinek PR tree-optimization/105094 * gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if bitsize <= 0 rather than just == 0. * gcc.dg/pr105094.c: New test. --- gcc/gimple-ssa-store-merging.cc | 2 +- gcc/testsuite/gcc.dg/pr105094.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/pr105094.c diff --git a/gcc/gimple-ssa-store-merging.cc b/gcc/gimple-ssa-store-merging.cc index e2e2157..b952ce5 100644 --- a/gcc/gimple-ssa-store-merging.cc +++ b/gcc/gimple-ssa-store-merging.cc @@ -4940,7 +4940,7 @@ mem_valid_for_store_merging (tree mem, poly_uint64 *pbitsize, tree base_addr = get_inner_reference (mem, &bitsize, &bitpos, &offset, &mode, &unsignedp, &reversep, &volatilep); *pbitsize = bitsize; - if (known_eq (bitsize, 0)) + if (known_le (bitsize, 0)) return NULL_TREE; if (TREE_CODE (mem) == COMPONENT_REF diff --git a/gcc/testsuite/gcc.dg/pr105094.c b/gcc/testsuite/gcc.dg/pr105094.c new file mode 100644 index 0000000..da6dc17 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr105094.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/105094 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct S { short a; char b[~(__SIZE_TYPE__)0 / __CHAR_BIT__ - 1]; }; +void bar (struct S *); + +void +foo (void) +{ + struct S s = { 5 }; + bar (&s); +} -- 2.7.4