From 386b8ddd5f255c560efcadb650e90ceac537b98f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 17 Feb 2018 21:29:45 +0000 Subject: [PATCH] [MIPS][MSA] Convert vector integer min/max opcodes to use generic implementation Found while investigating D43338 Simon^3 - the LLVM project needs more Simons. Differential Revision: https://reviews.llvm.org/D43433 llvm-svn: 325447 --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 4 -- llvm/lib/Target/Mips/MipsISelLowering.h | 6 --- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 72 +++++++++++++---------------- llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 61 ++++++------------------ 4 files changed, 45 insertions(+), 98 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 3d383b3..f739f9a 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -286,10 +286,6 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; - case MipsISD::VSMAX: return "MipsISD::VSMAX"; - case MipsISD::VSMIN: return "MipsISD::VSMIN"; - case MipsISD::VUMAX: return "MipsISD::VUMAX"; - case MipsISD::VUMIN: return "MipsISD::VUMIN"; case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; case MipsISD::VNOR: return "MipsISD::VNOR"; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index ce4f037..f17faff 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -217,12 +217,6 @@ class TargetRegisterClass; VCLT_S, VCLT_U, - // Element-wise vector max/min. - VSMAX, - VSMIN, - VUMAX, - VUMIN, - // Vector Shuffle with mask as an operand VSHF, // Generic shuffle SHF, // 4-element set shuffle. diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index bf79f0f..7c56bc7 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -35,14 +35,6 @@ def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; -def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, - [SDNPCommutative, SDNPAssociative]>; -def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, - [SDNPCommutative, SDNPAssociative]>; -def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, - [SDNPCommutative, SDNPAssociative]>; -def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, - [SDNPCommutative, SDNPAssociative]>; def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; @@ -2350,32 +2342,32 @@ class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; -class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; -class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; -class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; -class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; +class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; +class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; +class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; +class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; -class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; -class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; -class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; -class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; +class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; +class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; +class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; +class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; -class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, +class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, MSA128BOpnd>; -class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, +class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, MSA128HOpnd>; -class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, +class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, MSA128WOpnd>; -class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, +class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, MSA128DOpnd>; -class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, +class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, MSA128BOpnd>; -class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, +class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, MSA128HOpnd>; -class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, +class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, MSA128WOpnd>; -class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, +class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, MSA128DOpnd>; class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; @@ -2383,32 +2375,32 @@ class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; -class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; -class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; -class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; -class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; +class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; +class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; +class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; +class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; -class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; -class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; -class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; -class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; +class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; +class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; +class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; +class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; -class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, +class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, MSA128BOpnd>; -class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, +class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, MSA128HOpnd>; -class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, +class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, MSA128WOpnd>; -class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, +class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, MSA128DOpnd>; -class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, +class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, MSA128BOpnd>; -class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, +class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, MSA128HOpnd>; -class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, +class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, MSA128WOpnd>; -class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, +class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, MSA128DOpnd>; class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index f7d7e2a..deb65bc 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -331,8 +331,12 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::SRA, Ty, Legal); setOperationAction(ISD::SRL, Ty, Legal); setOperationAction(ISD::SUB, Ty, Legal); + setOperationAction(ISD::SMAX, Ty, Legal); + setOperationAction(ISD::SMIN, Ty, Legal); setOperationAction(ISD::UDIV, Ty, Legal); setOperationAction(ISD::UREM, Ty, Legal); + setOperationAction(ISD::UMAX, Ty, Legal); + setOperationAction(ISD::UMIN, Ty, Legal); setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); setOperationAction(ISD::VSELECT, Ty, Legal); setOperationAction(ISD::XOR, Ty, Legal); @@ -890,46 +894,7 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { EVT Ty = N->getValueType(0); - if (Ty.is128BitVector() && Ty.isInteger()) { - // Try the following combines: - // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) - // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) - // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) - // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) - // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) - // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) - // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) - // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) - // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but - // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the - // legalizer. - SDValue Op0 = N->getOperand(0); - - if (Op0->getOpcode() != ISD::SETCC) - return SDValue(); - - ISD::CondCode CondCode = cast(Op0->getOperand(2))->get(); - bool Signed; - - if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) - Signed = true; - else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) - Signed = false; - else - return SDValue(); - - SDValue Op1 = N->getOperand(1); - SDValue Op2 = N->getOperand(2); - SDValue Op0Op0 = Op0->getOperand(0); - SDValue Op0Op1 = Op0->getOperand(1); - - if (Op1 == Op0Op0 && Op2 == Op0Op1) - return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), - Ty, Op1, Op2); - else if (Op1 == Op0Op1 && Op2 == Op0Op0) - return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), - Ty, Op1, Op2); - } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { + if (Ty == MVT::v2i16 || Ty == MVT::v4i8) { SDValue SetCC = N->getOperand(0); if (SetCC.getOpcode() != MipsISD::SETCC_DSP) @@ -1919,49 +1884,49 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_max_s_h: case Intrinsic::mips_max_s_w: case Intrinsic::mips_max_s_d: - return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); case Intrinsic::mips_max_u_b: case Intrinsic::mips_max_u_h: case Intrinsic::mips_max_u_w: case Intrinsic::mips_max_u_d: - return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); case Intrinsic::mips_maxi_s_b: case Intrinsic::mips_maxi_s_h: case Intrinsic::mips_maxi_s_w: case Intrinsic::mips_maxi_s_d: - return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); case Intrinsic::mips_maxi_u_b: case Intrinsic::mips_maxi_u_h: case Intrinsic::mips_maxi_u_w: case Intrinsic::mips_maxi_u_d: - return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); case Intrinsic::mips_min_s_b: case Intrinsic::mips_min_s_h: case Intrinsic::mips_min_s_w: case Intrinsic::mips_min_s_d: - return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); case Intrinsic::mips_min_u_b: case Intrinsic::mips_min_u_h: case Intrinsic::mips_min_u_w: case Intrinsic::mips_min_u_d: - return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); case Intrinsic::mips_mini_s_b: case Intrinsic::mips_mini_s_h: case Intrinsic::mips_mini_s_w: case Intrinsic::mips_mini_s_d: - return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); case Intrinsic::mips_mini_u_b: case Intrinsic::mips_mini_u_h: case Intrinsic::mips_mini_u_w: case Intrinsic::mips_mini_u_d: - return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); case Intrinsic::mips_mod_s_b: case Intrinsic::mips_mod_s_h: -- 2.7.4