From 3856512334ee525d5c922b0480b7503210cc4bb3 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Thu, 5 Sep 2019 16:58:18 +0000 Subject: [PATCH] [x86] add test for horizontal math bug (PR43225); NFC llvm-svn: 371088 --- .../test/CodeGen/X86/haddsub-shuf-undef-operand.ll | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 llvm/test/CodeGen/X86/haddsub-shuf-undef-operand.ll diff --git a/llvm/test/CodeGen/X86/haddsub-shuf-undef-operand.ll b/llvm/test/CodeGen/X86/haddsub-shuf-undef-operand.ll new file mode 100644 index 0000000..3eec47a --- /dev/null +++ b/llvm/test/CodeGen/X86/haddsub-shuf-undef-operand.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s + +; FIXME: Eliminating a shuffle means we have to replace an undef operand of a horizontal op. + +define void @PR43225(<4 x double>* %p0, <4 x double>* %p1, <4 x double> %x, <4 x double> %y, <4 x double> %z) nounwind { +; CHECK-LABEL: PR43225: +; CHECK: # %bb.0: +; CHECK-NEXT: vmovaps (%rdi), %ymm0 +; CHECK-NEXT: vmovapd (%rsi), %ymm0 +; CHECK-NEXT: vhsubpd %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: vmovapd %ymm0, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq + %t39 = load volatile <4 x double>, <4 x double>* %p0, align 32 + %shuffle11 = shufflevector <4 x double> %t39, <4 x double> %x, <4 x i32> + %t40 = load volatile <4 x double>, <4 x double>* %p1, align 32 + %t41 = tail call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %shuffle11, <4 x double> %t40) + %t42 = tail call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %z, <4 x double> %t41) + %shuffle12 = shufflevector <4 x double> %t42, <4 x double> undef, <4 x i32> + store volatile <4 x double> %shuffle12, <4 x double>* %p0, align 32 + ret void +} + +declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) +declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) -- 2.7.4