From 37cd4d0f42c31cc0c933069e528e65deaeb94477 Mon Sep 17 00:00:00 2001 From: Marek Olsak Date: Tue, 3 Feb 2015 21:53:27 +0000 Subject: [PATCH] R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT tests llvm-svn: 228040 --- llvm/test/CodeGen/R600/128bit-kernel-args.ll | 34 +- llvm/test/CodeGen/R600/64bit-kernel-args.ll | 10 +- llvm/test/CodeGen/R600/add.ll | 144 ++--- llvm/test/CodeGen/R600/bfi_int.ll | 32 +- llvm/test/CodeGen/R600/build_vector.ll | 46 +- llvm/test/CodeGen/R600/call_fs.ll | 16 +- llvm/test/CodeGen/R600/cf_end.ll | 10 +- llvm/test/CodeGen/R600/elf.ll | 30 +- llvm/test/CodeGen/R600/elf.r600.ll | 18 +- llvm/test/CodeGen/R600/input-mods.ll | 18 +- llvm/test/CodeGen/R600/kernel-args.ll | 536 +++++++++--------- llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 14 +- llvm/test/CodeGen/R600/llvm.exp2.ll | 92 ++-- llvm/test/CodeGen/R600/llvm.log2.ll | 92 ++-- llvm/test/CodeGen/R600/llvm.sqrt.ll | 60 +-- llvm/test/CodeGen/R600/load.ll | 598 ++++++++++----------- llvm/test/CodeGen/R600/load.vec.ll | 22 +- llvm/test/CodeGen/R600/local-memory-two-objects.ll | 32 +- llvm/test/CodeGen/R600/r600-encoding.ll | 12 +- llvm/test/CodeGen/R600/shl.ll | 246 ++++----- llvm/test/CodeGen/R600/sra.ll | 286 +++++----- llvm/test/CodeGen/R600/store.ll | 316 +++++------ llvm/test/CodeGen/R600/store.r600.ll | 10 +- llvm/test/CodeGen/R600/swizzle-export.ll | 18 +- llvm/test/CodeGen/R600/udiv.ll | 28 +- llvm/test/CodeGen/R600/vertex-fetch-encoding.ll | 16 +- llvm/test/CodeGen/R600/vselect.ll | 60 +-- llvm/test/CodeGen/R600/zero_extend.ll | 32 +- 28 files changed, 1414 insertions(+), 1414 deletions(-) diff --git a/llvm/test/CodeGen/R600/128bit-kernel-args.ll b/llvm/test/CodeGen/R600/128bit-kernel-args.ll index 2d7740b..557d86a 100644 --- a/llvm/test/CodeGen/R600/128bit-kernel-args.ll +++ b/llvm/test/CodeGen/R600/128bit-kernel-args.ll @@ -1,27 +1,27 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI -; R600-CHECK: {{^}}v4i32_kernel_arg: -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X -; SI-CHECK: {{^}}v4i32_kernel_arg: -; SI-CHECK: buffer_store_dwordx4 +; R600: {{^}}v4i32_kernel_arg: +; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y +; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z +; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W +; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X +; SI: {{^}}v4i32_kernel_arg: +; SI: buffer_store_dwordx4 define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out ret void } -; R600-CHECK: {{^}}v4f32_kernel_arg: -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W -; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X -; SI-CHECK: {{^}}v4f32_kernel_arg: -; SI-CHECK: buffer_store_dwordx4 +; R600: {{^}}v4f32_kernel_arg: +; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y +; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z +; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W +; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X +; SI: {{^}}v4f32_kernel_arg: +; SI: buffer_store_dwordx4 define void @v4f32_kernel_arg(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/64bit-kernel-args.ll b/llvm/test/CodeGen/R600/64bit-kernel-args.ll index 02b6f34..9f2738e 100644 --- a/llvm/test/CodeGen/R600/64bit-kernel-args.ll +++ b/llvm/test/CodeGen/R600/64bit-kernel-args.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI -; SI-CHECK: {{^}}f64_kernel_arg: -; SI-CHECK-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9 -; SI-CHECK-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb -; SI-CHECK: buffer_store_dwordx2 +; SI: {{^}}f64_kernel_arg: +; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9 +; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb +; SI: buffer_store_dwordx2 define void @f64_kernel_arg(double addrspace(1)* %out, double %in) { entry: store double %in, double addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/add.ll b/llvm/test/CodeGen/R600/add.ll index 850f376..3a8b97c 100644 --- a/llvm/test/CodeGen/R600/add.ll +++ b/llvm/test/CodeGen/R600/add.ll @@ -1,13 +1,13 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ;FUNC-LABEL: {{^}}test1: -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} -;SI-CHECK-NOT: [[REG]] -;SI-CHECK: buffer_store_dword [[REG]], +;SI: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} +;SI-NOT: [[REG]] +;SI: buffer_store_dword [[REG]], define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 %a = load i32 addrspace(1)* %in @@ -18,11 +18,11 @@ define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { } ;FUNC-LABEL: {{^}}test2: -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -34,15 +34,15 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { } ;FUNC-LABEL: {{^}}test4: -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -54,22 +54,22 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}test8: -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { entry: %0 = add <8 x i32> %a, %b @@ -78,38 +78,38 @@ entry: } ; FUNC-LABEL: {{^}}test16: -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; EG-CHECK: ADD_INT -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 -; SI-CHECK: s_add_i32 +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; EG: ADD_INT +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 +; SI: s_add_i32 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { entry: %0 = add <16 x i32> %a, %b @@ -118,8 +118,8 @@ entry: } ; FUNC-LABEL: {{^}}add64: -; SI-CHECK: s_add_u32 -; SI-CHECK: s_addc_u32 +; SI: s_add_u32 +; SI: s_addc_u32 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = add i64 %a, %b @@ -133,7 +133,7 @@ entry: ; to a VGPR before doing the add. ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: -; SI-CHECK-NOT: v_addc_u32_e32 s +; SI-NOT: v_addc_u32_e32 s define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -144,8 +144,8 @@ entry: ; Test i64 add inside a branch. ; FUNC-LABEL: {{^}}add64_in_branch: -; SI-CHECK: s_add_u32 -; SI-CHECK: s_addc_u32 +; SI: s_add_u32 +; SI: s_addc_u32 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 diff --git a/llvm/test/CodeGen/R600/bfi_int.ll b/llvm/test/CodeGen/R600/bfi_int.ll index 8e1c7db..0334934 100644 --- a/llvm/test/CodeGen/R600/bfi_int.ll +++ b/llvm/test/CodeGen/R600/bfi_int.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s ; BFI_INT Definition pattern from ISA docs ; (y & x) | (z & ~x) ; -; R600-CHECK: {{^}}bfi_def: -; R600-CHECK: BFI_INT -; SI-CHECK: @bfi_def -; SI-CHECK: v_bfi_b32 +; R600: {{^}}bfi_def: +; R600: BFI_INT +; SI: @bfi_def +; SI: v_bfi_b32 define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: %0 = xor i32 %x, -1 @@ -21,10 +21,10 @@ entry: ; SHA-256 Ch function ; z ^ (x & (y ^ z)) -; R600-CHECK: {{^}}bfi_sha256_ch: -; R600-CHECK: BFI_INT -; SI-CHECK: @bfi_sha256_ch -; SI-CHECK: v_bfi_b32 +; R600: {{^}}bfi_sha256_ch: +; R600: BFI_INT +; SI: @bfi_sha256_ch +; SI: v_bfi_b32 define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: %0 = xor i32 %y, %z @@ -36,11 +36,11 @@ entry: ; SHA-256 Ma function ; ((x & z) | (y & (x | z))) -; R600-CHECK: {{^}}bfi_sha256_ma: -; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W -; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W -; SI-CHECK: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}} -; SI-CHECK: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}} +; R600: {{^}}bfi_sha256_ma: +; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W +; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W +; SI: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}} +; SI: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}} define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: diff --git a/llvm/test/CodeGen/R600/build_vector.ll b/llvm/test/CodeGen/R600/build_vector.ll index f5089f3..65eacf5 100644 --- a/llvm/test/CodeGen/R600/build_vector.ll +++ b/llvm/test/CodeGen/R600/build_vector.ll @@ -1,33 +1,33 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI -; R600-CHECK: {{^}}build_vector2: -; R600-CHECK: MOV -; R600-CHECK: MOV -; R600-CHECK-NOT: MOV -; SI-CHECK: {{^}}build_vector2: -; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} +; R600: {{^}}build_vector2: +; R600: MOV +; R600: MOV +; R600-NOT: MOV +; SI: {{^}}build_vector2: +; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} define void @build_vector2 (<2 x i32> addrspace(1)* %out) { entry: store <2 x i32> , <2 x i32> addrspace(1)* %out ret void } -; R600-CHECK: {{^}}build_vector4: -; R600-CHECK: MOV -; R600-CHECK: MOV -; R600-CHECK: MOV -; R600-CHECK: MOV -; R600-CHECK-NOT: MOV -; SI-CHECK: {{^}}build_vector4: -; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 -; SI-CHECK-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 -; SI-CHECK: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} +; R600: {{^}}build_vector4: +; R600: MOV +; R600: MOV +; R600: MOV +; R600: MOV +; R600-NOT: MOV +; SI: {{^}}build_vector4: +; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 +; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 +; SI: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} define void @build_vector4 (<4 x i32> addrspace(1)* %out) { entry: store <4 x i32> , <4 x i32> addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/call_fs.ll b/llvm/test/CodeGen/R600/call_fs.ll index 7df2240..db2cb6e5 100644 --- a/llvm/test/CodeGen/R600/call_fs.ll +++ b/llvm/test/CodeGen/R600/call_fs.ll @@ -1,13 +1,13 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s -; EG-CHECK: {{^}}call_fs: -; EG-CHECK: .long 257 -; EG-CHECK: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84] -; R600-CHECK: {{^}}call_fs: -; R600-CHECK: .long 257 -; R600-CHECK:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89] +; EG: {{^}}call_fs: +; EG: .long 257 +; EG: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84] +; R600: {{^}}call_fs: +; R600: .long 257 +; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89] define void @call_fs() #0 { diff --git a/llvm/test/CodeGen/R600/cf_end.ll b/llvm/test/CodeGen/R600/cf_end.ll index 138004d..c74ee22 100644 --- a/llvm/test/CodeGen/R600/cf_end.ll +++ b/llvm/test/CodeGen/R600/cf_end.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM %s -; EG-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80] -; CM-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88] +; EG: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80] +; CM: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88] define void @eop() { ret void } diff --git a/llvm/test/CodeGen/R600/elf.ll b/llvm/test/CodeGen/R600/elf.ll index d197967..aca3109 100644 --- a/llvm/test/CodeGen/R600/elf.ll +++ b/llvm/test/CodeGen/R600/elf.ll @@ -1,21 +1,21 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s -; ELF-CHECK: Format: ELF32 -; ELF-CHECK: Name: .AMDGPU.config -; ELF-CHECK: Type: SHT_PROGBITS +; ELF: Format: ELF32 +; ELF: Name: .AMDGPU.config +; ELF: Type: SHT_PROGBITS -; ELF-CHECK: Symbol { -; ELF-CHECK: Name: test -; ELF-CHECK: Binding: Global +; ELF: Symbol { +; ELF: Name: test +; ELF: Binding: Global -; CONFIG-CHECK: .align 256 -; CONFIG-CHECK: test: -; CONFIG-CHECK: .section .AMDGPU.config -; CONFIG-CHECK-NEXT: .long 45096 -; CONFIG-CHECK-NEXT: .long 0 +; CONFIG: .align 256 +; CONFIG: test: +; CONFIG: .section .AMDGPU.config +; CONFIG-NEXT: .long 45096 +; CONFIG-NEXT: .long 0 define void @test(i32 %p) #0 { %i = add i32 %p, 2 %r = bitcast i32 %i to float diff --git a/llvm/test/CodeGen/R600/elf.r600.ll b/llvm/test/CodeGen/R600/elf.r600.ll index 4436c07..51cd085 100644 --- a/llvm/test/CodeGen/R600/elf.r600.ll +++ b/llvm/test/CodeGen/R600/elf.r600.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s -; ELF-CHECK: Format: ELF32 -; ELF-CHECK: Name: .AMDGPU.config +; ELF: Format: ELF32 +; ELF: Name: .AMDGPU.config -; CONFIG-CHECK: .section .AMDGPU.config -; CONFIG-CHECK-NEXT: .long 166100 -; CONFIG-CHECK-NEXT: .long 2 -; CONFIG-CHECK-NEXT: .long 165900 -; CONFIG-CHECK-NEXT: .long 0 +; CONFIG: .section .AMDGPU.config +; CONFIG-NEXT: .long 166100 +; CONFIG-NEXT: .long 2 +; CONFIG-NEXT: .long 165900 +; CONFIG-NEXT: .long 0 define void @test(float addrspace(1)* %out, i32 %p) { %i = add i32 %p, 2 %r = bitcast i32 %i to float diff --git a/llvm/test/CodeGen/R600/input-mods.ll b/llvm/test/CodeGen/R600/input-mods.ll index e3e9499..1c4d285 100644 --- a/llvm/test/CodeGen/R600/input-mods.ll +++ b/llvm/test/CodeGen/R600/input-mods.ll @@ -1,13 +1,13 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK -;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG +;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM -;EG-CHECK-LABEL: {{^}}test: -;EG-CHECK: EXP_IEEE * -;CM-CHECK-LABEL: {{^}}test: -;CM-CHECK: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X| -;CM-CHECK: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X| -;CM-CHECK: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X| -;CM-CHECK: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X| +;EG-LABEL: {{^}}test: +;EG: EXP_IEEE * +;CM-LABEL: {{^}}test: +;CM: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X| +;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X| +;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X| +;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X| define void @test(<4 x float> inreg %reg0) #0 { %r0 = extractelement <4 x float> %reg0, i32 0 diff --git a/llvm/test/CodeGen/R600/kernel-args.ll b/llvm/test/CodeGen/R600/kernel-args.ll index 1984d33..42d289d 100644 --- a/llvm/test/CodeGen/R600/kernel-args.ll +++ b/llvm/test/CodeGen/R600/kernel-args.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI -; EG-CHECK-LABEL: {{^}}i8_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i8_arg: -; SI-CHECK: buffer_load_ubyte +; EG-LABEL: {{^}}i8_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i8_arg: +; SI: buffer_load_ubyte define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { entry: @@ -14,10 +14,10 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i8_zext_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i8_zext_arg: -; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb +; EG-LABEL: {{^}}i8_zext_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i8_zext_arg: +; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { entry: @@ -26,10 +26,10 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i8_sext_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i8_sext_arg: -; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb +; EG-LABEL: {{^}}i8_sext_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i8_sext_arg: +; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { entry: @@ -38,10 +38,10 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i16_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i16_arg: -; SI-CHECK: buffer_load_ushort +; EG-LABEL: {{^}}i16_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i16_arg: +; SI: buffer_load_ushort define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { entry: @@ -50,10 +50,10 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i16_zext_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i16_zext_arg: -; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb +; EG-LABEL: {{^}}i16_zext_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i16_zext_arg: +; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { entry: @@ -62,10 +62,10 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i16_sext_arg: -; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i16_sext_arg: -; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb +; EG-LABEL: {{^}}i16_sext_arg: +; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i16_sext_arg: +; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { entry: @@ -74,9 +74,9 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}i32_arg: -; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}i32_arg: +; EG-LABEL: {{^}}i32_arg: +; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}i32_arg: ; s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { entry: @@ -84,9 +84,9 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}f32_arg: -; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z -; SI-CHECK-LABEL: {{^}}f32_arg: +; EG-LABEL: {{^}}f32_arg: +; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; SI-LABEL: {{^}}f32_arg: ; s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { entry: @@ -94,360 +94,360 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}v2i8_arg: -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; SI-CHECK-LABEL: {{^}}v2i8_arg: -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; EG-LABEL: {{^}}v2i8_arg: +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; SI-LABEL: {{^}}v2i8_arg: +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) { entry: store <2 x i8> %in, <2 x i8> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v2i16_arg: -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; SI-CHECK-LABEL: {{^}}v2i16_arg: -; SI-CHECK-DAG: buffer_load_ushort -; SI-CHECK-DAG: buffer_load_ushort +; EG-LABEL: {{^}}v2i16_arg: +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; SI-LABEL: {{^}}v2i16_arg: +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v2i32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W -; SI-CHECK-LABEL: {{^}}v2i32_arg: -; SI-CHECK: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb +; EG-LABEL: {{^}}v2i32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; SI-LABEL: {{^}}v2i32_arg: +; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { entry: store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v2f32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W -; SI-CHECK-LABEL: {{^}}v2f32_arg: -; SI-CHECK: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb +; EG-LABEL: {{^}}v2f32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; SI-LABEL: {{^}}v2f32_arg: +; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { entry: store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v3i8_arg: +; EG-LABEL: {{^}}v3i8_arg: ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 -; SI-CHECK-LABEL: {{^}}v3i8_arg: +; SI-LABEL: {{^}}v3i8_arg: define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind { entry: store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v3i16_arg: +; EG-LABEL: {{^}}v3i16_arg: ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 -; SI-CHECK-LABEL: {{^}}v3i16_arg: +; SI-LABEL: {{^}}v3i16_arg: define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind { entry: store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v3i32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; SI-CHECK-LABEL: {{^}}v3i32_arg: -; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd +; EG-LABEL: {{^}}v3i32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; SI-LABEL: {{^}}v3i32_arg: +; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { entry: store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v3f32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; SI-CHECK-LABEL: {{^}}v3f32_arg: -; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd +; EG-LABEL: {{^}}v3f32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; SI-LABEL: {{^}}v3f32_arg: +; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { entry: store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v4i8_arg: -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; SI-CHECK-LABEL: {{^}}v4i8_arg: -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; EG-LABEL: {{^}}v4i8_arg: +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; SI-LABEL: {{^}}v4i8_arg: +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v4i16_arg: -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; SI-CHECK-LABEL: {{^}}v4i16_arg: -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort +; EG-LABEL: {{^}}v4i16_arg: +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; SI-LABEL: {{^}}v4i16_arg: +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { entry: store <4 x i16> %in, <4 x i16> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v4i32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X -; SI-CHECK-LABEL: {{^}}v4i32_arg: -; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd +; EG-LABEL: {{^}}v4i32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; SI-LABEL: {{^}}v4i32_arg: +; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v4f32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X -; SI-CHECK-LABEL: {{^}}v4f32_arg: -; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd +; EG-LABEL: {{^}}v4f32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; SI-LABEL: {{^}}v4f32_arg: +; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v8i8_arg: -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; SI-CHECK-LABEL: {{^}}v8i8_arg: -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; EG-LABEL: {{^}}v8i8_arg: +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; SI-LABEL: {{^}}v8i8_arg: +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) { entry: store <8 x i8> %in, <8 x i8> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v8i16_arg: -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; SI-CHECK-LABEL: {{^}}v8i16_arg: -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort +; EG-LABEL: {{^}}v8i16_arg: +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; SI-LABEL: {{^}}v8i16_arg: +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { entry: store <8 x i16> %in, <8 x i16> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v8i32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X -; SI-CHECK-LABEL: {{^}}v8i32_arg: -; SI-CHECK: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 +; EG-LABEL: {{^}}v8i32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; SI-LABEL: {{^}}v8i32_arg: +; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { entry: store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v8f32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X -; SI-CHECK-LABEL: {{^}}v8f32_arg: -; SI-CHECK: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 +; EG-LABEL: {{^}}v8f32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; SI-LABEL: {{^}}v8f32_arg: +; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { entry: store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v16i8_arg: -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; EG-CHECK: VTX_READ_8 -; SI-CHECK-LABEL: {{^}}v16i8_arg: -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; EG-LABEL: {{^}}v16i8_arg: +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; SI-LABEL: {{^}}v16i8_arg: +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) { entry: store <16 x i8> %in, <16 x i8> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v16i16_arg: -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; EG-CHECK: VTX_READ_16 -; SI-CHECK-LABEL: {{^}}v16i16_arg: -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort +; EG-LABEL: {{^}}v16i16_arg: +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; SI-LABEL: {{^}}v16i16_arg: +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { entry: store <16 x i16> %in, <16 x i16> addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}v16i32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X -; SI-CHECK-LABEL: {{^}}v16i32_arg: -; SI-CHECK: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 +; EG-LABEL: {{^}}v16i32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; SI-LABEL: {{^}}v16i32_arg: +; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { entry: store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 ret void } -; EG-CHECK-LABEL: {{^}}v16f32_arg: -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X -; SI-CHECK-LABEL: {{^}}v16f32_arg: -; SI-CHECK: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 +; EG-LABEL: {{^}}v16f32_arg: +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; SI-LABEL: {{^}}v16f32_arg: +; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { entry: store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index 60b693e..74792e5 100644 --- a/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s -; R600-CHECK: {{^}}amdgpu_trunc: -; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI-CHECK: {{^}}amdgpu_trunc: -; SI-CHECK: v_trunc_f32 +; R600: {{^}}amdgpu_trunc: +; R600: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI: {{^}}amdgpu_trunc: +; SI: v_trunc_f32 define void @amdgpu_trunc(float addrspace(1)* %out, float %x) { entry: diff --git a/llvm/test/CodeGen/R600/llvm.exp2.ll b/llvm/test/CodeGen/R600/llvm.exp2.ll index a2aa4f7..4269892 100644 --- a/llvm/test/CodeGen/R600/llvm.exp2.ll +++ b/llvm/test/CodeGen/R600/llvm.exp2.ll @@ -1,15 +1,15 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC +;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI --check-prefix=FUNC +;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;FUNC-LABEL: {{^}}test: -;EG-CHECK: EXP_IEEE -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_exp_f32 +;EG: EXP_IEEE +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_exp_f32 define void @test(float addrspace(1)* %out, float %in) { entry: @@ -19,20 +19,20 @@ entry: } ;FUNC-LABEL: {{^}}testv2: -;EG-CHECK: EXP_IEEE -;EG-CHECK: EXP_IEEE +;EG: EXP_IEEE +;EG: EXP_IEEE ; FIXME: We should be able to merge these packets together on Cayman so we ; have a maximum of 4 instructions. -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_exp_f32 -;SI-CHECK: v_exp_f32 +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_exp_f32 +;SI: v_exp_f32 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: @@ -42,32 +42,32 @@ entry: } ;FUNC-LABEL: {{^}}testv4: -;EG-CHECK: EXP_IEEE -;EG-CHECK: EXP_IEEE -;EG-CHECK: EXP_IEEE -;EG-CHECK: EXP_IEEE +;EG: EXP_IEEE +;EG: EXP_IEEE +;EG: EXP_IEEE +;EG: EXP_IEEE ; FIXME: We should be able to merge these packets together on Cayman so we ; have a maximum of 4 instructions. -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_exp_f32 -;SI-CHECK: v_exp_f32 -;SI-CHECK: v_exp_f32 -;SI-CHECK: v_exp_f32 +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_exp_f32 +;SI: v_exp_f32 +;SI: v_exp_f32 +;SI: v_exp_f32 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in) diff --git a/llvm/test/CodeGen/R600/llvm.log2.ll b/llvm/test/CodeGen/R600/llvm.log2.ll index e4bfab9..c75e785 100644 --- a/llvm/test/CodeGen/R600/llvm.log2.ll +++ b/llvm/test/CodeGen/R600/llvm.log2.ll @@ -1,15 +1,15 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC +;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI --check-prefix=FUNC +;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;FUNC-LABEL: {{^}}test: -;EG-CHECK: LOG_IEEE -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_log_f32 +;EG: LOG_IEEE +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_log_f32 define void @test(float addrspace(1)* %out, float %in) { entry: @@ -19,20 +19,20 @@ entry: } ;FUNC-LABEL: {{^}}testv2: -;EG-CHECK: LOG_IEEE -;EG-CHECK: LOG_IEEE +;EG: LOG_IEEE +;EG: LOG_IEEE ; FIXME: We should be able to merge these packets together on Cayman so we ; have a maximum of 4 instructions. -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_log_f32 -;SI-CHECK: v_log_f32 +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_log_f32 +;SI: v_log_f32 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: @@ -42,32 +42,32 @@ entry: } ;FUNC-LABEL: {{^}}testv4: -;EG-CHECK: LOG_IEEE -;EG-CHECK: LOG_IEEE -;EG-CHECK: LOG_IEEE -;EG-CHECK: LOG_IEEE +;EG: LOG_IEEE +;EG: LOG_IEEE +;EG: LOG_IEEE +;EG: LOG_IEEE ; FIXME: We should be able to merge these packets together on Cayman so we ; have a maximum of 4 instructions. -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: v_log_f32 -;SI-CHECK: v_log_f32 -;SI-CHECK: v_log_f32 -;SI-CHECK: v_log_f32 +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +;SI: v_log_f32 +;SI: v_log_f32 +;SI: v_log_f32 +;SI: v_log_f32 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in) diff --git a/llvm/test/CodeGen/R600/llvm.sqrt.ll b/llvm/test/CodeGen/R600/llvm.sqrt.ll index d337bb5..cc4717a 100644 --- a/llvm/test/CodeGen/R600/llvm.sqrt.ll +++ b/llvm/test/CodeGen/R600/llvm.sqrt.ll @@ -1,12 +1,12 @@ -; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=amdgcn --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI-CHECK -; RUN: llc < %s -march=amdgcn --mcpu=tonga -verify-machineinstrs| FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600 +; RUN: llc < %s -march=amdgcn --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=amdgcn --mcpu=tonga -verify-machineinstrs| FileCheck %s --check-prefix=SI -; R600-CHECK-LABEL: {{^}}sqrt_f32: -; R600-CHECK: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z -; R600-CHECK: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS -; SI-CHECK-LABEL: {{^}}sqrt_f32: -; SI-CHECK: v_sqrt_f32_e32 +; R600-LABEL: {{^}}sqrt_f32: +; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z +; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS +; SI-LABEL: {{^}}sqrt_f32: +; SI: v_sqrt_f32_e32 define void @sqrt_f32(float addrspace(1)* %out, float %in) { entry: %0 = call float @llvm.sqrt.f32(float %in) @@ -14,14 +14,14 @@ entry: ret void } -; R600-CHECK-LABEL: {{^}}sqrt_v2f32: -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS -; SI-CHECK-LABEL: {{^}}sqrt_v2f32: -; SI-CHECK: v_sqrt_f32_e32 -; SI-CHECK: v_sqrt_f32_e32 +; R600-LABEL: {{^}}sqrt_v2f32: +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS +; SI-LABEL: {{^}}sqrt_v2f32: +; SI: v_sqrt_f32_e32 +; SI: v_sqrt_f32_e32 define void @sqrt_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: %0 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) @@ -29,20 +29,20 @@ entry: ret void } -; R600-CHECK-LABEL: {{^}}sqrt_v4f32: -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].W -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS -; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X -; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS -; SI-CHECK-LABEL: {{^}}sqrt_v4f32: -; SI-CHECK: v_sqrt_f32_e32 -; SI-CHECK: v_sqrt_f32_e32 -; SI-CHECK: v_sqrt_f32_e32 -; SI-CHECK: v_sqrt_f32_e32 +; R600-LABEL: {{^}}sqrt_v4f32: +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].W +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS +; SI-LABEL: {{^}}sqrt_v4f32: +; SI: v_sqrt_f32_e32 +; SI: v_sqrt_f32_e32 +; SI: v_sqrt_f32_e32 +; SI: v_sqrt_f32_e32 define void @sqrt_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) diff --git a/llvm/test/CodeGen/R600/load.ll b/llvm/test/CodeGen/R600/load.ll index 8142cae..b71b7cb 100644 --- a/llvm/test/CodeGen/R600/load.ll +++ b/llvm/test/CodeGen/R600/load.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600 --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ;===------------------------------------------------------------------------===; ; GLOBAL ADDRESS SPACE @@ -9,9 +9,9 @@ ; Load an i8 value from the global address space. ; FUNC-LABEL: {{^}}load_i8: -; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, +; SI: buffer_load_ubyte v{{[0-9]+}}, define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { %1 = load i8 addrspace(1)* %in %2 = zext i8 %1 to i32 @@ -20,12 +20,12 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}load_i8_sext: -; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] -; R600-CHECK: 24 -; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] -; R600-CHECK: 24 -; SI-CHECK: buffer_load_sbyte +; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600: 24 +; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600: 24 +; SI: buffer_load_sbyte define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = load i8 addrspace(1)* %in @@ -35,10 +35,10 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i8: -; R600-CHECK: VTX_READ_8 -; R600-CHECK: VTX_READ_8 -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; R600: VTX_READ_8 +; R600: VTX_READ_8 +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { entry: %0 = load <2 x i8> addrspace(1)* %in @@ -48,18 +48,18 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i8_sext: -; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] -; R600-CHECK-DAG: 24 -; SI-CHECK: buffer_load_sbyte -; SI-CHECK: buffer_load_sbyte +; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-DAG: 24 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-DAG: 24 +; SI: buffer_load_sbyte +; SI: buffer_load_sbyte define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { entry: %0 = load <2 x i8> addrspace(1)* %in @@ -69,14 +69,14 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i8: -; R600-CHECK: VTX_READ_8 -; R600-CHECK: VTX_READ_8 -; R600-CHECK: VTX_READ_8 -; R600-CHECK: VTX_READ_8 -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte -; SI-CHECK: buffer_load_ubyte +; R600: VTX_READ_8 +; R600: VTX_READ_8 +; R600: VTX_READ_8 +; R600: VTX_READ_8 +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { entry: %0 = load <4 x i8> addrspace(1)* %in @@ -86,30 +86,30 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i8_sext: -; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] -; R600-CHECK-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] -; R600-CHECK-DAG: 24 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] -; R600-CHECK-DAG: 24 -; SI-CHECK: buffer_load_sbyte -; SI-CHECK: buffer_load_sbyte -; SI-CHECK: buffer_load_sbyte -; SI-CHECK: buffer_load_sbyte +; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; R600-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-DAG: 24 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-DAG: 24 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] +; R600-DAG: 24 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] +; R600-DAG: 24 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] +; R600-DAG: 24 +; SI: buffer_load_sbyte +; SI: buffer_load_sbyte +; SI: buffer_load_sbyte +; SI: buffer_load_sbyte define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { entry: %0 = load <4 x i8> addrspace(1)* %in @@ -120,8 +120,8 @@ entry: ; Load an i16 value from the global address space. ; FUNC-LABEL: {{^}}load_i16: -; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ushort +; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI: buffer_load_ushort define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { entry: %0 = load i16 addrspace(1)* %in @@ -131,12 +131,12 @@ entry: } ; FUNC-LABEL: {{^}}load_i16_sext: -; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] -; R600-CHECK: 16 -; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] -; R600-CHECK: 16 -; SI-CHECK: buffer_load_sshort +; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600: 16 +; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600: 16 +; SI: buffer_load_sshort define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { entry: %0 = load i16 addrspace(1)* %in @@ -146,10 +146,10 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i16: -; R600-CHECK: VTX_READ_16 -; R600-CHECK: VTX_READ_16 -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort +; R600: VTX_READ_16 +; R600: VTX_READ_16 +; SI: buffer_load_ushort +; SI: buffer_load_ushort define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { entry: %0 = load <2 x i16> addrspace(1)* %in @@ -159,18 +159,18 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i16_sext: -; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] -; R600-CHECK-DAG: 16 -; SI-CHECK: buffer_load_sshort -; SI-CHECK: buffer_load_sshort +; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-DAG: 16 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-DAG: 16 +; SI: buffer_load_sshort +; SI: buffer_load_sshort define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { entry: %0 = load <2 x i16> addrspace(1)* %in @@ -180,14 +180,14 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i16: -; R600-CHECK: VTX_READ_16 -; R600-CHECK: VTX_READ_16 -; R600-CHECK: VTX_READ_16 -; R600-CHECK: VTX_READ_16 -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort -; SI-CHECK: buffer_load_ushort +; R600: VTX_READ_16 +; R600: VTX_READ_16 +; R600: VTX_READ_16 +; R600: VTX_READ_16 +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_load_ushort define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { entry: %0 = load <4 x i16> addrspace(1)* %in @@ -197,30 +197,30 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i16_sext: -; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] -; R600-CHECK-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] -; R600-CHECK-DAG: 16 -; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] -; R600-CHECK-DAG: 16 -; SI-CHECK: buffer_load_sshort -; SI-CHECK: buffer_load_sshort -; SI-CHECK: buffer_load_sshort -; SI-CHECK: buffer_load_sshort +; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; R600-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-DAG: 16 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-DAG: 16 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] +; R600-DAG: 16 +; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] +; R600-DAG: 16 +; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] +; R600-DAG: 16 +; SI: buffer_load_sshort +; SI: buffer_load_sshort +; SI: buffer_load_sshort +; SI: buffer_load_sshort define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { entry: %0 = load <4 x i16> addrspace(1)* %in @@ -231,9 +231,9 @@ entry: ; load an i32 value from the global address space. ; FUNC-LABEL: {{^}}load_i32: -; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: buffer_load_dword v{{[0-9]+}} +; SI: buffer_load_dword v{{[0-9]+}} define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = load i32 addrspace(1)* %in @@ -243,9 +243,9 @@ entry: ; load a f32 value from the global address space. ; FUNC-LABEL: {{^}}load_f32: -; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: buffer_load_dword v{{[0-9]+}} +; SI: buffer_load_dword v{{[0-9]+}} define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) { entry: %0 = load float addrspace(1)* %in @@ -255,9 +255,9 @@ entry: ; load a v2f32 value from the global address space ; FUNC-LABEL: {{^}}load_v2f32: -; R600-CHECK: MEM_RAT -; R600-CHECK: VTX_READ_64 -; SI-CHECK: buffer_load_dwordx2 +; R600: MEM_RAT +; R600: VTX_READ_64 +; SI: buffer_load_dwordx2 define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) { entry: %0 = load <2 x float> addrspace(1)* %in @@ -266,8 +266,8 @@ entry: } ; FUNC-LABEL: {{^}}load_i64: -; R600-CHECK: VTX_READ_64 -; SI-CHECK: buffer_load_dwordx2 +; R600: VTX_READ_64 +; SI: buffer_load_dwordx2 define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -276,11 +276,11 @@ entry: } ; FUNC-LABEL: {{^}}load_i64_sext: -; R600-CHECK: MEM_RAT -; R600-CHECK: MEM_RAT -; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x -; R600-CHECK: 31 -; SI-CHECK: buffer_load_dword +; R600: MEM_RAT +; R600: MEM_RAT +; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x +; R600: 31 +; SI: buffer_load_dword define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: @@ -291,8 +291,8 @@ entry: } ; FUNC-LABEL: {{^}}load_i64_zext: -; R600-CHECK: MEM_RAT -; R600-CHECK: MEM_RAT +; R600: MEM_RAT +; R600: MEM_RAT define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = load i32 addrspace(1)* %in @@ -302,17 +302,17 @@ entry: } ; FUNC-LABEL: {{^}}load_v8i32: -; R600-CHECK: VTX_READ_128 -; R600-CHECK: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 ; XXX: We should be using DWORDX4 instructions on SI. -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword define void @load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) { entry: %0 = load <8 x i32> addrspace(1)* %in @@ -321,27 +321,27 @@ entry: } ; FUNC-LABEL: {{^}}load_v16i32: -; R600-CHECK: VTX_READ_128 -; R600-CHECK: VTX_READ_128 -; R600-CHECK: VTX_READ_128 -; R600-CHECK: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 ; XXX: We should be using DWORDX4 instructions on SI. -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword -; SI-CHECK: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword define void @load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) { entry: %0 = load <16 x i32> addrspace(1)* %in @@ -355,12 +355,12 @@ entry: ; Load a sign-extended i8 value ; FUNC-LABEL: {{^}}load_const_i8_sext: -; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] -; R600-CHECK: 24 -; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] -; R600-CHECK: 24 -; SI-CHECK: buffer_load_sbyte v{{[0-9]+}}, +; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600: 24 +; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600: 24 +; SI: buffer_load_sbyte v{{[0-9]+}}, define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = load i8 addrspace(2)* %in @@ -371,8 +371,8 @@ entry: ; Load an aligned i8 value ; FUNC-LABEL: {{^}}load_const_i8_aligned: -; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, +; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI: buffer_load_ubyte v{{[0-9]+}}, define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = load i8 addrspace(2)* %in @@ -383,8 +383,8 @@ entry: ; Load an un-aligned i8 value ; FUNC-LABEL: {{^}}load_const_i8_unaligned: -; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, +; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI: buffer_load_ubyte v{{[0-9]+}}, define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = getelementptr i8 addrspace(2)* %in, i32 1 @@ -396,12 +396,12 @@ entry: ; Load a sign-extended i16 value ; FUNC-LABEL: {{^}}load_const_i16_sext: -; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] -; R600-CHECK: 16 -; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] -; R600-CHECK: 16 -; SI-CHECK: buffer_load_sshort +; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600: 16 +; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600: 16 +; SI: buffer_load_sshort define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = load i16 addrspace(2)* %in @@ -412,8 +412,8 @@ entry: ; Load an aligned i16 value ; FUNC-LABEL: {{^}}load_const_i16_aligned: -; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ushort +; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI: buffer_load_ushort define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = load i16 addrspace(2)* %in @@ -424,8 +424,8 @@ entry: ; Load an un-aligned i16 value ; FUNC-LABEL: {{^}}load_const_i16_unaligned: -; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: buffer_load_ushort +; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI: buffer_load_ushort define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = getelementptr i16 addrspace(2)* %in, i32 1 @@ -437,9 +437,9 @@ entry: ; Load an i32 value from the constant address space. ; FUNC-LABEL: {{^}}load_const_addrspace_i32: -; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: s_load_dword s{{[0-9]+}} +; SI: s_load_dword s{{[0-9]+}} define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %0 = load i32 addrspace(2)* %in @@ -449,9 +449,9 @@ entry: ; Load a f32 value from the constant address space. ; FUNC-LABEL: {{^}}load_const_addrspace_f32: -; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: s_load_dword s{{[0-9]+}} +; SI: s_load_dword s{{[0-9]+}} define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { %1 = load float addrspace(2)* %in store float %1, float addrspace(1)* %out @@ -464,10 +464,10 @@ define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace( ; Load an i8 value from the local address space. ; FUNC-LABEL: {{^}}load_i8_local: -; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u8 +; R600: LDS_UBYTE_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u8 define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { %1 = load i8 addrspace(3)* %in %2 = zext i8 %1 to i32 @@ -476,11 +476,11 @@ define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { } ; FUNC-LABEL: {{^}}load_i8_sext_local: -; R600-CHECK: LDS_UBYTE_READ_RET -; R600-CHECK: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i8 +; R600: LDS_UBYTE_READ_RET +; R600: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i8 define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { entry: %0 = load i8 addrspace(3)* %in @@ -490,12 +490,12 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i8_local: -; R600-CHECK: LDS_UBYTE_READ_RET -; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u8 -; SI-CHECK: ds_read_u8 +; R600: LDS_UBYTE_READ_RET +; R600: LDS_UBYTE_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u8 +; SI: ds_read_u8 define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { entry: %0 = load <2 x i8> addrspace(3)* %in @@ -505,14 +505,14 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i8_sext_local: -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i8 -; SI-CHECK: ds_read_i8 +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: ASHR +; R600-DAG: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i8 +; SI: ds_read_i8 define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { entry: %0 = load <2 x i8> addrspace(3)* %in @@ -522,16 +522,16 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i8_local: -; R600-CHECK: LDS_UBYTE_READ_RET -; R600-CHECK: LDS_UBYTE_READ_RET -; R600-CHECK: LDS_UBYTE_READ_RET -; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u8 -; SI-CHECK: ds_read_u8 -; SI-CHECK: ds_read_u8 -; SI-CHECK: ds_read_u8 +; R600: LDS_UBYTE_READ_RET +; R600: LDS_UBYTE_READ_RET +; R600: LDS_UBYTE_READ_RET +; R600: LDS_UBYTE_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { entry: %0 = load <4 x i8> addrspace(3)* %in @@ -541,20 +541,20 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i8_sext_local: -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: LDS_UBYTE_READ_RET -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i8 -; SI-CHECK: ds_read_i8 -; SI-CHECK: ds_read_i8 -; SI-CHECK: ds_read_i8 +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: LDS_UBYTE_READ_RET +; R600-DAG: ASHR +; R600-DAG: ASHR +; R600-DAG: ASHR +; R600-DAG: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i8 +; SI: ds_read_i8 +; SI: ds_read_i8 +; SI: ds_read_i8 define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { entry: %0 = load <4 x i8> addrspace(3)* %in @@ -565,10 +565,10 @@ entry: ; Load an i16 value from the local address space. ; FUNC-LABEL: {{^}}load_i16_local: -; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u16 +; R600: LDS_USHORT_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u16 define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { entry: %0 = load i16 addrspace(3)* %in @@ -578,11 +578,11 @@ entry: } ; FUNC-LABEL: {{^}}load_i16_sext_local: -; R600-CHECK: LDS_USHORT_READ_RET -; R600-CHECK: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i16 +; R600: LDS_USHORT_READ_RET +; R600: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i16 define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { entry: %0 = load i16 addrspace(3)* %in @@ -592,12 +592,12 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i16_local: -; R600-CHECK: LDS_USHORT_READ_RET -; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u16 -; SI-CHECK: ds_read_u16 +; R600: LDS_USHORT_READ_RET +; R600: LDS_USHORT_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u16 +; SI: ds_read_u16 define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { entry: %0 = load <2 x i16> addrspace(3)* %in @@ -607,14 +607,14 @@ entry: } ; FUNC-LABEL: {{^}}load_v2i16_sext_local: -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i16 -; SI-CHECK: ds_read_i16 +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: ASHR +; R600-DAG: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i16 +; SI: ds_read_i16 define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { entry: %0 = load <2 x i16> addrspace(3)* %in @@ -624,16 +624,16 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i16_local: -; R600-CHECK: LDS_USHORT_READ_RET -; R600-CHECK: LDS_USHORT_READ_RET -; R600-CHECK: LDS_USHORT_READ_RET -; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_u16 -; SI-CHECK: ds_read_u16 -; SI-CHECK: ds_read_u16 -; SI-CHECK: ds_read_u16 +; R600: LDS_USHORT_READ_RET +; R600: LDS_USHORT_READ_RET +; R600: LDS_USHORT_READ_RET +; R600: LDS_USHORT_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { entry: %0 = load <4 x i16> addrspace(3)* %in @@ -643,20 +643,20 @@ entry: } ; FUNC-LABEL: {{^}}load_v4i16_sext_local: -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: LDS_USHORT_READ_RET -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_i16 -; SI-CHECK: ds_read_i16 -; SI-CHECK: ds_read_i16 -; SI-CHECK: ds_read_i16 +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: LDS_USHORT_READ_RET +; R600-DAG: ASHR +; R600-DAG: ASHR +; R600-DAG: ASHR +; R600-DAG: ASHR +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_i16 +; SI: ds_read_i16 +; SI: ds_read_i16 +; SI: ds_read_i16 define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { entry: %0 = load <4 x i16> addrspace(3)* %in @@ -667,10 +667,10 @@ entry: ; load an i32 value from the local address space. ; FUNC-LABEL: {{^}}load_i32_local: -; R600-CHECK: LDS_READ_RET -; SI-CHECK-NOT: s_wqm_b64 -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_b32 +; R600: LDS_READ_RET +; SI-NOT: s_wqm_b64 +; SI: s_mov_b32 m0 +; SI: ds_read_b32 define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = load i32 addrspace(3)* %in @@ -680,9 +680,9 @@ entry: ; load a f32 value from the local address space. ; FUNC-LABEL: {{^}}load_f32_local: -; R600-CHECK: LDS_READ_RET -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_b32 +; R600: LDS_READ_RET +; SI: s_mov_b32 m0 +; SI: ds_read_b32 define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) { entry: %0 = load float addrspace(3)* %in @@ -692,10 +692,10 @@ entry: ; load a v2f32 value from the local address space ; FUNC-LABEL: {{^}}load_v2f32_local: -; R600-CHECK: LDS_READ_RET -; R600-CHECK: LDS_READ_RET -; SI-CHECK: s_mov_b32 m0 -; SI-CHECK: ds_read_b64 +; R600: LDS_READ_RET +; R600: LDS_READ_RET +; SI: s_mov_b32 m0 +; SI: ds_read_b64 define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) { entry: %0 = load <2 x float> addrspace(3)* %in @@ -705,11 +705,11 @@ entry: ; Test loading a i32 and v2i32 value from the same base pointer. ; FUNC-LABEL: {{^}}load_i32_v2i32_local: -; R600-CHECK: LDS_READ_RET -; R600-CHECK: LDS_READ_RET -; R600-CHECK: LDS_READ_RET -; SI-CHECK-DAG: ds_read_b32 -; SI-CHECK-DAG: ds_read2_b32 +; R600: LDS_READ_RET +; R600: LDS_READ_RET +; R600: LDS_READ_RET +; SI-DAG: ds_read_b32 +; SI-DAG: ds_read2_b32 define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) { %scalar = load i32 addrspace(3)* %in %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)* @@ -727,9 +727,9 @@ define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3) ; On SI we need to make sure that the base offset is a register and not ; an immediate. ; FUNC-LABEL: {{^}}load_i32_local_const_ptr: -; SI-CHECK: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 -; SI-CHECK: ds_read_b32 v0, v[[ZERO]] offset:4 -; R600-CHECK: LDS_READ_RET +; SI: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 +; SI: ds_read_b32 v0, v[[ZERO]] offset:4 +; R600: LDS_READ_RET define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %tmp0 = getelementptr [512 x i32] addrspace(3)* @lds, i32 0, i32 1 diff --git a/llvm/test/CodeGen/R600/load.vec.ll b/llvm/test/CodeGen/R600/load.vec.ll index 224e043..346d8dc 100644 --- a/llvm/test/CodeGen/R600/load.vec.ll +++ b/llvm/test/CodeGen/R600/load.vec.ll @@ -1,12 +1,12 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s ; load a v2i32 value from the global address space. -; EG-CHECK: {{^}}load_v2i32: -; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 -; SI-CHECK: {{^}}load_v2i32: -; SI-CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] +; EG: {{^}}load_v2i32: +; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 +; SI: {{^}}load_v2i32: +; SI: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %a = load <2 x i32> addrspace(1) * %in store <2 x i32> %a, <2 x i32> addrspace(1)* %out @@ -14,10 +14,10 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i } ; load a v4i32 value from the global address space. -; EG-CHECK: {{^}}load_v4i32: -; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0 -; SI-CHECK: {{^}}load_v4i32: -; SI-CHECK: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}] +; EG: {{^}}load_v4i32: +; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0 +; SI: {{^}}load_v4i32: +; SI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}] define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %a = load <4 x i32> addrspace(1) * %in store <4 x i32> %a, <4 x i32> addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/local-memory-two-objects.ll b/llvm/test/CodeGen/R600/local-memory-two-objects.ll index 86edfde..cd52a9e 100644 --- a/llvm/test/CodeGen/R600/local-memory-two-objects.ll +++ b/llvm/test/CodeGen/R600/local-memory-two-objects.ll @@ -1,34 +1,34 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=CI %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI %s +; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=CI %s @local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 @local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 -; EG-CHECK: {{^}}local_memory_two_objects: +; EG: {{^}}local_memory_two_objects: ; Check that the LDS size emitted correctly -; EG-CHECK: .long 166120 -; EG-CHECK-NEXT: .long 8 -; SI-CHECK: .long 47180 -; SI-CHECK-NEXT: .long 38792 +; EG: .long 166120 +; EG-NEXT: .long 8 +; GCN: .long 47180 +; GCN-NEXT: .long 38792 ; We would like to check the the lds writes are using different ; addresses, but due to variations in the scheduler, we can't do ; this consistently on evergreen GPUs. -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; SI-CHECK: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] -; SI-CHECK-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]] +; EG: LDS_WRITE +; EG: LDS_WRITE +; GCN: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] +; GCN-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]] ; GROUP_BARRIER must be the last instruction in a clause -; EG-CHECK: GROUP_BARRIER -; EG-CHECK-NEXT: ALU clause +; EG: GROUP_BARRIER +; EG-NEXT: ALU clause ; Make sure the lds reads are using different addresses, at different ; constant offsets. -; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] -; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] +; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] +; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] ; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}} ; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0] ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] [M0] diff --git a/llvm/test/CodeGen/R600/r600-encoding.ll b/llvm/test/CodeGen/R600/r600-encoding.ll index 112cdac..3a82ee3 100644 --- a/llvm/test/CodeGen/R600/r600-encoding.ll +++ b/llvm/test/CodeGen/R600/r600-encoding.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s ; The earliest R600 GPUs have a slightly different encoding than the rest of ; the VLIW4/5 GPUs. -; EG-CHECK: {{^}}test: -; EG-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] +; EG: {{^}}test: +; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] -; R600-CHECK: {{^}}test: -; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] +; R600: {{^}}test: +; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] define void @test(<4 x float> inreg %reg0) #0 { entry: diff --git a/llvm/test/CodeGen/R600/shl.ll b/llvm/test/CodeGen/R600/shl.ll index c6a18bf..f89353b 100644 --- a/llvm/test/CodeGen/R600/shl.ll +++ b/llvm/test/CodeGen/R600/shl.ll @@ -1,18 +1,18 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s -;EG-CHECK: {{^}}shl_v2i32: -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}shl_v2i32: +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: {{^}}shl_v2i32: -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: {{^}}shl_v2i32: +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: {{^}}shl_v2i32: -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: {{^}}shl_v2i32: +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -23,23 +23,23 @@ define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in ret void } -;EG-CHECK: {{^}}shl_v4i32: -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}shl_v4i32: +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: {{^}}shl_v4i32: -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: {{^}}shl_v4i32: +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: {{^}}shl_v4i32: -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: {{^}}shl_v4i32: +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -50,23 +50,23 @@ define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in ret void } -;EG-CHECK: {{^}}shl_i64: -;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] -;EG-CHECK: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} -;EG-CHECK: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 +;EG: {{^}}shl_i64: +;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] +;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} +;EG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-CHECK-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] -;EG-CHECK-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} -;EG-CHECK-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}} -;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} -;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 +;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] +;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} +;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}} +;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal +;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} +;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 -;SI-CHECK: {{^}}shl_i64: -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: {{^}}shl_i64: +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;VI-CHECK: {{^}}shl_i64: -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: {{^}}shl_i64: +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 @@ -77,35 +77,35 @@ define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ret void } -;EG-CHECK: {{^}}shl_v2i64: -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHA]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHB]] -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT - -;SI-CHECK: {{^}}shl_v2i64: -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-CHECK: {{^}}shl_v2i64: -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;EG: {{^}}shl_v2i64: +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: LSHL {{.*}}, [[SHA]] +;EG-DAG: LSHL {{.*}}, [[SHB]] +;EG-DAG: LSHL {{.*}}, [[SHA]] +;EG-DAG: LSHL {{.*}}, [[SHB]] +;EG-DAG: LSHL +;EG-DAG: LSHL +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT + +;SI: {{^}}shl_v2i64: +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} + +;VI: {{^}}shl_v2i64: +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 @@ -116,59 +116,59 @@ define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in ret void } -;EG-CHECK: {{^}}shl_v4i64: -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHA]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHB]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHC]] -;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHD]] -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: LSHR {{.*}}, 1 -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHC]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHD]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHC]] -;EG-CHECK-DAG: LSHL {{.*}}, [[SHD]] -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: LSHL -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT - -;SI-CHECK: {{^}}shl_v4i64: -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-CHECK: {{^}}shl_v4i64: -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;EG: {{^}}shl_v4i64: +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHC]] +;EG-DAG: LSHR {{\*? *}}[[COMPSHD]] +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: LSHR {{.*}}, 1 +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: LSHL {{.*}}, [[SHA]] +;EG-DAG: LSHL {{.*}}, [[SHB]] +;EG-DAG: LSHL {{.*}}, [[SHC]] +;EG-DAG: LSHL {{.*}}, [[SHD]] +;EG-DAG: LSHL {{.*}}, [[SHA]] +;EG-DAG: LSHL {{.*}}, [[SHB]] +;EG-DAG: LSHL {{.*}}, [[SHC]] +;EG-DAG: LSHL {{.*}}, [[SHD]] +;EG-DAG: LSHL +;EG-DAG: LSHL +;EG-DAG: LSHL +;EG-DAG: LSHL +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT {{.*}}, 0.0 +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT + +;SI: {{^}}shl_v4i64: +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} + +;VI: {{^}}shl_v4i64: +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 diff --git a/llvm/test/CodeGen/R600/sra.ll b/llvm/test/CodeGen/R600/sra.ll index 7b461ca..d6c6ccd 100644 --- a/llvm/test/CodeGen/R600/sra.ll +++ b/llvm/test/CodeGen/R600/sra.ll @@ -1,18 +1,18 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s -;EG-CHECK-LABEL: {{^}}ashr_v2i32: -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-LABEL: {{^}}ashr_v2i32: +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK-LABEL: {{^}}ashr_v2i32: -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-LABEL: {{^}}ashr_v2i32: +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK-LABEL: {{^}}ashr_v2i32: -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI-LABEL: {{^}}ashr_v2i32: +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -23,23 +23,23 @@ define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i ret void } -;EG-CHECK-LABEL: {{^}}ashr_v4i32: -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-LABEL: {{^}}ashr_v4i32: +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK-LABEL: {{^}}ashr_v4i32: -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-LABEL: {{^}}ashr_v4i32: +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK-LABEL: {{^}}ashr_v4i32: -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-CHECK: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI-LABEL: {{^}}ashr_v4i32: +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -50,14 +50,14 @@ define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i ret void } -;EG-CHECK-LABEL: {{^}}ashr_i64: -;EG-CHECK: ASHR +;EG-LABEL: {{^}}ashr_i64: +;EG: ASHR -;SI-CHECK-LABEL: {{^}}ashr_i64: -;SI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 +;SI-LABEL: {{^}}ashr_i64: +;SI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 -;VI-CHECK-LABEL: {{^}}ashr_i64: -;VI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 +;VI-LABEL: {{^}}ashr_i64: +;VI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { entry: @@ -67,25 +67,25 @@ entry: ret void } -;EG-CHECK-LABEL: {{^}}ashr_i64_2: -;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] -;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} -;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 +;EG-LABEL: {{^}}ashr_i64_2: +;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] +;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} +;EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] -;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} -;EG-CHECK-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} -;EG-CHECK-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal -;EG-CHECK-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} -;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} +;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] +;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} +;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} +;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal +;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal +;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal +;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} +;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} -;SI-CHECK-LABEL: {{^}}ashr_i64_2: -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-LABEL: {{^}}ashr_i64_2: +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;VI-CHECK-LABEL: {{^}}ashr_i64_2: -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI-LABEL: {{^}}ashr_i64_2: +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { entry: @@ -97,39 +97,39 @@ entry: ret void } -;EG-CHECK-LABEL: {{^}}ashr_v2i64: -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]] -;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT - -;SI-CHECK-LABEL: {{^}}ashr_v2i64: -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-CHECK-LABEL: {{^}}ashr_v2i64: -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;EG-LABEL: {{^}}ashr_v2i64: +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHA]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHB]] +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: ASHR {{.*}}, [[SHA]] +;EG-DAG: ASHR {{.*}}, [[SHB]] +;EG-DAG: LSHR {{.*}}, [[SHA]] +;EG-DAG: LSHR {{.*}}, [[SHB]] +;EG-DAG: OR_INT +;EG-DAG: OR_INT +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ASHR +;EG-DAG: ASHR +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT + +;SI-LABEL: {{^}}ashr_v2i64: +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} + +;VI-LABEL: {{^}}ashr_v2i64: +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 @@ -140,67 +140,67 @@ define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i ret void } -;EG-CHECK-LABEL: {{^}}ashr_v4i64: -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]] -;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]] -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: LSHL {{.*}}, 1 -;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]] -;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]] -;EG-CHECK-DAG: ASHR {{.*}}, [[SHC]] -;EG-CHECK-DAG: ASHR {{.*}}, [[SHD]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] -;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: OR_INT -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: ASHR {{.*}}, literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal -;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT -;EG-CHECK-DAG: CNDE_INT - -;SI-CHECK-LABEL: {{^}}ashr_v4i64: -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-CHECK-LABEL: {{^}}ashr_v4i64: -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI-CHECK: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;EG-LABEL: {{^}}ashr_v4i64: +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] +;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHA]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHB]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHC]] +;EG-DAG: LSHL {{\*? *}}[[COMPSHD]] +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: LSHL {{.*}}, 1 +;EG-DAG: ASHR {{.*}}, [[SHA]] +;EG-DAG: ASHR {{.*}}, [[SHB]] +;EG-DAG: ASHR {{.*}}, [[SHC]] +;EG-DAG: ASHR {{.*}}, [[SHD]] +;EG-DAG: LSHR {{.*}}, [[SHA]] +;EG-DAG: LSHR {{.*}}, [[SHB]] +;EG-DAG: LSHR {{.*}}, [[SHA]] +;EG-DAG: LSHR {{.*}}, [[SHB]] +;EG-DAG: OR_INT +;EG-DAG: OR_INT +;EG-DAG: OR_INT +;EG-DAG: OR_INT +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal +;EG-DAG: ASHR +;EG-DAG: ASHR +;EG-DAG: ASHR +;EG-DAG: ASHR +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: ASHR {{.*}}, literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal +;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT +;EG-DAG: CNDE_INT + +;SI-LABEL: {{^}}ashr_v4i64: +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} + +;VI-LABEL: {{^}}ashr_v4i64: +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 diff --git a/llvm/test/CodeGen/R600/store.ll b/llvm/test/CodeGen/R600/store.ll index 49227e9a..e4cb313 100644 --- a/llvm/test/CodeGen/R600/store.ll +++ b/llvm/test/CodeGen/R600/store.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-CHECK -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI-CHECK -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG-CHECK -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM-CHECK -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ;===------------------------------------------------------------------------===; ; Global Address Space ;===------------------------------------------------------------------------===; ; FUNC-LABEL: {{^}}store_i1: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_byte +; EG: MEM_RAT MSKOR +; SI: buffer_store_byte define void @store_i1(i1 addrspace(1)* %out) { entry: store i1 true, i1 addrspace(1)* %out @@ -16,29 +16,29 @@ entry: } ; i8 store -; EG-CHECK-LABEL: {{^}}store_i8: -; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-LABEL: {{^}}store_i8: +; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; IG 0: Get the byte index and truncate the value -; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y -; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43) +; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y +; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43) ; IG 1: Truncate the calculated the shift amount for the mask ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-CHECK-NEXT: 255 +; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] +; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-NEXT: 255 ; IG 3: Initialize the Y and Z channels to zero ; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 -; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 +; EG: MOV T[[RW_GPR]].Y, 0.0 +; EG: MOV * T[[RW_GPR]].Z, 0.0 -; SI-CHECK-LABEL: {{^}}store_i8: -; SI-CHECK: buffer_store_byte +; SI-LABEL: {{^}}store_i8: +; SI: buffer_store_byte define void @store_i8(i8 addrspace(1)* %out, i8 %in) { entry: @@ -47,44 +47,44 @@ entry: } ; i16 store -; EG-CHECK-LABEL: {{^}}store_i16: -; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-LABEL: {{^}}store_i16: +; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; IG 0: Get the byte index and truncate the value -; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-CHECK-NEXT: 3(4.203895e-45), +; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-NEXT: 3(4.203895e-45), -; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y +; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y -; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41) +; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) ; IG 1: Truncate the calculated the shift amount for the mask ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-CHECK-NEXT: 65535 +; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] +; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-NEXT: 65535 ; IG 3: Initialize the Y and Z channels to zero ; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 -; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 +; EG: MOV T[[RW_GPR]].Y, 0.0 +; EG: MOV * T[[RW_GPR]].Z, 0.0 -; SI-CHECK-LABEL: {{^}}store_i16: -; SI-CHECK: buffer_store_short +; SI-LABEL: {{^}}store_i16: +; SI: buffer_store_short define void @store_i16(i16 addrspace(1)* %out, i16 %in) { entry: store i16 %in, i16 addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_v2i8: -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK-NOT: MEM_RAT MSKOR -; SI-CHECK-LABEL: {{^}}store_v2i8: -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte +; EG-LABEL: {{^}}store_v2i8: +; EG: MEM_RAT MSKOR +; EG-NOT: MEM_RAT MSKOR +; SI-LABEL: {{^}}store_v2i8: +; SI: buffer_store_byte +; SI: buffer_store_byte define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i8> @@ -93,13 +93,13 @@ entry: } -; EG-CHECK-LABEL: {{^}}store_v2i16: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v2i16: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v2i16: -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short +; EG-LABEL: {{^}}store_v2i16: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v2i16: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v2i16: +; SI: buffer_store_short +; SI: buffer_store_short define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -107,15 +107,15 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}store_v4i8: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v4i8: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v4i8: -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte +; EG-LABEL: {{^}}store_v4i8: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v4i8: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v4i8: +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i8> @@ -124,30 +124,30 @@ entry: } ; floating-point store -; EG-CHECK-LABEL: {{^}}store_f32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 -; CM-CHECK-LABEL: {{^}}store_f32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK-LABEL: {{^}}store_f32: -; SI-CHECK: buffer_store_dword +; EG-LABEL: {{^}}store_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; CM-LABEL: {{^}}store_f32: +; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-LABEL: {{^}}store_f32: +; SI: buffer_store_dword define void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_v4i16: -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK-NOT: MEM_RAT MSKOR -; SI-CHECK-LABEL: {{^}}store_v4i16: -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK-NOT: buffer_store_byte +; EG-LABEL: {{^}}store_v4i16: +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG-NOT: MEM_RAT MSKOR +; SI-LABEL: {{^}}store_v4i16: +; SI: buffer_store_short +; SI: buffer_store_short +; SI: buffer_store_short +; SI: buffer_store_short +; SI-NOT: buffer_store_byte define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i16> @@ -156,12 +156,12 @@ entry: } ; vec2 floating-point stores -; EG-CHECK-LABEL: {{^}}store_v2f32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v2f32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v2f32: -; SI-CHECK: buffer_store_dwordx2 +; EG-LABEL: {{^}}store_v2f32: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v2f32: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v2f32: +; SI: buffer_store_dwordx2 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { entry: @@ -171,14 +171,14 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}store_v4i32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v4i32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v4i32: -; SI-CHECK: buffer_store_dwordx4 +; EG-LABEL: {{^}}store_v4i32: +; EG: MEM_RAT_CACHELESS STORE_RAW +; EG-NOT: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v4i32: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v4i32: +; SI: buffer_store_dwordx4 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out @@ -186,8 +186,8 @@ entry: } ; FUNC-LABEL: {{^}}store_i64_i8: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_byte +; EG: MEM_RAT MSKOR +; SI: buffer_store_byte define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -196,8 +196,8 @@ entry: } ; FUNC-LABEL: {{^}}store_i64_i16: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_short +; EG: MEM_RAT MSKOR +; SI: buffer_store_short define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -210,89 +210,89 @@ entry: ;===------------------------------------------------------------------------===; ; FUNC-LABEL: {{^}}store_local_i1: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: ds_write_b8 +; EG: LDS_BYTE_WRITE +; SI: ds_write_b8 define void @store_local_i1(i1 addrspace(3)* %out) { entry: store i1 true, i1 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_i8: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK-LABEL: {{^}}store_local_i8: -; SI-CHECK: ds_write_b8 +; EG-LABEL: {{^}}store_local_i8: +; EG: LDS_BYTE_WRITE +; SI-LABEL: {{^}}store_local_i8: +; SI: ds_write_b8 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) { store i8 %in, i8 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_i16: -; EG-CHECK: LDS_SHORT_WRITE -; SI-CHECK-LABEL: {{^}}store_local_i16: -; SI-CHECK: ds_write_b16 +; EG-LABEL: {{^}}store_local_i16: +; EG: LDS_SHORT_WRITE +; SI-LABEL: {{^}}store_local_i16: +; SI: ds_write_b16 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { store i16 %in, i16 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v2i16: -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v2i16: -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v2i16: -; SI-CHECK: ds_write_b16 -; SI-CHECK: ds_write_b16 +; EG-LABEL: {{^}}store_local_v2i16: +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v2i16: +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v2i16: +; SI: ds_write_b16 +; SI: ds_write_b16 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v4i8: -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v4i8: -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v4i8: -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 +; EG-LABEL: {{^}}store_local_v4i8: +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v4i8: +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v4i8: +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v2i32: -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v2i32: -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v2i32: -; SI-CHECK: ds_write_b64 +; EG-LABEL: {{^}}store_local_v2i32: +; EG: LDS_WRITE +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v2i32: +; CM: LDS_WRITE +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v2i32: +; SI: ds_write_b64 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) { entry: store <2 x i32> %in, <2 x i32> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v4i32: -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v4i32: -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v4i32: -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 +; EG-LABEL: {{^}}store_local_v4i32: +; EG: LDS_WRITE +; EG: LDS_WRITE +; EG: LDS_WRITE +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v4i32: +; CM: LDS_WRITE +; CM: LDS_WRITE +; CM: LDS_WRITE +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v4i32: +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(3)* %out @@ -300,8 +300,8 @@ entry: } ; FUNC-LABEL: {{^}}store_local_i64_i8: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: ds_write_b8 +; EG: LDS_BYTE_WRITE +; SI: ds_write_b8 define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -310,8 +310,8 @@ entry: } ; FUNC-LABEL: {{^}}store_local_i64_i16: -; EG-CHECK: LDS_SHORT_WRITE -; SI-CHECK: ds_write_b16 +; EG: LDS_SHORT_WRITE +; SI: ds_write_b16 define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -326,12 +326,12 @@ entry: ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should ; be two 32-bit stores. -; EG-CHECK-LABEL: {{^}}vecload2: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}vecload2: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}vecload2: -; SI-CHECK: buffer_store_dwordx2 +; EG-LABEL: {{^}}vecload2: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}vecload2: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}vecload2: +; SI: buffer_store_dwordx2 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { entry: %0 = load i32 addrspace(2)* %mem, align 4 @@ -349,14 +349,14 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= ; FUNC-LABEL: {{^}}"i128-const-store": ; FIXME: We should be able to to this with one store instruction -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD +; EG: STORE_RAW +; EG: STORE_RAW +; EG: STORE_RAW +; EG: STORE_RAW +; CM: STORE_DWORD +; CM: STORE_DWORD +; CM: STORE_DWORD +; CM: STORE_DWORD ; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2 define void @i128-const-store(i32 addrspace(1)* %out) { diff --git a/llvm/test/CodeGen/R600/store.r600.ll b/llvm/test/CodeGen/R600/store.r600.ll index 3df30d4..2197260 100644 --- a/llvm/test/CodeGen/R600/store.r600.ll +++ b/llvm/test/CodeGen/R600/store.r600.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; XXX: Merge this test into store.ll once it is supported on SI ; v4i32 store -; EG-CHECK: {{^}}store_v4i32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG: {{^}}store_v4i32: +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %1 = load <4 x i32> addrspace(1) * %in @@ -13,8 +13,8 @@ define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % } ; v4f32 store -; EG-CHECK: {{^}}store_v4f32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG: {{^}}store_v4f32: +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %1 = load <4 x float> addrspace(1) * %in store <4 x float> %1, <4 x float> addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/swizzle-export.ll b/llvm/test/CodeGen/R600/swizzle-export.ll index 3e6f7a7..5eaca76 100644 --- a/llvm/test/CodeGen/R600/swizzle-export.ll +++ b/llvm/test/CodeGen/R600/swizzle-export.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s -;EG-CHECK: {{^}}main: -;EG-CHECK: EXPORT T{{[0-9]+}}.XYXX -;EG-CHECK: EXPORT T{{[0-9]+}}.ZXXX -;EG-CHECK: EXPORT T{{[0-9]+}}.XXWX -;EG-CHECK: EXPORT T{{[0-9]+}}.XXXW +;EG: {{^}}main: +;EG: EXPORT T{{[0-9]+}}.XYXX +;EG: EXPORT T{{[0-9]+}}.ZXXX +;EG: EXPORT T{{[0-9]+}}.XXWX +;EG: EXPORT T{{[0-9]+}}.XXXW define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { main_body: @@ -92,9 +92,9 @@ main_body: ret void } -; EG-CHECK: {{^}}main2: -; EG-CHECK: T{{[0-9]+}}.XY__ -; EG-CHECK: T{{[0-9]+}}.ZXY0 +; EG: {{^}}main2: +; EG: T{{[0-9]+}}.XY__ +; EG: T{{[0-9]+}}.ZXY0 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { main_body: diff --git a/llvm/test/CodeGen/R600/udiv.ll b/llvm/test/CodeGen/R600/udiv.ll index a6ce5e9..0c2c65b 100644 --- a/llvm/test/CodeGen/R600/udiv.ll +++ b/llvm/test/CodeGen/R600/udiv.ll @@ -1,10 +1,10 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s -;EG-CHECK-LABEL: {{^}}test: -;EG-CHECK-NOT: SETGE_INT -;EG-CHECK: CF_END +;EG-LABEL: {{^}}test: +;EG-NOT: SETGE_INT +;EG: CF_END define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 @@ -19,10 +19,10 @@ define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ;The goal of this test is to make sure the ISel doesn't fail when it gets ;a v4i32 udiv -;EG-CHECK-LABEL: {{^}}test2: -;EG-CHECK: CF_END -;SI-CHECK-LABEL: {{^}}test2: -;SI-CHECK: s_endpgm +;EG-LABEL: {{^}}test2: +;EG: CF_END +;SI-LABEL: {{^}}test2: +;SI: s_endpgm define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -33,10 +33,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ret void } -;EG-CHECK-LABEL: {{^}}test4: -;EG-CHECK: CF_END -;SI-CHECK-LABEL: {{^}}test4: -;SI-CHECK: s_endpgm +;EG-LABEL: {{^}}test4: +;EG: CF_END +;SI-LABEL: {{^}}test4: +;SI: s_endpgm define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/llvm/test/CodeGen/R600/vertex-fetch-encoding.ll b/llvm/test/CodeGen/R600/vertex-fetch-encoding.ll index e24744e..e4d117f 100644 --- a/llvm/test/CodeGen/R600/vertex-fetch-encoding.ll +++ b/llvm/test/CodeGen/R600/vertex-fetch-encoding.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s -; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM %s -; NI-CHECK: {{^}}vtx_fetch32: -; NI-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 -; CM-CHECK: {{^}}vtx_fetch32: -; CM-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 +; NI: {{^}}vtx_fetch32: +; NI: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 +; CM: {{^}}vtx_fetch32: +; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 define void @vtx_fetch32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: @@ -13,8 +13,8 @@ entry: ret void } -; NI-CHECK: {{^}}vtx_fetch128: -; NI-CHECK: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00 +; NI: {{^}}vtx_fetch128: +; NI: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00 ; XXX: Add a case for Cayman when v4i32 stores are supported. define void @vtx_fetch128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { diff --git a/llvm/test/CodeGen/R600/vselect.ll b/llvm/test/CodeGen/R600/vselect.ll index 809ccf8..a6152f7 100644 --- a/llvm/test/CodeGen/R600/vselect.ll +++ b/llvm/test/CodeGen/R600/vselect.ll @@ -1,14 +1,14 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s +;RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s -;EG-CHECK: {{^}}test_select_v2i32: -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}test_select_v2i32: +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: {{^}}test_select_v2i32: -;SI-CHECK: v_cndmask_b32_e64 -;SI-CHECK: v_cndmask_b32_e64 +;SI: {{^}}test_select_v2i32: +;SI: v_cndmask_b32_e64 +;SI: v_cndmask_b32_e64 define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { entry: @@ -20,13 +20,13 @@ entry: ret void } -;EG-CHECK: {{^}}test_select_v2f32: -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}test_select_v2f32: +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: {{^}}test_select_v2f32: -;SI-CHECK: v_cndmask_b32_e64 -;SI-CHECK: v_cndmask_b32_e64 +;SI: {{^}}test_select_v2f32: +;SI: v_cndmask_b32_e64 +;SI: v_cndmask_b32_e64 define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { entry: @@ -38,17 +38,17 @@ entry: ret void } -;EG-CHECK: {{^}}test_select_v4i32: -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}test_select_v4i32: +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: {{^}}test_select_v4i32: -;SI-CHECK: v_cndmask_b32_e64 -;SI-CHECK: v_cndmask_b32_e64 -;SI-CHECK: v_cndmask_b32_e64 -;SI-CHECK: v_cndmask_b32_e64 +;SI: {{^}}test_select_v4i32: +;SI: v_cndmask_b32_e64 +;SI: v_cndmask_b32_e64 +;SI: v_cndmask_b32_e64 +;SI: v_cndmask_b32_e64 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { entry: @@ -60,11 +60,11 @@ entry: ret void } -;EG-CHECK: {{^}}test_select_v4f32: -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: {{^}}test_select_v4f32: +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { entry: diff --git a/llvm/test/CodeGen/R600/zero_extend.ll b/llvm/test/CodeGen/R600/zero_extend.ll index 1f4dd43..033055d 100644 --- a/llvm/test/CodeGen/R600/zero_extend.ll +++ b/llvm/test/CodeGen/R600/zero_extend.ll @@ -1,15 +1,15 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI -; R600-CHECK: {{^}}test: -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW +; R600: {{^}}test: +; R600: MEM_RAT_CACHELESS STORE_RAW +; R600: MEM_RAT_CACHELESS STORE_RAW -; SI-CHECK: {{^}}test: -; SI-CHECK: s_mov_b32 [[ZERO:s[0-9]]], 0{{$}} -; SI-CHECK: v_mov_b32_e32 v[[V_ZERO:[0-9]]], [[ZERO]] -; SI-CHECK: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}} +; SI: {{^}}test: +; SI: s_mov_b32 [[ZERO:s[0-9]]], 0{{$}} +; SI: v_mov_b32_e32 v[[V_ZERO:[0-9]]], [[ZERO]] +; SI: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}} define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { entry: %0 = mul i32 %a, %b @@ -19,8 +19,8 @@ entry: ret void } -; SI-CHECK-LABEL: {{^}}testi1toi32: -; SI-CHECK: v_cndmask_b32 +; SI-LABEL: {{^}}testi1toi32: +; SI: v_cndmask_b32 define void @testi1toi32(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp eq i32 %a, %b @@ -29,10 +29,10 @@ entry: ret void } -; SI-CHECK-LABEL: {{^}}zext_i1_to_i64: -; SI-CHECK: s_mov_b32 s{{[0-9]+}}, 0 -; SI-CHECK: v_cmp_eq_i32 -; SI-CHECK: v_cndmask_b32 +; SI-LABEL: {{^}}zext_i1_to_i64: +; SI: s_mov_b32 s{{[0-9]+}}, 0 +; SI: v_cmp_eq_i32 +; SI: v_cndmask_b32 define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %ext = zext i1 %cmp to i64 -- 2.7.4