From 37ac4f865fba451d969bd9b4b1e28ce296e093da Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 6 Jan 2021 12:55:52 +0000 Subject: [PATCH] [Hexagon] Regenerate zext-v4i1.ll tests This will be improved by part of the work for D86578 --- llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll | 34 ++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll index e5394d9..5f9a152 100644 --- a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll @@ -1,12 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s ; Check that this compiles successfully. -; CHECK: vcmph.eq target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" define i32 @fred(<8 x i16>* %a0) #0 { +; CHECK-LABEL: fred: +; CHECK: // %bb.0: // %b0 +; CHECK-NEXT: { +; CHECK-NEXT: if (p0) jump:nt .LBB0_2 +; CHECK-NEXT: } +; CHECK-NEXT: // %bb.1: // %b2 +; CHECK-NEXT: { +; CHECK-NEXT: r3:2 = combine(#0,#0) +; CHECK-NEXT: r1:0 = memd(r0+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: p0 = vcmph.eq(r1:0,r3:2) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r1:0 = mask(p0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = and(r0,#1) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: p0 = cmp.eq(r0,#11) +; CHECK-NEXT: r0 = #1 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if (p0) r0 = #0 +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } +; CHECK-NEXT: .LBB0_2: // %b14 +; CHECK-NEXT: { +; CHECK-NEXT: r0 = #0 +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } b0: switch i32 undef, label %b14 [ i32 5, label %b2 -- 2.7.4