From 376233113e254e47ea9624c770150c1e90bbce80 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Nov 2021 15:05:27 -0800 Subject: [PATCH] [RISCV] Use TargetConstant for CSR number for READ_CSR/WRITE_CSR. This is consistent with what we do for other operands that are required to be constants. I don't think this results in any real changes. The pattern match code for isel treats ConstantSDNode and TargetConstantSDNode the same. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9d8d11e..9f5f3d2 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5362,7 +5362,7 @@ SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op, const MVT XLenVT = Subtarget.getXLenVT(); SDLoc DL(Op); SDValue Chain = Op->getOperand(0); - SDValue SysRegNo = DAG.getConstant( + SDValue SysRegNo = DAG.getTargetConstant( RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other); SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo); @@ -5394,7 +5394,7 @@ SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op, SDLoc DL(Op); SDValue Chain = Op->getOperand(0); SDValue RMValue = Op->getOperand(1); - SDValue SysRegNo = DAG.getConstant( + SDValue SysRegNo = DAG.getTargetConstant( RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); // Encoding used for rounding mode in RISCV differs from that used in -- 2.7.4