From 374097963cec9c1142faf10b819aa28d1fb6f641 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Sun, 24 Apr 2005 12:53:36 +0000 Subject: [PATCH] rs6000.c (rs6000_override_options): Use gcc_assert and gcc_unreachable as appropriate. * config/rs6000/rs6000.c (rs6000_override_options): Use gcc_assert and gcc_unreachable as appropriate. (num_insns_constant, output_vec_const_move, build_mask64_2_operands, rs6000_output_dwarf_dtprel, rs6000_emit_set_const, rs6000_emit_move, spe_build_register_parallel, function_arg, rs6000_move_block_from_reg, altivec_expand_predicate_builtin, spe_expand_predicate_builtin, spe_expand_evsel_builtin, rs6000_expand_builtin, spe_init_builtins, altivec_init_builtins, rs6000_common_init_builtins, expand_block_clear, expand_block_move, validate_condition_mode, ccr_bit, extract_MB, extract_ME, rs6000_get_some_local_dynamic_name, rs6000_output_function_entry, print_operand, print_operand_address, rs6000_generate_compare, rs6000_emit_sCOND, output_cbranch, output_e500_flip_gt_bit, rs6000_emit_vector_compare, rs6000_emit_vector_compare, rs6000_emit_cmove, rs6000_emit_minmax, rs6000_split_multireg_move, compute_save_world_info, rs6000_stack_info, rs6000_emit_load_toc_table, rs6000_frame_related, spe_synthesize_frame_save, rs6000_emit_epilogue, rs6000_output_function_epilogue, rs6000_hash_constant, output_toc, output_function_profiler, rs6000_trampoline_size, rs6000_initialize_trampoline, find_addr_reg, rs6000_machopic_legitimize_pic_address, rs6000_initial_elimination_offset, rs6000_dbx_register_number): Likewise. * config/rs6000/rs6000.md (*fix_truncdfsi2_internal, *movdf_hardfloat32, *movdf_softfloat32, *fix_trunctfsi2_internal, *movti_power, *movti_string, call, call_value, sibcall, sibcall_value): Likewise. * config/rs6000/spe.md (*movdf_e500_double, *movv2si_internal): Likewise. * config/rs6000/rs6000.h (PREFERRED_RELOAD_CLASS): Remove 'abort' from comment. From-SVN: r98658 --- gcc/ChangeLog | 37 ++ gcc/config/rs6000/rs6000.c | 893 ++++++++++++++++++++++---------------------- gcc/config/rs6000/rs6000.h | 2 +- gcc/config/rs6000/rs6000.md | 70 ++-- gcc/config/rs6000/spe.md | 4 +- 5 files changed, 528 insertions(+), 478 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9f2ee99..8b1c9e7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,40 @@ +2005-04-24 Nathan Sidwell + + * config/rs6000/rs6000.c (rs6000_override_options): Use gcc_assert + and gcc_unreachable as appropriate. + (num_insns_constant, output_vec_const_move, + build_mask64_2_operands, rs6000_output_dwarf_dtprel, + rs6000_emit_set_const, rs6000_emit_move, + spe_build_register_parallel, function_arg, + rs6000_move_block_from_reg, altivec_expand_predicate_builtin, + spe_expand_predicate_builtin, spe_expand_evsel_builtin, + rs6000_expand_builtin, spe_init_builtins, altivec_init_builtins, + rs6000_common_init_builtins, expand_block_clear, + expand_block_move, validate_condition_mode, ccr_bit, extract_MB, + extract_ME, rs6000_get_some_local_dynamic_name, + rs6000_output_function_entry, print_operand, + print_operand_address, rs6000_generate_compare, rs6000_emit_sCOND, + output_cbranch, output_e500_flip_gt_bit, + rs6000_emit_vector_compare, rs6000_emit_vector_compare, + rs6000_emit_cmove, rs6000_emit_minmax, rs6000_split_multireg_move, + compute_save_world_info, rs6000_stack_info, + rs6000_emit_load_toc_table, rs6000_frame_related, + spe_synthesize_frame_save, rs6000_emit_epilogue, + rs6000_output_function_epilogue, rs6000_hash_constant, output_toc, + output_function_profiler, rs6000_trampoline_size, + rs6000_initialize_trampoline, find_addr_reg, + rs6000_machopic_legitimize_pic_address, + rs6000_initial_elimination_offset, + rs6000_dbx_register_number): Likewise. + * config/rs6000/rs6000.md (*fix_truncdfsi2_internal, + *movdf_hardfloat32, *movdf_softfloat32, *fix_trunctfsi2_internal, + *movti_power, *movti_string, call, call_value, sibcall, + sibcall_value): Likewise. + * config/rs6000/spe.md (*movdf_e500_double, + *movv2si_internal): Likewise. + * config/rs6000/rs6000.h (PREFERRED_RELOAD_CLASS): Remove 'abort' + from comment. + 2005-04-24 Richard Henderson PR target/21101 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c980d7d..2397aee 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1589,7 +1589,7 @@ rs6000_override_options (const char *default_cpu) break; default: - abort (); + gcc_unreachable (); } } @@ -1849,8 +1849,11 @@ num_insns_constant_wide (HOST_WIDE_INT value) int num_insns_constant (rtx op, enum machine_mode mode) { - if (GET_CODE (op) == CONST_INT) + HOST_WIDE_INT low, high; + + switch (GET_CODE (op)) { + case CONST_INT: #if HOST_BITS_PER_WIDE_INT == 64 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 && mask64_operand (op, mode)) @@ -1858,65 +1861,57 @@ num_insns_constant (rtx op, enum machine_mode mode) else #endif return num_insns_constant_wide (INTVAL (op)); - } - - else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) - { - long l; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, op); - REAL_VALUE_TO_TARGET_SINGLE (rv, l); - return num_insns_constant_wide ((HOST_WIDE_INT) l); - } - - else if (GET_CODE (op) == CONST_DOUBLE) - { - HOST_WIDE_INT low; - HOST_WIDE_INT high; - long l[2]; - REAL_VALUE_TYPE rv; - int endian = (WORDS_BIG_ENDIAN == 0); - if (mode == VOIDmode || mode == DImode) - { - high = CONST_DOUBLE_HIGH (op); - low = CONST_DOUBLE_LOW (op); - } - else - { - REAL_VALUE_FROM_CONST_DOUBLE (rv, op); - REAL_VALUE_TO_TARGET_DOUBLE (rv, l); - high = l[endian]; - low = l[1 - endian]; - } - - if (TARGET_32BIT) - return (num_insns_constant_wide (low) - + num_insns_constant_wide (high)); - - else - { - if (high == 0 && low >= 0) - return num_insns_constant_wide (low); - - else if (high == -1 && low < 0) - return num_insns_constant_wide (low); - - else if (mask64_operand (op, mode)) - return 2; + case CONST_DOUBLE: + if (mode == SFmode) + { + long l; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + REAL_VALUE_TO_TARGET_SINGLE (rv, l); + return num_insns_constant_wide ((HOST_WIDE_INT) l); + } - else if (low == 0) - return num_insns_constant_wide (high) + 1; + if (mode == VOIDmode || mode == DImode) + { + high = CONST_DOUBLE_HIGH (op); + low = CONST_DOUBLE_LOW (op); + } + else + { + long l[2]; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + REAL_VALUE_TO_TARGET_DOUBLE (rv, l); + high = l[WORDS_BIG_ENDIAN == 0]; + low = l[WORDS_BIG_ENDIAN != 0]; + } - else - return (num_insns_constant_wide (high) - + num_insns_constant_wide (low) + 1); - } + if (TARGET_32BIT) + return (num_insns_constant_wide (low) + + num_insns_constant_wide (high)); + else + { + if ((high == 0 && low >= 0) + || (high == -1 && low < 0)) + return num_insns_constant_wide (low); + + else if (mask64_operand (op, mode)) + return 2; + + else if (low == 0) + return num_insns_constant_wide (high) + 1; + + else + return (num_insns_constant_wide (high) + + num_insns_constant_wide (low) + 1); + } + + default: + gcc_unreachable (); } - - else - abort (); } /* Returns the constant for the splat instruction, if exists. */ @@ -2006,66 +2001,61 @@ output_vec_const_move (rtx *operands) { if (zero_constant (vec, mode)) return "vxor %0,%0,%0"; - else if (easy_vector_constant (vec, mode)) + + gcc_assert (easy_vector_constant (vec, mode)); + + operands[1] = GEN_INT (cst); + switch (mode) { - operands[1] = GEN_INT (cst); - switch (mode) + case V4SImode: + if (EASY_VECTOR_15 (cst)) { - case V4SImode: - if (EASY_VECTOR_15 (cst)) - { - operands[1] = GEN_INT (cst); - return "vspltisw %0,%1"; - } - else if (EASY_VECTOR_15_ADD_SELF (cst)) - return "#"; - cst = cst >> 16; - /* Fall thru */ - - case V8HImode: - if (EASY_VECTOR_15 (cst)) - { - operands[1] = GEN_INT (cst); - return "vspltish %0,%1"; - } - else if (EASY_VECTOR_15_ADD_SELF (cst)) - return "#"; - cst = cst >> 8; - /* Fall thru */ + operands[1] = GEN_INT (cst); + return "vspltisw %0,%1"; + } + else if (EASY_VECTOR_15_ADD_SELF (cst)) + return "#"; + cst = cst >> 16; + /* Fall thru */ - case V16QImode: - if (EASY_VECTOR_15 (cst)) - { - operands[1] = GEN_INT (cst); - return "vspltisb %0,%1"; - } - else if (EASY_VECTOR_15_ADD_SELF (cst)) - return "#"; + case V8HImode: + if (EASY_VECTOR_15 (cst)) + { + operands[1] = GEN_INT (cst); + return "vspltish %0,%1"; + } + else if (EASY_VECTOR_15_ADD_SELF (cst)) + return "#"; + cst = cst >> 8; + /* Fall thru */ - default: - abort (); + case V16QImode: + if (EASY_VECTOR_15 (cst)) + { + operands[1] = GEN_INT (cst); + return "vspltisb %0,%1"; } + else if (EASY_VECTOR_15_ADD_SELF (cst)) + return "#"; + + default: + gcc_unreachable (); } - else - abort (); } - if (TARGET_SPE) - { - /* Vector constant 0 is handled as a splitter of V2SI, and in the - pattern of V1DI, V4HI, and V2SF. - - FIXME: We should probably return # and add post reload - splitters for these, but this way is so easy ;-). */ - operands[1] = GEN_INT (cst); - operands[2] = GEN_INT (cst2); - if (cst == cst2) - return "li %0,%1\n\tevmergelo %0,%0,%0"; - else - return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; - } - - abort (); + gcc_assert (TARGET_SPE); + + /* Vector constant 0 is handled as a splitter of V2SI, and in the + pattern of V1DI, V4HI, and V2SF. + + FIXME: We should probably return # and add post reload + splitters for these, but this way is so easy ;-). */ + operands[1] = GEN_INT (cst); + operands[2] = GEN_INT (cst2); + if (cst == cst2) + return "li %0,%1\n\tevmergelo %0,%0,%0"; + else + return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; } int @@ -2132,8 +2122,7 @@ build_mask64_2_operands (rtx in, rtx *out) unsigned HOST_WIDE_INT c, lsb, m1, m2; int shift; - if (GET_CODE (in) != CONST_INT) - abort (); + gcc_assert (GET_CODE (in) == CONST_INT); c = INTVAL (in); if (c & 1) @@ -2189,7 +2178,7 @@ build_mask64_2_operands (rtx in, rtx *out) #else (void)in; (void)out; - abort (); + gcc_unreachable (); #endif } @@ -2671,7 +2660,7 @@ rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) fputs (DOUBLE_INT_ASM_OP, file); break; default: - abort (); + gcc_unreachable (); } output_addr_const (file, x); fputs ("@dtprel+0x8000", file); @@ -3284,17 +3273,18 @@ rs6000_emit_set_const (rtx dest, enum machine_mode mode, rtx result, insn, set; HOST_WIDE_INT c0, c1; - if (mode == QImode || mode == HImode) + switch (mode) { + case QImode: + case HImode: if (dest == NULL) dest = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, dest, source)); return dest; - } - else if (mode == SImode) - { + + case SImode: result = no_new_pseudos ? dest : gen_reg_rtx (SImode); - + emit_insn (gen_rtx_SET (VOIDmode, result, GEN_INT (INTVAL (source) & (~ (HOST_WIDE_INT) 0xffff)))); @@ -3302,16 +3292,17 @@ rs6000_emit_set_const (rtx dest, enum machine_mode mode, gen_rtx_IOR (SImode, result, GEN_INT (INTVAL (source) & 0xffff)))); result = dest; - } - else if (mode == DImode) - { - if (GET_CODE (source) == CONST_INT) + break; + + case DImode: + switch (GET_CODE (source)) { + case CONST_INT: c0 = INTVAL (source); c1 = -(c0 < 0); - } - else if (GET_CODE (source) == CONST_DOUBLE) - { + break; + + case CONST_DOUBLE: #if HOST_BITS_PER_WIDE_INT >= 64 c0 = CONST_DOUBLE_LOW (source); c1 = -(c0 < 0); @@ -3319,14 +3310,18 @@ rs6000_emit_set_const (rtx dest, enum machine_mode mode, c0 = CONST_DOUBLE_LOW (source); c1 = CONST_DOUBLE_HIGH (source); #endif + break; + + default: + gcc_unreachable (); } - else - abort (); result = rs6000_emit_set_long_const (dest, c0, c1); + break; + + default: + gcc_unreachable (); } - else - abort (); insn = get_last_insn (); set = single_set (insn); @@ -3464,14 +3459,13 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) to a CONST_INT. */ operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); } - if (GET_CODE (operands[1]) == CONST_DOUBLE - && ! FLOAT_MODE_P (mode) - && ((CONST_DOUBLE_HIGH (operands[1]) == 0 - && CONST_DOUBLE_LOW (operands[1]) >= 0) - || (CONST_DOUBLE_HIGH (operands[1]) == -1 - && CONST_DOUBLE_LOW (operands[1]) < 0))) - abort (); - + gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE + || FLOAT_MODE_P (mode) + || ((CONST_DOUBLE_HIGH (operands[1]) != 0 + || CONST_DOUBLE_LOW (operands[1]) < 0) + && (CONST_DOUBLE_HIGH (operands[1]) != -1 + || CONST_DOUBLE_LOW (operands[1]) >= 0))); + /* Check if GCC is setting up a block move that will end up using FP registers as temporaries. We must make sure this is acceptable. */ if (GET_CODE (operands[0]) == MEM @@ -3769,7 +3763,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) break; default: - abort (); + gcc_unreachable (); } /* Above, we may have called force_const_mem which may have returned @@ -4329,22 +4323,23 @@ spe_build_register_parallel (enum machine_mode mode, int gregno) { rtx r1, r3; - if (mode == DFmode) + switch (mode) { + case DFmode: r1 = gen_rtx_REG (DImode, gregno); r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); - } - else if (mode == DCmode) - { + + case DCmode: r1 = gen_rtx_REG (DImode, gregno); r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); r3 = gen_rtx_REG (DImode, gregno + 2); r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); + + default: + gcc_unreachable (); } - abort (); - return NULL_RTX; } /* Determine where to put a SIMD argument on the SPE. */ @@ -4825,8 +4820,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, { /* Currently, we only ever need one reg here because complex doubles are split. */ - if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) - abort (); + gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode); /* Long double split over regs and memory. */ fmode = DFmode; @@ -5061,8 +5055,7 @@ rs6000_move_block_from_reg (int regno, rtx x, int nregs) else tem = replace_equiv_address (tem, XEXP (tem, 0)); - if (tem == NULL_RTX) - abort (); + gcc_assert (tem); emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); } @@ -6106,8 +6099,7 @@ altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, else cr6_form_int = TREE_INT_CST_LOW (cr6_form); - if (mode0 != mode1) - abort (); + gcc_assert (mode0 == mode1); /* If we have invalid arguments, bail out before generating bad rtl. */ if (arg0 == error_mark_node || arg1 == error_mark_node) @@ -6856,8 +6848,7 @@ spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) else form_int = TREE_INT_CST_LOW (form); - if (mode0 != mode1) - abort (); + gcc_assert (mode0 == mode1); if (arg0 == error_mark_node || arg1 == error_mark_node) return const0_rtx; @@ -6958,8 +6949,7 @@ spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) enum machine_mode mode0 = insn_data[icode].operand[1].mode; enum machine_mode mode1 = insn_data[icode].operand[2].mode; - if (mode0 != mode1) - abort (); + gcc_assert (mode0 == mode1); if (arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node || arg3 == error_mark_node) @@ -7022,12 +7012,10 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, tree arg; rtx op, addr, pat; - if (!TARGET_ALTIVEC) - abort (); + gcc_assert (TARGET_ALTIVEC); arg = TREE_VALUE (arglist); - if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE) - abort (); + gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); addr = memory_address (mode, op); if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) @@ -7070,29 +7058,27 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return ret; } - if (TARGET_ALTIVEC || TARGET_SPE) - { - /* Handle simple unary operations. */ - d = (struct builtin_description *) bdesc_1arg; - for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_unop_builtin (d->icode, arglist, target); - - /* Handle simple binary operations. */ - d = (struct builtin_description *) bdesc_2arg; - for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_binop_builtin (d->icode, arglist, target); - - /* Handle simple ternary operations. */ - d = (struct builtin_description *) bdesc_3arg; - for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_ternop_builtin (d->icode, arglist, target); - } + gcc_assert (TARGET_ALTIVEC || TARGET_SPE); + + /* Handle simple unary operations. */ + d = (struct builtin_description *) bdesc_1arg; + for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_unop_builtin (d->icode, arglist, target); + + /* Handle simple binary operations. */ + d = (struct builtin_description *) bdesc_2arg; + for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_binop_builtin (d->icode, arglist, target); - abort (); - return NULL_RTX; + /* Handle simple ternary operations. */ + d = (struct builtin_description *) bdesc_3arg; + for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_ternop_builtin (d->icode, arglist, target); + + gcc_unreachable (); } static tree @@ -7413,7 +7399,7 @@ spe_init_builtins (void) type = int_ftype_int_v2sf_v2sf; break; default: - abort (); + gcc_unreachable (); } def_builtin (d->mask, d->name, type, d->code); @@ -7434,7 +7420,7 @@ spe_init_builtins (void) type = v2sf_ftype_4_v2sf; break; default: - abort (); + gcc_unreachable (); } def_builtin (d->mask, d->name, type, d->code); @@ -7610,7 +7596,7 @@ altivec_init_builtins (void) type = int_ftype_int_v4sf_v4sf; break; default: - abort (); + gcc_unreachable (); } def_builtin (dp->mask, dp->name, type, dp->code); @@ -7640,7 +7626,7 @@ altivec_init_builtins (void) type = v4sf_ftype_v4sf; break; default: - abort (); + gcc_unreachable (); } def_builtin (d->mask, d->name, type, d->code); @@ -7886,7 +7872,7 @@ rs6000_common_init_builtins (void) type = v16qi_ftype_v16qi_v16qi_v16qi; break; default: - abort (); + gcc_unreachable (); } } else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) @@ -7906,7 +7892,7 @@ rs6000_common_init_builtins (void) type = v16qi_ftype_v16qi_v16qi_v16qi; break; default: - abort (); + gcc_unreachable (); } } else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode @@ -7940,7 +7926,7 @@ rs6000_common_init_builtins (void) type = v4sf_ftype_v4sf_v4sf_int; else - abort (); + gcc_unreachable (); def_builtin (d->mask, d->name, type, d->code); } @@ -7986,7 +7972,7 @@ rs6000_common_init_builtins (void) type = int_ftype_int_int; break; default: - abort (); + gcc_unreachable (); } } @@ -8053,9 +8039,10 @@ rs6000_common_init_builtins (void) else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) type = v2si_ftype_int_char; - /* int, x, x. */ - else if (mode0 == SImode) + else { + /* int, x, x. */ + gcc_assert (mode0 == SImode); switch (mode1) { case V4SImode: @@ -8071,13 +8058,10 @@ rs6000_common_init_builtins (void) type = int_ftype_v8hi_v8hi; break; default: - abort (); + gcc_unreachable (); } } - else - abort (); - def_builtin (d->mask, d->name, type, d->code); } @@ -8117,7 +8101,7 @@ rs6000_common_init_builtins (void) else if (mode0 == V2SImode && mode1 == QImode) type = v2si_ftype_char; else - abort (); + gcc_unreachable (); def_builtin (d->mask, d->name, type, d->code); } @@ -8210,9 +8194,8 @@ expand_block_clear (rtx operands[]) if (! constp) return 0; - /* If this is not a fixed size alignment, abort */ - if (GET_CODE (align_rtx) != CONST_INT) - abort (); + /* This must be a fixed size alignment */ + gcc_assert (GET_CODE (align_rtx) == CONST_INT); align = INTVAL (align_rtx) * BITS_PER_UNIT; /* Anything to clear? */ @@ -8308,9 +8291,8 @@ expand_block_move (rtx operands[]) if (! constp) return 0; - /* If this is not a fixed size alignment, abort */ - if (GET_CODE (align_rtx) != CONST_INT) - abort (); + /* This must be a fixed size alignment */ + gcc_assert (GET_CODE (align_rtx) == CONST_INT); align = INTVAL (align_rtx) * BITS_PER_UNIT; /* Anything to move? */ @@ -8526,40 +8508,33 @@ rs6000_output_load_multiple (rtx operands[3]) void validate_condition_mode (enum rtx_code code, enum machine_mode mode) { - if ((GET_RTX_CLASS (code) != RTX_COMPARE - && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) - || GET_MODE_CLASS (mode) != MODE_CC) - abort (); + gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE + || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) + && GET_MODE_CLASS (mode) == MODE_CC); /* These don't make sense. */ - if ((code == GT || code == LT || code == GE || code == LE) - && mode == CCUNSmode) - abort (); + gcc_assert ((code != GT && code != LT && code != GE && code != LE) + || mode != CCUNSmode); - if ((code == GTU || code == LTU || code == GEU || code == LEU) - && mode != CCUNSmode) - abort (); + gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) + || mode == CCUNSmode); - if (mode != CCFPmode - && (code == ORDERED || code == UNORDERED - || code == UNEQ || code == LTGT - || code == UNGT || code == UNLT - || code == UNGE || code == UNLE)) - abort (); + gcc_assert (mode == CCFPmode + || (code != ORDERED && code != UNORDERED + && code != UNEQ && code != LTGT + && code != UNGT && code != UNLT + && code != UNGE && code != UNLE)); /* These should never be generated except for flag_finite_math_only. */ - if (mode == CCFPmode - && ! flag_finite_math_only - && (code == LE || code == GE - || code == UNEQ || code == LTGT - || code == UNGT || code == UNLT)) - abort (); + gcc_assert (mode != CCFPmode + || flag_finite_math_only + || (code != LE && code != GE + && code != UNEQ && code != LTGT + && code != UNGT && code != UNLT)); /* These are invalid; the information is not there. */ - if (mode == CCEQmode - && code != EQ && code != NE) - abort (); + gcc_assert (mode != CCEQmode || code == EQ || code == NE); } @@ -8954,9 +8929,7 @@ ccr_bit (rtx op, int scc_p) reg = XEXP (op, 0); - if (GET_CODE (reg) != REG - || ! CR_REGNO_P (REGNO (reg))) - abort (); + gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); cc_mode = GET_MODE (reg); cc_regnum = REGNO (reg); @@ -8966,9 +8939,9 @@ ccr_bit (rtx op, int scc_p) /* When generating a sCOND operation, only positive conditions are allowed. */ - if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED - && code != GTU && code != LTU) - abort (); + gcc_assert (!scc_p + || code == EQ || code == GT || code == LT || code == UNORDERED + || code == GTU || code == LTU); switch (code) { @@ -8993,7 +8966,7 @@ ccr_bit (rtx op, int scc_p) return scc_p ? base_bit + 3 : base_bit + 1; default: - abort (); + gcc_unreachable (); } } @@ -9041,8 +9014,7 @@ extract_MB (rtx op) from the left. */ if ((val & 0x80000000) == 0) { - if ((val & 0xffffffff) == 0) - abort (); + gcc_assert (val & 0xffffffff); i = 1; while (((val <<= 1) & 0x80000000) == 0) @@ -9074,8 +9046,7 @@ extract_ME (rtx op) the right. */ if ((val & 1) == 0) { - if ((val & 0xffffffff) == 0) - abort (); + gcc_assert (val & 0xffffffff); i = 30; while (((val >>= 1) & 1) == 0) @@ -9115,7 +9086,7 @@ rs6000_get_some_local_dynamic_name (void) rs6000_get_some_local_dynamic_name_1, 0)) return cfun->machine->some_ld_name; - abort (); + gcc_unreachable (); } /* Helper function for rs6000_get_some_local_dynamic_name. */ @@ -9148,7 +9119,7 @@ rs6000_output_function_entry (FILE *file, const char *fname) switch (DEFAULT_ABI) { default: - abort (); + gcc_unreachable (); case ABI_AIX: if (DOT_SYMBOLS) @@ -9234,8 +9205,7 @@ print_operand (FILE *file, rtx x, int code) case 'D': /* Like 'J' but get to the EQ bit. */ - if (GET_CODE (x) != REG) - abort (); + gcc_assert (GET_CODE (x) == REG); /* Bit 1 is EQ bit. */ i = 4 * (REGNO (x) - CR0_REGNO) + 2; @@ -9527,15 +9497,13 @@ print_operand (FILE *file, rtx x, int code) } while (uval != 0) --i, uval >>= 1; - if (i < 0) - abort (); + gcc_assert (i >= 0); fprintf (file, "%d", i); return; case 't': /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ - if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) - abort (); + gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); /* Bit 3 is OV bit. */ i = 4 * (REGNO (x) - CR0_REGNO) + 3; @@ -9616,7 +9584,7 @@ print_operand (FILE *file, rtx x, int code) fputs ("lge", file); /* 5 */ break; default: - abort (); + gcc_unreachable (); } break; @@ -9649,9 +9617,8 @@ print_operand (FILE *file, rtx x, int code) { val = CONST_DOUBLE_LOW (x); - if (val == 0) - abort (); - else if (val < 0) + gcc_assert (val); + if (val < 0) --i; else for ( ; i < 64; i++) @@ -9692,8 +9659,7 @@ print_operand (FILE *file, rtx x, int code) names. If we are configured for System V (or the embedded ABI) on the PowerPC, do not emit the period, since those systems do not use TOCs and the like. */ - if (GET_CODE (x) != SYMBOL_REF) - abort (); + gcc_assert (GET_CODE (x) == SYMBOL_REF); /* Mark the decl as referenced so that cgraph will output the function. */ @@ -9739,8 +9705,7 @@ print_operand (FILE *file, rtx x, int code) { rtx tmp; - if (GET_CODE (x) != MEM) - abort (); + gcc_assert (GET_CODE (x) == MEM); tmp = XEXP (x, 0); @@ -9758,8 +9723,7 @@ print_operand (FILE *file, rtx x, int code) { int x; - if (GET_CODE (XEXP (tmp, 0)) != REG) - abort (); + gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); x = INTVAL (XEXP (tmp, 1)); fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); @@ -9775,8 +9739,11 @@ print_operand (FILE *file, rtx x, int code) tmp = XEXP (tmp, 0); if (GET_CODE (tmp) == REG) fprintf (file, "0,%s", reg_names[REGNO (tmp)]); - else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) + else { + gcc_assert (GET_CODE (tmp) == PLUS + && GET_CODE (XEXP (tmp, 1)) == REG); + if (REGNO (XEXP (tmp, 0)) == 0) fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], reg_names[ REGNO (XEXP (tmp, 0)) ]); @@ -9784,8 +9751,6 @@ print_operand (FILE *file, rtx x, int code) fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], reg_names[ REGNO (XEXP (tmp, 1)) ]); } - else - abort (); break; } @@ -9832,8 +9797,8 @@ print_operand_address (FILE *file, rtx x) if (small_data_operand (x, GET_MODE (x))) fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[SMALL_DATA_REG]); - else if (TARGET_TOC) - abort (); + else + gcc_assert (!TARGET_TOC); } else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) { @@ -9901,7 +9866,7 @@ print_operand_address (FILE *file, rtx x) fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); } else - abort (); + gcc_unreachable (); } /* Target hook for assembling integer objects. The PowerPC version has @@ -10057,52 +10022,78 @@ rs6000_generate_compare (enum rtx_code code) switch (code) { case EQ: case UNEQ: case NE: case LTGT: - if (op_mode == SFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else if (op_mode == DFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else abort (); + switch (op_mode) + { + case SFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + case DFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + default: + gcc_unreachable (); + } break; + case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: - if (op_mode == SFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else if (op_mode == DFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else abort (); + switch (op_mode) + { + case SFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + case DFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + default: + gcc_unreachable (); + } break; + case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: - if (op_mode == SFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else if (op_mode == DFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, - rs6000_compare_op1); - else abort (); + switch (op_mode) + { + case SFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + case DFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + + default: + gcc_unreachable (); + } break; default: - abort (); + gcc_unreachable (); } /* Synthesize LE and GE from LT/GT || EQ. */ @@ -10116,25 +10107,33 @@ rs6000_generate_compare (enum rtx_code code) case GE: code = GT; break; case LEU: code = LT; break; case GEU: code = GT; break; - default: abort (); + default: gcc_unreachable (); } compare_result2 = gen_reg_rtx (CCFPmode); /* Do the EQ. */ - if (op_mode == SFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, - rs6000_compare_op1); - else if (op_mode == DFmode) - cmp = flag_unsafe_math_optimizations - ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, - rs6000_compare_op1) - : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, - rs6000_compare_op1); - else abort (); + switch (op_mode) + { + case SFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1); + break; + + case DFmode: + cmp = flag_unsafe_math_optimizations + ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1); + break; + + default: + gcc_unreachable (); + } emit_insn (cmp); /* OR them together. */ @@ -10205,7 +10204,7 @@ rs6000_generate_compare (enum rtx_code code) case LTGT: or1 = LT; or2 = GT; break; case UNGT: or1 = UNORDERED; or2 = GT; break; case UNLT: or1 = UNORDERED; or2 = LT; break; - default: abort (); + default: gcc_unreachable (); } validate_condition_mode (or1, comp_mode); validate_condition_mode (or2, comp_mode); @@ -10246,8 +10245,7 @@ rs6000_emit_sCOND (enum rtx_code code, rtx result) PUT_MODE (condition_rtx, SImode); t = XEXP (condition_rtx, 0); - if (cond_code != NE && cond_code != EQ) - abort (); + gcc_assert (cond_code == NE || cond_code == EQ); if (cond_code == NE) emit_insn (gen_e500_flip_gt_bit (t, t)); @@ -10350,13 +10348,20 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) { /* The efscmp/tst* instructions twiddle bit 2, which maps nicely to the GT bit. */ - if (code == EQ) - /* Opposite of GT. */ - code = GT; - else if (code == NE) - code = UNLE; - else - abort (); + switch (code) + { + case EQ: + /* Opposite of GT. */ + code = GT; + break; + + case NE: + code = UNLE; + break; + + default: + gcc_unreachable (); + } } switch (code) @@ -10380,7 +10385,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) case UNGE: ccode = "nl"; break; case UNLE: ccode = "ng"; break; default: - abort (); + gcc_unreachable (); } /* Maybe we have a guess as to how likely the branch is. @@ -10440,9 +10445,8 @@ output_e500_flip_gt_bit (rtx dst, rtx src) static char string[64]; int a, b; - if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) - || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) - abort (); + gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) + && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); /* GT bit. */ a = 4 * (REGNO (dst) - CR0_REGNO) + 1; @@ -10516,13 +10520,8 @@ rs6000_emit_vector_compare (enum rtx_code rcode, enum machine_mode dest_mode; enum machine_mode op_mode = GET_MODE (op1); -#ifdef ENABLE_CHECKING - if (!TARGET_ALTIVEC) - abort (); - - if (GET_MODE (op0) != GET_MODE (op1)) - abort (); -#endif + gcc_assert (TARGET_ALTIVEC); + gcc_assert (GET_MODE (op0) == GET_MODE (op1)); /* Floating point vector compare instructions uses destination V4SImode. Move destination to appropriate mode later. */ @@ -10558,8 +10557,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode, dest_mode); nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; - if (nor_code == CODE_FOR_nothing) - abort (); + gcc_assert (nor_code != CODE_FOR_nothing); emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); if (dmode != dest_mode) @@ -10581,16 +10579,27 @@ rs6000_emit_vector_compare (enum rtx_code rcode, enum insn_code ior_code; enum rtx_code new_code; - if (rcode == GE) - new_code = GT; - else if (rcode == GEU) - new_code = GTU; - else if (rcode == LE) - new_code = LT; - else if (rcode == LEU) - new_code = LTU; - else - abort (); + switch (rcode) + { + case GE: + new_code = GT; + break; + + case GEU: + new_code = GTU; + break; + + case LE: + new_code = LT; + break; + + case LEU: + new_code = LTU; + break; + + default: + gcc_unreachable (); + } c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dest_mode); @@ -10598,8 +10607,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode, dest_mode); ior_code = ior_optab->handlers[(int)dest_mode].insn_code; - if (ior_code == CODE_FOR_nothing) - abort (); + gcc_assert (ior_code != CODE_FOR_nothing); emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); if (dmode != dest_mode) { @@ -10611,15 +10619,14 @@ rs6000_emit_vector_compare (enum rtx_code rcode, } break; default: - abort (); + gcc_unreachable (); } if (try_again) { vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); - if (vec_cmp_insn == INSN_NOT_AVAILABLE) - /* You only get two chances. */ - abort (); + /* You only get two chances. */ + gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); } if (swap_operands) @@ -10892,7 +10899,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) break; default: - abort (); + gcc_unreachable (); } emit_insn (gen_rtx_SET (VOIDmode, dest, @@ -10963,8 +10970,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) else target = emit_conditional_move (dest, c, op0, op1, mode, op1, op0, mode, 0); - if (target == NULL_RTX) - abort (); + gcc_assert (target); if (target != dest) emit_move_insn (dest, target); } @@ -11176,8 +11182,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) reg_mode = word_mode; reg_mode_size = GET_MODE_SIZE (reg_mode); - if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) - abort (); + gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { @@ -11268,8 +11273,8 @@ rs6000_split_multireg_move (rtx dst, rtx src) : gen_adddi3 (breg, breg, delta_rtx)); dst = gen_rtx_MEM (mode, breg); } - else if (! offsettable_memref_p (dst)) - abort (); + else + gcc_assert (offsettable_memref_p (dst)); } for (i = 0; i < nregs; i++) @@ -11440,9 +11445,9 @@ compute_save_world_info (rs6000_stack_t *info_ptr) /* Because the Darwin register save/restore routines only handle F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency check and abort if there's something worng. */ - if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO - || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO) - abort (); + gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO + && (info_ptr->first_altivec_reg_save + >= FIRST_SAVED_ALTIVEC_REGNO)); } return; } @@ -11695,7 +11700,7 @@ rs6000_stack_info (void) { case ABI_NONE: default: - abort (); + gcc_unreachable (); case ABI_AIX: case ABI_DARWIN: @@ -12245,8 +12250,10 @@ rs6000_emit_load_toc_table (int fromprolog) if (fromprolog) rs6000_maybe_dead (insn); } - else if (DEFAULT_ABI == ABI_AIX) + else { + gcc_assert (DEFAULT_ABI == ABI_AIX); + if (TARGET_32BIT) insn = emit_insn (gen_load_toc_aix_si (dest)); else @@ -12254,8 +12261,6 @@ rs6000_emit_load_toc_table (int fromprolog) if (fromprolog) rs6000_maybe_dead (insn); } - else - abort (); } /* Emit instructions to restore the link register after determining where @@ -12538,9 +12543,11 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, XEXP (SET_DEST (set), 0) = temp; } } - else if (GET_CODE (real) == PARALLEL) + else { int i; + + gcc_assert (GET_CODE (real) == PARALLEL); for (i = 0; i < XVECLEN (real, 0); i++) if (GET_CODE (XVECEXP (real, 0, i)) == SET) { @@ -12561,8 +12568,6 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, RTX_FRAME_RELATED_P (set) = 1; } } - else - abort (); if (TARGET_SPE) real = spe_synthesize_frame_save (real); @@ -12591,10 +12596,9 @@ spe_synthesize_frame_save (rtx real) This is so we can differentiate between 64-bit and 32-bit saves. Words cannot describe this nastiness. */ - if (GET_CODE (SET_DEST (real)) != MEM - || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS - || GET_CODE (SET_SRC (real)) != REG) - abort (); + gcc_assert (GET_CODE (SET_DEST (real)) == MEM + && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS + && GET_CODE (SET_SRC (real)) == REG); /* Transform: (set (mem (plus (reg x) (const y))) @@ -12849,16 +12853,16 @@ rs6000_emit_prologue (void) /* The SAVE_WORLD and RESTORE_WORLD routines make a number of assumptions about the offsets of various bits of the stack frame. Abort if things aren't what they should be. */ - if (info->gp_save_offset != -220 - || info->fp_save_offset != -144 - || info->lr_save_offset != 8 - || info->cr_save_offset != 4 - || !info->push_p - || !info->lr_save_p - || (current_function_calls_eh_return && info->ehrd_offset != -432) - || (info->vrsave_save_offset != -224 - || info->altivec_save_offset != (-224 -16 -192))) - abort (); + gcc_assert (info->gp_save_offset == -220 + && info->fp_save_offset == -144 + && info->lr_save_offset == 8 + && info->cr_save_offset == 4 + && info->push_p + && info->lr_save_p + && (!current_function_calls_eh_return + || info->ehrd_offset == -432) + && info->vrsave_save_offset == -224 + && info->altivec_save_offset == (-224 -16 -192)); treg = gen_rtx_REG (SImode, 11); emit_move_insn (treg, GEN_INT (-info->total_size)); @@ -13752,8 +13756,7 @@ rs6000_emit_epilogue (int sibcall) for (i = 0; i < 8; i++) if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) count++; - if (count == 0) - abort (); + gcc_assert (count); } if (using_mfcr_multiple && count > 1) @@ -13776,8 +13779,7 @@ rs6000_emit_epilogue (int sibcall) ndx++; } emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); - if (ndx != count) - abort (); + gcc_assert (ndx == count); } else for (i = 0; i < 8; i++) @@ -14012,7 +14014,7 @@ rs6000_output_function_epilogue (FILE *file, else if (! strcmp (language_string, "GNU Objective-C")) i = 14; else - abort (); + gcc_unreachable (); fprintf (file, "%d,", i); /* 8 single bit fields: global linkage (not set for C extern linkage, @@ -14065,12 +14067,20 @@ rs6000_output_function_epilogue (FILE *file, float_parms++; - if (mode == SFmode) - bits = 0x2; - else if (mode == DFmode || mode == TFmode) - bits = 0x3; - else - abort (); + switch (mode) + { + case SFmode: + bits = 0x2; + break; + + case DFmode: + case TFmode: + bits = 0x3; + break; + + default: + gcc_unreachable (); + } /* If only one bit will fit, don't or in this entry. */ if (next_parm_info_bit > 0) @@ -14384,7 +14394,7 @@ rs6000_hash_constant (rtx k) case '0': break; default: - abort (); + gcc_unreachable (); } return result; @@ -14456,8 +14466,7 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) rtx base = x; int offset = 0; - if (TARGET_NO_TOC) - abort (); + gcc_assert (!TARGET_NO_TOC); /* When the linker won't eliminate them, don't output duplicate TOC entries (this happens on AIX if there is any kind of TOC, @@ -14636,8 +14645,8 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) For a 32-bit target, CONST_INT values are loaded and shifted entirely within `low' and can be stored in one TOC entry. */ - if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) - abort ();/* It would be easy to make this work, but it doesn't now. */ + /* It would be easy to make this work, but it doesn't now. */ + gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) { @@ -14689,21 +14698,30 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) if (GET_CODE (x) == CONST) { - if (GET_CODE (XEXP (x, 0)) != PLUS) - abort (); + gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); base = XEXP (XEXP (x, 0), 0); offset = INTVAL (XEXP (XEXP (x, 0), 1)); } - if (GET_CODE (base) == SYMBOL_REF) - name = XSTR (base, 0); - else if (GET_CODE (base) == LABEL_REF) - ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); - else if (GET_CODE (base) == CODE_LABEL) - ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); - else - abort (); + switch (GET_CODE (base)) + { + case SYMBOL_REF: + name = XSTR (base, 0); + break; + + case LABEL_REF: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (base, 0))); + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); + break; + + default: + gcc_unreachable (); + } real_name = (*targetm.strip_name_encoding) (name); if (TARGET_MINIMAL_TOC) @@ -14921,7 +14939,7 @@ output_function_profiler (FILE *file, int labelno) switch (DEFAULT_ABI) { default: - abort (); + gcc_unreachable (); case ABI_V4: save_lr = 4; @@ -14981,8 +14999,7 @@ output_function_profiler (FILE *file, int labelno) } else { - if (TARGET_32BIT) - abort (); + gcc_assert (!TARGET_32BIT); asm_fprintf (file, "\tmflr %s\n", reg_names[0]); asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); @@ -15900,7 +15917,7 @@ rs6000_trampoline_size (void) switch (DEFAULT_ABI) { default: - abort (); + gcc_unreachable (); case ABI_AIX: ret = (TARGET_32BIT) ? 12 : 24; @@ -15929,7 +15946,7 @@ rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) switch (DEFAULT_ABI) { default: - abort (); + gcc_unreachable (); /* Macros to shorten the code expansions below. */ #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) @@ -16309,11 +16326,10 @@ find_addr_reg (rtx addr) else if (CONSTANT_P (XEXP (addr, 1))) addr = XEXP (addr, 0); else - abort (); + gcc_unreachable (); } - if (GET_CODE (addr) == REG && REGNO (addr) != 0) - return addr; - abort (); + gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); + return addr; } void @@ -16586,26 +16602,23 @@ rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, if (GET_CODE (orig) == CONST) { + rtx reg_temp; + if (GET_CODE (XEXP (orig, 0)) == PLUS && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) return orig; - if (GET_CODE (XEXP (orig, 0)) == PLUS) - { - /* Use a different reg for the intermediate value, as - it will be marked UNCHANGING. */ - rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); - - base = - rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), - Pmode, reg_temp); - offset = - rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), - Pmode, reg); - } - else - abort (); - + gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); + + /* Use a different reg for the intermediate value, as + it will be marked UNCHANGING. */ + reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); + base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), + Pmode, reg_temp); + offset = + rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), + Pmode, reg); + if (GET_CODE (offset) == CONST_INT) { if (SMALL_INT (offset)) @@ -17611,7 +17624,7 @@ rs6000_initial_elimination_offset (int from, int to) else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) offset = 0; else - abort (); + gcc_unreachable (); return offset; } @@ -17684,10 +17697,8 @@ rs6000_dbx_register_number (unsigned int regno) return 612; /* SPE high reg number. We get these values of regno from rs6000_dwarf_register_span. */ - if (regno >= 1200 && regno < 1232) - return regno; - - abort (); + gcc_assert (regno >= 1200 && regno < 1232); + return regno; } /* target hook eh_return_filter_mode */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index adef695..137e6dd 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1393,7 +1393,7 @@ enum reg_class We also don't want to reload integer values into floating-point registers if we can at all help it. In fact, this can - cause reload to abort, if it tries to generate a reload of CTR + cause reload to die, if it tries to generate a reload of CTR into a FP register and discovers it doesn't have the memory location required. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3c3e4c7..c40731c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5194,8 +5194,7 @@ " { rtx lowword, highword; - if (GET_CODE (operands[4]) != MEM) - abort(); + gcc_assert (GET_CODE (operands[4]) == MEM); highword = XEXP (operands[4], 0); lowword = plus_constant (highword, 4); if (! WORDS_BIG_ENDIAN) @@ -5278,8 +5277,7 @@ " { rtx lowword, highword; - if (GET_CODE (operands[4]) != MEM) - abort(); + gcc_assert (GET_CODE (operands[4]) == MEM); highword = XEXP (operands[4], 0); lowword = plus_constant (highword, 4); if (! WORDS_BIG_ENDIAN) @@ -5338,8 +5336,7 @@ " { rtx lowword; - if (GET_CODE (operands[3]) != MEM) - abort(); + gcc_assert (GET_CODE (operands[3]) == MEM); lowword = XEXP (operands[3], 0); if (WORDS_BIG_ENDIAN) lowword = plus_constant (lowword, 4); @@ -8149,7 +8146,7 @@ switch (which_alternative) { default: - abort (); + gcc_unreachable (); case 0: /* We normally copy the low-numbered register first. However, if the first register operand 0 is the same as the second register @@ -8246,7 +8243,7 @@ switch (which_alternative) { default: - abort (); + gcc_unreachable (); case 0: /* We normally copy the low-numbered register first. However, if the first register operand 0 is the same as the second register of @@ -8485,8 +8482,7 @@ rtx lowword; emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); - if (GET_CODE (operands[5]) != MEM) - abort(); + gcc_assert (GET_CODE (operands[5]) == MEM); lowword = XEXP (operands[5], 0); if (WORDS_BIG_ENDIAN) lowword = plus_constant (lowword, 4); @@ -8738,7 +8734,7 @@ switch (which_alternative) { default: - abort (); + gcc_unreachable (); case 0: if (TARGET_STRING) @@ -8770,7 +8766,7 @@ switch (which_alternative) { default: - abort (); + gcc_unreachable (); case 0: if (TARGET_STRING) return \"{stsi|stswi} %1,%P0,16\"; @@ -10332,8 +10328,8 @@ operands[0] = machopic_indirect_call_target (operands[0]); #endif - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) - abort (); + gcc_assert (GET_CODE (operands[0]) == MEM); + gcc_assert (GET_CODE (operands[1]) == CONST_INT); operands[0] = XEXP (operands[0], 0); @@ -10344,12 +10340,14 @@ if (INTVAL (operands[2]) & CALL_LONG) operands[0] = rs6000_longcall_ref (operands[0]); - if (DEFAULT_ABI == ABI_V4 - || DEFAULT_ABI == ABI_DARWIN) - operands[0] = force_reg (Pmode, operands[0]); + switch (DEFAULT_ABI) + { + case ABI_V4: + case ABI_DARWIN: + operands[0] = force_reg (Pmode, operands[0]); + break; - else if (DEFAULT_ABI == ABI_AIX) - { + case ABI_AIX: /* AIX function pointers are really pointers to a three word area. */ emit_call_insn (TARGET_32BIT @@ -10360,9 +10358,10 @@ operands[0]), operands[1])); DONE; + + default: + gcc_unreachable (); } - else - abort (); } }") @@ -10380,8 +10379,8 @@ operands[1] = machopic_indirect_call_target (operands[1]); #endif - if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) - abort (); + gcc_assert (GET_CODE (operands[1]) == MEM); + gcc_assert (GET_CODE (operands[2]) == CONST_INT); operands[1] = XEXP (operands[1], 0); @@ -10392,12 +10391,14 @@ if (INTVAL (operands[3]) & CALL_LONG) operands[1] = rs6000_longcall_ref (operands[1]); - if (DEFAULT_ABI == ABI_V4 - || DEFAULT_ABI == ABI_DARWIN) - operands[1] = force_reg (Pmode, operands[1]); + switch (DEFAULT_ABI) + { + case ABI_V4: + case ABI_DARWIN: + operands[1] = force_reg (Pmode, operands[1]); + break; - else if (DEFAULT_ABI == ABI_AIX) - { + case ABI_AIX: /* AIX function pointers are really pointers to a three word area. */ emit_call_insn (TARGET_32BIT @@ -10410,9 +10411,10 @@ operands[1]), operands[2])); DONE; + + default: + gcc_unreachable (); } - else - abort (); } }") @@ -10749,8 +10751,8 @@ operands[0] = machopic_indirect_call_target (operands[0]); #endif - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) - abort (); + gcc_assert (GET_CODE (operands[0]) == MEM); + gcc_assert (GET_CODE (operands[1]) == CONST_INT); operands[0] = XEXP (operands[0], 0); operands[3] = gen_reg_rtx (SImode); @@ -10935,8 +10937,8 @@ operands[1] = machopic_indirect_call_target (operands[1]); #endif - if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) - abort (); + gcc_assert (GET_CODE (operands[1]) == MEM); + gcc_assert (GET_CODE (operands[2]) == CONST_INT); operands[1] = XEXP (operands[1], 0); operands[4] = gen_reg_rtx (SImode); diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 79d03ff..32c5965 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2247,7 +2247,7 @@ case 2: return \"evstdd%X0 %1,%y0\"; default: - abort (); + gcc_unreachable (); } }" [(set_attr "type" "*,vecload,vecstore") @@ -2327,7 +2327,7 @@ case 1: return \"evldd%X1 %0,%y1\"; case 2: return \"evor %0,%1,%1\"; case 3: return output_vec_const_move (operands); - default: abort (); + default: gcc_unreachable (); } }" [(set_attr "type" "vecload,vecstore,*,*") -- 2.7.4