From 37334ea67a8a3132ecae53888c82f35f958d9a7a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 21 Apr 2018 21:59:36 +0000 Subject: [PATCH] [X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models. llvm-svn: 330527 --- llvm/lib/Target/X86/X86SchedBroadwell.td | 25 ---------- llvm/lib/Target/X86/X86SchedHaswell.td | 19 +------- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 29 +---------- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 73 ++-------------------------- llvm/lib/Target/X86/X86ScheduleZnver1.td | 3 -- 5 files changed, 6 insertions(+), 143 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 6760ad0..3fc7643 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -352,11 +352,7 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr", "MMX_MOVQ2DQrr", "(V?)MOV64toPQIrr", - "(V?)MOVAPD(Y?)rr", - "(V?)MOVAPS(Y?)rr", "(V?)MOVDI2PDIrr", - "(V?)MOVUPD(Y?)rr", - "(V?)MOVUPS(Y?)rr", "(V?)PBLENDW(Y?)rri", "(V?)PSLLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri")>; @@ -416,10 +412,6 @@ def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { let ResourceCycles = [1]; } def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr", - "(V?)MOVDQA(Y?)rr", - "(V?)MOVDQU(Y?)rr", - "(V?)MOVPQI2QIrr", - "VMOVZPQILo2PQIrr", "VPBLENDD(Y?)rri")>; def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { @@ -878,27 +870,10 @@ def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16", "MOVSX(16|32|64)rm8", "MOVZX(16|32|64)rm16", "MOVZX(16|32|64)rm8", - "PREFETCHNTA", - "PREFETCHT0", - "PREFETCHT1", - "PREFETCHT2", "VBROADCASTSSrm", - "(V?)LDDQUrm", - "(V?)MOV64toPQIrm", - "(V?)MOVAPDrm", - "(V?)MOVAPSrm", "(V?)MOVDDUPrm", - "(V?)MOVDI2PDIrm", - "(V?)MOVDQArm", - "(V?)MOVDQUrm", - "(V?)MOVNTDQArm", - "(V?)MOVQI2PQIrm", - "(V?)MOVSDrm", "(V?)MOVSHDUPrm", "(V?)MOVSLDUPrm", - "(V?)MOVSSrm", - "(V?)MOVUPDrm", - "(V?)MOVUPSrm", "VPBROADCASTDrm", "VPBROADCASTQrm")>; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index d7adb64..e992440 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -622,16 +622,7 @@ def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16", "MOVSX(16|32|64)rm8", "MOVZX(16|32|64)rm16", "MOVZX(16|32|64)rm8", - "PREFETCHNTA", - "PREFETCHT0", - "PREFETCHT1", - "PREFETCHT2", - "(V?)MOV64toPQIrm", - "(V?)MOVDDUPrm", - "(V?)MOVDI2PDIrm", - "(V?)MOVQI2PQIrm", - "(V?)MOVSDrm", - "(V?)MOVSSrm")>; + "(V?)MOVDDUPrm")>; def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { let Latency = 1; @@ -703,11 +694,7 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr", "MMX_MOVQ2DQrr", "(V?)MOV64toPQIrr", - "(V?)MOVAPD(Y?)rr", - "(V?)MOVAPS(Y?)rr", "(V?)MOVDI2PDIrr", - "(V?)MOVUPD(Y?)rr", - "(V?)MOVUPS(Y?)rr", "(V?)PBLENDW(Y?)rri", "(V?)PSLLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri")>; @@ -769,10 +756,6 @@ def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { let ResourceCycles = [1]; } def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr", - "(V?)MOVDQA(Y?)rr", - "(V?)MOVDQU(Y?)rr", - "(V?)MOVPQI2QIrr", - "VMOVZPQILo2PQIrr", "VPBLENDD(Y?)rri")>; def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 1672aea..8f686bf 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -497,15 +497,7 @@ def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKLWriteResGroup9], (instregex "(V?)MOVAPD(Y?)rr", - "(V?)MOVAPS(Y?)rr", - "(V?)MOVDQA(Y?)rr", - "(V?)MOVDQU(Y?)rr", - "(V?)MOVPQI2QIrr", - "(V?)MOVUPD(Y?)rr", - "(V?)MOVUPS(Y?)rr", - "(V?)MOVZPQILo2PQIrr", - "(V?)PADDB(Y?)rr", +def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADDB(Y?)rr", "(V?)PADDD(Y?)rr", "(V?)PADDQ(Y?)rr", "(V?)PADDW(Y?)rr", @@ -1053,16 +1045,7 @@ def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", "MOVSX(16|32|64)rm8", "MOVZX(16|32|64)rm16", "MOVZX(16|32|64)rm8", - "PREFETCHNTA", - "PREFETCHT0", - "PREFETCHT1", - "PREFETCHT2", - "(V?)MOV64toPQIrm", - "(V?)MOVDDUPrm", - "(V?)MOVDI2PDIrm", - "(V?)MOVQI2PQIrm", - "(V?)MOVSDrm", - "(V?)MOVSSrm")>; + "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { let Latency = 5; @@ -1135,16 +1118,8 @@ def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { let ResourceCycles = [1]; } def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm", - "(V?)LDDQUrm", - "(V?)MOVAPDrm", - "(V?)MOVAPSrm", - "(V?)MOVDQArm", - "(V?)MOVDQUrm", - "(V?)MOVNTDQArm", "(V?)MOVSHDUPrm", "(V?)MOVSLDUPrm", - "(V?)MOVUPDrm", - "(V?)MOVUPSrm", "VPBROADCASTDrm", "VPBROADCASTQrm")>; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index a5cb5cb..10f7dc2 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -804,14 +804,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr", - "MOVAPSrr", - "MOVDQArr", - "MOVDQUrr", - "MOVPQI2QIrr", - "MOVUPDrr", - "MOVUPSrr", - "PADDBrr", +def: InstRW<[SKXWriteResGroup9], (instregex "PADDBrr", "PADDDrr", "PADDQrr", "PADDWrr", @@ -825,51 +818,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr", "VBLENDMPSZ128rr", "VBLENDMPSZ256rr", "VBLENDMPSZrr", - "VMOVAPDYrr", - "VMOVAPDZ128rr", - "VMOVAPDZ256rr", - "VMOVAPDZrr", - "VMOVAPDrr", - "VMOVAPSYrr", - "VMOVAPSZ128rr", - "VMOVAPSZ256rr", - "VMOVAPSZrr", - "VMOVAPSrr", - "VMOVDQA32Z128rr", - "VMOVDQA32Z256rr", - "VMOVDQA32Zrr", - "VMOVDQA64Z128rr", - "VMOVDQA64Z256rr", - "VMOVDQA64Zrr", - "VMOVDQAYrr", - "VMOVDQArr", - "VMOVDQU16Z128rr", - "VMOVDQU16Z256rr", - "VMOVDQU16Zrr", - "VMOVDQU32Z128rr", - "VMOVDQU32Z256rr", - "VMOVDQU32Zrr", - "VMOVDQU64Z128rr", - "VMOVDQU64Z256rr", - "VMOVDQU64Zrr", - "VMOVDQU8Z128rr", - "VMOVDQU8Z256rr", - "VMOVDQU8Zrr", - "VMOVDQUYrr", - "VMOVDQUrr", - "VMOVPQI(2Q|Lo2PQ)IZrr", - "VMOVPQI2QIrr", - "VMOVUPDYrr", - "VMOVUPDZ128rr", - "VMOVUPDZ256rr", - "VMOVUPDZrr", - "VMOVUPDrr", - "VMOVUPSZ128rr", - "VMOVUPSZ256rr", - "VMOVUPSZrr", - "VMOVUPSYrr", - "VMOVUPSrr", - "VMOVZPQILo2PQIrr", "VPADDBYrr", "VPADDBZ128rr", "VPADDBZ256rr", @@ -2077,27 +2025,12 @@ def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup58], (instregex "MOV64toPQIrm", - "MOVDDUPrm", - "MOVDI2PDIrm", - "MOVQI2PQIrm", - "MOVSDrm", - "MOVSSrm", - "MOVSX(16|32|64)rm16", +def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", "MOVSX(16|32|64)rm32", "MOVSX(16|32|64)rm8", "MOVZX(16|32|64)rm16", "MOVZX(16|32|64)rm8", - "PREFETCHNTA", - "PREFETCHT0", - "PREFETCHT1", - "PREFETCHT2", - "VMOV64toPQIrm", - "VMOVDDUPrm", - "VMOVDI2PDIrm", - "VMOVQI2PQIrm", - "VMOVSDrm", - "VMOVSSrm")>; + "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71? def SKXWriteResGroup59 : SchedWriteRes<[SKXPort015]> { let Latency = 5; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index fb0a7f7..20f10ef 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -896,9 +896,6 @@ def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr")>; def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ64rr")>; // (V)MOVDQA/U. -// x <- x. -def : InstRW<[ZnWriteFPU], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr")>; - // y <- y. def : InstRW<[ZnWriteFPUY], (instregex "VMOVDQ(A|U)Yrr")>; -- 2.7.4