From 35964e9387532a00f63f11d2ee666ce5112e4417 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 4 Dec 2020 17:40:55 +0100 Subject: [PATCH] ac/surface: initialize the FMASK slice size for GFX9+ MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Marek Olšák Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/common/ac_surface.c | 3 ++- src/amd/common/ac_surface.h | 2 +- src/amd/vulkan/radv_meta_clear.c | 3 +-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 0f183ae93a2..855bf043698 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1404,6 +1404,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i surf->fmask_size = fout.fmaskBytes; surf->fmask_alignment = fout.baseAlign; + surf->fmask_slice_size = fout.sliceSize; surf->fmask_tile_swizzle = 0; surf->u.legacy.fmask.slice_tile_max = (fout.pitch * fout.height) / 64; @@ -1413,7 +1414,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i surf->u.legacy.fmask.tiling_index = fout.tileIndex; surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; - surf->u.legacy.fmask.slice_size = fout.sliceSize; /* Compute tile swizzle for FMASK. */ if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) { @@ -1973,6 +1973,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->u.gfx9.fmask.epitch = fout.pitch - 1; surf->fmask_size = fout.fmaskBytes; surf->fmask_alignment = fout.baseAlign; + surf->fmask_slice_size = fout.sliceSize; /* Compute tile swizzle for the FMASK surface. */ if (config->info.fmask_surf_index && fin.swizzleMode >= ADDR_SW_64KB_Z_T && diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index ebec13d53ba..00912d25a0f 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -99,7 +99,6 @@ struct legacy_surf_fmask { uint8_t tiling_index; /* max 31 */ uint8_t bankh; /* max 8 */ uint16_t pitch_in_pixels; - uint64_t slice_size; }; struct legacy_surf_layout { @@ -240,6 +239,7 @@ struct radeon_surf { uint64_t fmask_size; uint32_t surf_alignment; uint32_t fmask_alignment; + uint64_t fmask_slice_size; /* DCC and HTILE are very small. */ uint32_t dcc_size; diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 0b4b398190d..e839de5a381 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1449,8 +1449,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, size = image->planes[0].surface.fmask_size; } else { unsigned fmask_slice_size = - image->planes[0].surface.u.legacy.fmask.slice_size; - + image->planes[0].surface.fmask_slice_size; offset += fmask_slice_size * range->baseArrayLayer; size = fmask_slice_size * radv_get_layerCount(image, range); -- 2.34.1