From 355cc3fd8c63f4bddfd328f62c2d9413f492a7fd Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Tue, 24 Jan 2023 10:39:58 +0000 Subject: [PATCH] [NFC] Deprecate SelectionDag functions taking Alignment as unsigned --- llvm/include/llvm/CodeGen/SelectionDAG.h | 4 ++++ llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 ++++---- llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp | 12 ++++++------ llvm/lib/Target/VE/VEISelLowering.cpp | 8 ++++---- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 6 files changed, 21 insertions(+), 17 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index c620cd8..aa1936c 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1346,6 +1346,8 @@ public: Ranges); } /// FIXME: Remove once transition to Align is over. + LLVM_DEPRECATED("Use the getLoad function that takes a MaybeAlign instead", + "") inline SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -1380,6 +1382,7 @@ public: MMOFlags, AAInfo); } /// FIXME: Remove once transition to Align is over. + LLVM_DEPRECATED("Use the version that takes a MaybeAlign instead", "") inline SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment, @@ -1406,6 +1409,7 @@ public: AAInfo); } /// FIXME: Remove once transition to Align is over. + LLVM_DEPRECATED("Use the version that takes a MaybeAlign instead", "") inline SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment, diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 78ffb27..fad3932 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1511,7 +1511,7 @@ SDValue R600TargetLowering::LowerFormalArguments( // size of the register which isn't useful. unsigned PartOffset = VA.getLocMemOffset(); - unsigned Alignment = MinAlign(VT.getStoreSize(), PartOffset); + Align Alignment = commonAlignment(Align(VT.getStoreSize()), PartOffset); MachinePointerInfo PtrInfo(AMDGPUAS::PARAM_I_ADDRESS); SDValue Arg = DAG.getLoad( diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 47408e0..2e78b52 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -16590,7 +16590,7 @@ static SDValue PerformSplittingToNarrowingStores(StoreSDNode *St, SDValue Store = DAG.getTruncStore( Ch, DL, Extract, NewPtr, St->getPointerInfo().getWithOffset(NewOffset), - NewToVT, Alignment.value(), MMOFlags, AAInfo); + NewToVT, Alignment, MMOFlags, AAInfo); Stores.push_back(Store); } return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); @@ -16631,7 +16631,7 @@ static SDValue PerformSplittingMVETruncToNarrowingStores(StoreSDNode *St, SDValue Extract = Trunc.getOperand(i); SDValue Store = DAG.getTruncStore( Ch, DL, Extract, NewPtr, St->getPointerInfo().getWithOffset(NewOffset), - NewToVT, Alignment.value(), MMOFlags, AAInfo); + NewToVT, Alignment, MMOFlags, AAInfo); Stores.push_back(Store); } return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); @@ -16667,8 +16667,8 @@ static SDValue PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) { AAMDNodes AAInfo = St->getAAInfo(); EVT NewToVT = EVT::getIntegerVT(C, VT.getSizeInBits()); SDValue Store = DAG.getTruncStore(Ch, DL, SDValue(GetLane, 0), BasePtr, - St->getPointerInfo(), NewToVT, - Alignment.value(), MMOFlags, AAInfo); + St->getPointerInfo(), NewToVT, Alignment, + MMOFlags, AAInfo); return Store; } diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp index c994c80..20bab89 100644 --- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp @@ -76,13 +76,13 @@ SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemcpy( // MVI, MVHHI, MVHI and MVGHI respectively. static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, uint64_t ByteVal, uint64_t Size, - unsigned Align, MachinePointerInfo DstPtrInfo) { + Align Alignment, MachinePointerInfo DstPtrInfo) { uint64_t StoreVal = ByteVal; for (unsigned I = 1; I < Size; ++I) StoreVal |= ByteVal << (I * 8); return DAG.getStore( Chain, DL, DAG.getConstant(StoreVal, DL, MVT::getIntegerVT(Size * 8)), - Dst, DstPtrInfo, Align); + Dst, DstPtrInfo, Alignment); } SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemset( @@ -111,15 +111,15 @@ SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemset( unsigned Size1 = Bytes == 16 ? 8 : 1 << findLastSet(Bytes); unsigned Size2 = Bytes - Size1; SDValue Chain1 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size1, - Alignment.value(), DstPtrInfo); + Alignment, DstPtrInfo); if (Size2 == 0) return Chain1; Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, DAG.getConstant(Size1, DL, PtrVT)); DstPtrInfo = DstPtrInfo.getWithOffset(Size1); - SDValue Chain2 = memsetStore( - DAG, DL, Chain, Dst, ByteVal, Size2, - std::min((unsigned)Alignment.value(), Size1), DstPtrInfo); + SDValue Chain2 = + memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2, + std::min(Alignment, Align(Size1)), DstPtrInfo); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); } } else { diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index c921f8d..f373b36 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -1464,9 +1464,9 @@ static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG) { SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64, StNode->getValue(), SubRegOdd); - unsigned Alignment = StNode->getAlign().value(); + Align Alignment = StNode->getAlign(); if (Alignment > 8) - Alignment = 8; + Alignment = Align(8); // VE stores Hi64 to 8(addr) and Lo64 to 0(addr) SDValue OutChains[2]; @@ -1498,9 +1498,9 @@ static SDValue lowerStoreI1(SDValue Op, SelectionDAG &DAG) { assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type"); SDValue BasePtr = StNode->getBasePtr(); - unsigned Alignment = StNode->getAlign().value(); + Align Alignment = StNode->getAlign(); if (Alignment > 8) - Alignment = 8; + Alignment = Align(8); EVT AddrVT = BasePtr.getValueType(); EVT MemVT = StNode->getMemoryVT(); if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) { diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2ea9e68..02ca480 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29186,7 +29186,7 @@ SDValue X86TargetLowering::LowerSET_ROUNDING(SDValue Op, // Update rounding mode bits and store the new FP Control Word into stack. CWD = DAG.getNode(ISD::OR, DL, MVT::i16, CWD, RMBits); - Chain = DAG.getStore(Chain, DL, CWD, StackSlot, MPI, /* Alignment = */ 2); + Chain = DAG.getStore(Chain, DL, CWD, StackSlot, MPI, Align(2)); // Load FP control word from the slot. SDValue OpsLD[] = {Chain, StackSlot}; @@ -29217,7 +29217,7 @@ SDValue X86TargetLowering::LowerSET_ROUNDING(SDValue Op, // Update rounding mode bits and store the new FP Control Word into stack. CWD = DAG.getNode(ISD::OR, DL, MVT::i32, CWD, RMBits); - Chain = DAG.getStore(Chain, DL, CWD, StackSlot, MPI, /* Alignment = */ 4); + Chain = DAG.getStore(Chain, DL, CWD, StackSlot, MPI, Align(4)); // Load MXCSR from the slot. Chain = DAG.getNode( -- 2.7.4