From 351e4fa0e2c98bd24dfd8b547f366e00a4d554b2 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 25 Mar 2018 19:07:17 +0000 Subject: [PATCH] [ARM] Remove sched model instregex entries that don't match any instructions (D44687) Reviewed by @javed.absar llvm-svn: 328457 --- llvm/lib/Target/ARM/ARMScheduleA9.td | 7 +++--- llvm/lib/Target/ARM/ARMScheduleR52.td | 39 ++++++++++++++++----------------- llvm/lib/Target/ARM/ARMScheduleSwift.td | 34 ++++++++++++++-------------- 3 files changed, 39 insertions(+), 41 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index 21ac4f7..491522f 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -2537,8 +2537,7 @@ def : SchedAlias; def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi", "MOVCCsr")>; def : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>; -def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm", - "MOV_ga_dyn")>; +def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm")>; def : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>; def : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>; @@ -2551,12 +2550,12 @@ def : InstRW< [A9WriteM], "SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>; def : InstRW< [A9WriteM, A9WriteMHi], (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL", - "UMAAL", "SMLALv5", "UMLALv5", "UMAALv5", "SMLALBB", "SMLALBT", "SMLALTB", + "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB", "SMLALTT")>; // FIXME: These instructions used to have NoItinerary. Just copied the one from above. def : InstRW< [A9WriteM, A9WriteMHi], (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX", - "SMLSLD", "SMLLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>; + "SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>; def : InstRW<[A9WriteM16, A9WriteM16Hi], (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>; diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td index 0fdccd5d..11bce45 100644 --- a/llvm/lib/Target/ARM/ARMScheduleR52.td +++ b/llvm/lib/Target/ARM/ARMScheduleR52.td @@ -217,12 +217,11 @@ def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>; def : InstRW<[R52WriteALU_EX1, R52Read_ISS], - (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi", - "t2MOVi", "t2MOV_ga_dyn")>; + (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi", "t2MOVi")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1], - (instregex "MOV_ga_pcrel$", "t2MOV_ga_pcrel$")>; + (instregex "MOV_ga_pcrel$")>; def : InstRW<[R52WriteLd,R52Read_ISS], - (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; + (instregex "MOV_ga_pcrel_ldr")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>; @@ -257,12 +256,12 @@ def : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], // Sum of Absolute Difference def : InstRW< [R52WriteALU_WRI, R52Read_ISS, R52Read_ISS, R52Read_ISS], - (instregex "USAD8", "t2USAD8", "tUSAD8","USADA8", "t2USADA8", "tUSADA8") >; + (instregex "USAD8", "t2USAD8", "USADA8", "t2USADA8") >; // Integer Multiply def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS], - (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", - "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL", + (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", + "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", "t2SMULWB", "t2SMULWT", "t2SMUSD")>; @@ -270,17 +269,17 @@ def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS], // Even for 64-bit accumulation (or Long), the single MAC is used (not ALUs). // The store pipeline is used partly for 64-bit operations. def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS, R52Read_ISS], - (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", - "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR", + (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", + "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR", "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX", "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT", "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX", "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$", - "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT", + "SMLAL", "UMLAL", "SMLALBT", "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", - "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", + "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>; @@ -301,31 +300,31 @@ def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_ISS], "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T", "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", - "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T", + "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?", "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "MOVS?sr", "t2MOVS?sr")>; def : InstRW<[R52WriteALU_WRI, R52Read_EX2], (instregex "MOVT", "t2MOVT")>; -def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri","ANDS?ri", +def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri", "ANDS?ri", "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri", "t2AD(C|D)S?ri", "t2ANDS?ri", "t2BICS?ri","t2CLZ", "t2EORri", "t2MVN", "t2ORRri", "t2RSBS?ri", "t2SBCri")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "AD(C|D)S?rr", - "ANDS?rr", "BICS?rr", "CRC*", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr", + "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr", "t2AD(C|D)S?rr", "t2ANDS?rr", "t2BICS?rr", "t2CRC", "t2EORrr", "t2SBCrr")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], (instregex "AD(C|D)S?rsi", "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi", - "t2AD(|D)S?rsi", "t2ANDS?rsi", "t2BICS?rsi", "t2EORrsi", "t2ORRrsi", "t2RSBrsi", "t2SBCrsi")>; + "t2AD(C|D)S?rs", "t2ANDS?rs", "t2BICS?rs", "t2EORrs", "t2ORRrs", "t2RSBrs", "t2SBCrs")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS, R52Read_ISS], (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr", - "ORRrsrr", "RSBrsr", "RSCrsr", "SBCrsr")>; + "ORRrsr", "RSBrsr", "RSCrsr", "SBCrsr")>; def : InstRW<[R52WriteALU_EX1], - (instregex "ADR", "MOVSi", "MOVSsi", "MOVST?i16*", "MVNS?s?i", "t2MOVS?si")>; + (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>; def : InstRW<[R52WriteALU_EX1, R52Read_ISS], (instregex "ASRi", "RORS?i")>; def : InstRW<[R52WriteALU_EX1, R52Read_ISS, R52Read_ISS], @@ -484,7 +483,7 @@ def : InstRW<[R52WriteILDM, R52Read_ISS], def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], - (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>; + (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; // Integer Store, Single Element def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], @@ -500,7 +499,7 @@ def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], // Integer Store, Dual def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], - (instregex "STRD$", "t2STRDi8", "STL", "t2STRD$", "t2STL")>; + (instregex "STRD$", "t2STRDi8", "STL", "t2STL")>; def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>; @@ -508,7 +507,7 @@ def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2], (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2], (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", - "PUSH", "tPUSH")>; + "tPUSH")>; // LDRLIT pseudo instructions, they expand to LDR + PICADD def : InstRW<[R52WriteLd], diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td index 0264680..8798464 100644 --- a/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -164,12 +164,12 @@ let SchedModel = SwiftModel in { "t2UXTB16")>; // Pseudo instructions. def : InstRW<[SwiftWriteP01OneCycle2x], - (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi32imm", - "t2MOVi32imm", "t2MOV_ga_dyn")>; + (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm", + "t2MOVi32imm")>; def : InstRW<[SwiftWriteP01OneCycle3x], (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>; def : InstRW<[SwiftWriteP01OneCycle2x_load], - (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; + (instregex "MOV_ga_pcrel_ldr")>; def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>; @@ -221,8 +221,8 @@ let SchedModel = SwiftModel in { // 4.2.12 Integer Multiply (32-bit result) // Two sources. def : InstRW< [SwiftWriteP0FourCycle], - (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", - "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL", + (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", + "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", "t2SMULWB", "t2SMULWT", "t2SMUSD")>; @@ -244,8 +244,8 @@ let SchedModel = SwiftModel in { // Multiply accumulate, three sources def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, SwiftReadAdvanceFourCyclesPred], - (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", - "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", + (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", + "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR")>; // 4.2.13 Integer Multiply (32-bit result, Q flag) @@ -305,9 +305,9 @@ let SchedModel = SwiftModel in { // We are being a bit inaccurate here. def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU, SchedReadAdvance<4>, SchedReadAdvance<3>], - (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT", + (instregex "SMLAL", "UMLAL", "SMLALBT", "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", - "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT", + "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>; @@ -369,7 +369,7 @@ let SchedModel = SwiftModel in { "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>; def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne], (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", - "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>; + "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?")>; // 4.2.21 Integer Dual Load // Not accurate. @@ -486,7 +486,7 @@ let SchedModel = SwiftModel in { (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/ "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle], - (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>; + (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; // 4.2.23 Integer Store, Single Element def : InstRW<[SwiftWriteP2], (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", @@ -536,7 +536,7 @@ let SchedModel = SwiftModel in { (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM], (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", - "PUSH", "tPUSH")>; + "tPUSH")>; // LDRLIT pseudo instructions, they expand to LDR + PICADD def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU], @@ -552,14 +552,14 @@ let SchedModel = SwiftModel in { // 4.2.27 Not issued def : WriteRes { let Latency = 0; let NumMicroOps = 0; } - def : InstRW<[WriteNoop], (instregex "t2IT", "IT", "NOP")>; + def : InstRW<[WriteNoop], (instregex "t2IT", "IT")>; // 4.2.28 Advanced SIMD, Integer, 2 cycle def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL", "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi", "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST", - "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF", + "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>; def : InstRW<[SwiftWriteP1TwoCycle], @@ -569,7 +569,7 @@ let SchedModel = SwiftModel in { // 4.2.30 Advanced SIMD, Integer with Accumulate def : InstRW<[SwiftWriteP0FourCycle], (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT", - "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL", + "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL", "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD", "VQSUB")>; def : InstRW<[SwiftWriteP1FourCycle], @@ -626,12 +626,12 @@ let SchedModel = SwiftModel in { // 4.2.37 Advanced SIMD and VFP, Move def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc", - "VMVNv", "VMVN(d|q)", "VMVN(S|D)cc", + "VMVNv", "VMVN(d|q)", "FCONST(D|S)")>; def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>; def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>], (instregex "VQMOVN")>; - def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>; + def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN")>; def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>], (instregex "VDUP(8|16|32)")>; def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>; -- 2.7.4