From 34e29b2ebd2c296bad0bf6df986b3d75105c55ec Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 20 Feb 2017 16:10:30 +0000 Subject: [PATCH] intel/isl: add MCS width constraint 16 samples v3 (Jason Ekstrand): Add a comment explaining why Signed-off-by: Lionel Landwerlin Reviewed-by: Jason Ekstrand Reviewed-by: Chad Versace --- src/intel/isl/isl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 1a47da5..d1fb7e4 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1417,6 +1417,16 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, assert(surf->levels == 1); assert(surf->logical_level0_px.depth == 1); + /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9 + * bits which means the maximum pitch of a compression surface is 512 + * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is + * 64bpp, this gives us a maximum width of 8192 pixels. We can create + * larger multisampled surfaces, we just can't compress them. For 2x, 4x, + * and 8x, we have enough room for the full 16k supported by the hardware. + */ + if (surf->samples == 16 && surf->logical_level0_px.width > 8192) + return false; + enum isl_format mcs_format; switch (surf->samples) { case 2: mcs_format = ISL_FORMAT_MCS_2X; break; -- 2.7.4