From 34b512f5aa148cc6a36e8da921456895b2d20f66 Mon Sep 17 00:00:00 2001 From: Sofiane Naci Date: Thu, 1 Aug 2013 09:48:48 +0000 Subject: [PATCH] aarch64.md (define_attr "type"): Delete. * config/aarch64/aarch64.md (define_attr "type"): Delete. Include "../arm/types.md". Define "type" attribute for all patterns. * config/aarch64/aarch64-simd.md (move_lo_quad_): Update for attribute changes. From-SVN: r201399 --- gcc/ChangeLog | 7 + gcc/config/aarch64/aarch64-simd.md | 1 + gcc/config/aarch64/aarch64.md | 315 +++++++++++++++++++++++++++++-------- 3 files changed, 258 insertions(+), 65 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f2d25f0..1ba4e06 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-08-01 Sofiane Naci + + * config/aarch64/aarch64.md (define_attr "type"): Delete. + Include "../arm/types.md". Define "type" attribute for all patterns. + * config/aarch64/aarch64-simd.md (move_lo_quad_): Update for + attribute changes. + 2013-07-31 Michael Meissner * config/rs6000/predicates.md (fusion_gpr_addis): New predicates diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 178efdc..3c76032 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1051,6 +1051,7 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "v8type" "*,fmov,*") + (set_attr "type" "*,mov_reg,*") (set_attr "simd_type" "simd_dup,*,simd_dup") (set_attr "simd_mode" "") (set_attr "simd" "yes,*,yes") diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5d64228..7266d38 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -272,48 +272,9 @@ udiv" (const_string "alu")) - -; The "type" attribute is used by the AArch32 backend. Below is a mapping -; from "v8type" to "type". - -(define_attr "type" - "alu,alu_shift,block,branch,call,f_2_r,f_cvt,f_flag,f_loads, - f_loadd,f_stored,f_stores,faddd,fadds,fcmpd,fcmps,fconstd,fconsts, - fcpys,fdivd,fdivs,ffarithd,ffariths,fmacd,fmacs,fmuld,fmuls,load_byte, - load1,load2,mult,r_2_f,store1,store2" - (cond [ - (eq_attr "v8type" "alu_shift,alus_shift,logic_shift,logics_shift") (const_string "alu_shift") - (eq_attr "v8type" "branch") (const_string "branch") - (eq_attr "v8type" "call") (const_string "call") - (eq_attr "v8type" "fmovf2i") (const_string "f_2_r") - (eq_attr "v8type" "fcvt,fcvtf2i,fcvti2f") (const_string "f_cvt") - (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "SF")) (const_string "f_loads") - (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "DF")) (const_string "f_loadd") - (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "SF")) (const_string "f_stores") - (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "DF")) (const_string "f_stored") - (and (eq_attr "v8type" "fadd,fminmax") (eq_attr "mode" "DF")) (const_string "faddd") - (and (eq_attr "v8type" "fadd,fminmax") (eq_attr "mode" "SF")) (const_string "fadds") - (and (eq_attr "v8type" "fcmp,fccmp") (eq_attr "mode" "DF")) (const_string "fcmpd") - (and (eq_attr "v8type" "fcmp,fccmp") (eq_attr "mode" "SF")) (const_string "fcmps") - (and (eq_attr "v8type" "fconst") (eq_attr "mode" "DF")) (const_string "fconstd") - (and (eq_attr "v8type" "fconst") (eq_attr "mode" "SF")) (const_string "fconsts") - (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF")) (const_string "fdivd") - (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF")) (const_string "fdivs") - (and (eq_attr "v8type" "ffarith") (eq_attr "mode" "DF")) (const_string "ffarithd") - (and (eq_attr "v8type" "ffarith") (eq_attr "mode" "SF")) (const_string "ffariths") - (and (eq_attr "v8type" "fmadd") (eq_attr "mode" "DF")) (const_string "fmacd") - (and (eq_attr "v8type" "fmadd") (eq_attr "mode" "SF")) (const_string "fmacs") - (and (eq_attr "v8type" "fmul") (eq_attr "mode" "DF")) (const_string "fmuld") - (and (eq_attr "v8type" "fmul") (eq_attr "mode" "SF")) (const_string "fmuls") - (and (eq_attr "v8type" "load1") (eq_attr "mode" "QI,HI")) (const_string "load_byte") - (and (eq_attr "v8type" "load1") (eq_attr "mode" "SI,DI,TI")) (const_string "load1") - (eq_attr "v8type" "load2") (const_string "load2") - (and (eq_attr "v8type" "mulh,mult,mull,madd,sdiv,udiv") (eq_attr "mode" "SI")) (const_string "mult") - (eq_attr "v8type" "fmovi2f") (const_string "r_2_f") - (eq_attr "v8type" "store1") (const_string "store1") - (eq_attr "v8type" "store2") (const_string "store2") - ] - (const_string "alu"))) +; The "type" attribute is is included here from AArch32 backend to be able +; to share pipeline descriptions. +(include "../arm/types.md") ;; Attribute that specifies whether or not the instruction touches fp ;; registers. @@ -358,14 +319,16 @@ [(set (pc) (match_operand:DI 0 "register_operand" "r"))] "" "br\\t%0" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] ) (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "b\\t%l0" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] ) (define_expand "cbranch4" @@ -403,7 +366,8 @@ (pc)))] "" "b%m0\\t%l2" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] ) (define_expand "casesi" @@ -467,7 +431,8 @@ return aarch64_output_casesi (operands); " [(set_attr "length" "16") - (set_attr "v8type" "branch")] + (set_attr "v8type" "branch") + (set_attr "type" "branch")] ) (define_insn "nop" @@ -508,7 +473,8 @@ [(return)] "" "ret" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] ) (define_insn "eh_return" @@ -516,7 +482,9 @@ UNSPECV_EH_RETURN)] "" "#" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] + ) (define_split @@ -536,7 +504,9 @@ (pc)))] "" "\\t%0, %l1" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] + ) (define_insn "*tb1" @@ -555,6 +525,7 @@ return \"\\t%0, %1, %l2\"; " [(set_attr "v8type" "branch") + (set_attr "type" "branch") (set_attr "mode" "") (set (attr "length") (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768)) @@ -576,6 +547,7 @@ return \"\\t%0, , %l1\"; " [(set_attr "v8type" "branch") + (set_attr "type" "branch") (set_attr "mode" "") (set (attr "length") (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768)) @@ -620,7 +592,8 @@ (clobber (reg:DI LR_REGNUM))] "" "blr\\t%0" - [(set_attr "v8type" "call")] + [(set_attr "v8type" "call") + (set_attr "type" "call")] ) (define_insn "*call_symbol" @@ -631,7 +604,8 @@ "GET_CODE (operands[0]) == SYMBOL_REF && !aarch64_is_long_call_p (operands[0])" "bl\\t%a0" - [(set_attr "v8type" "call")] + [(set_attr "v8type" "call") + (set_attr "type" "call")] ) (define_expand "call_value" @@ -668,7 +642,9 @@ (clobber (reg:DI LR_REGNUM))] "" "blr\\t%1" - [(set_attr "v8type" "call")] + [(set_attr "v8type" "call") + (set_attr "type" "call")] + ) (define_insn "*call_value_symbol" @@ -680,7 +656,8 @@ "GET_CODE (operands[1]) == SYMBOL_REF && !aarch64_is_long_call_p (operands[1])" "bl\\t%a1" - [(set_attr "v8type" "call")] + [(set_attr "v8type" "call") + (set_attr "type" "call")] ) (define_expand "sibcall" @@ -715,7 +692,9 @@ (use (match_operand 2 "" ""))] "GET_CODE (operands[0]) == SYMBOL_REF" "b\\t%a0" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] + ) (define_insn "*sibcall_value_insn" @@ -726,7 +705,8 @@ (use (match_operand 3 "" ""))] "GET_CODE (operands[1]) == SYMBOL_REF" "b\\t%a1" - [(set_attr "v8type" "branch")] + [(set_attr "v8type" "branch") + (set_attr "type" "branch")] ) ;; Call subroutine returning any type. @@ -804,6 +784,7 @@ } } [(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*") + (set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,*,*,*") (set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup") (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes") (set_attr "mode" "") @@ -846,6 +827,8 @@ fmov\\t%w0, %s1 fmov\\t%s0, %s1" [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov") + (set_attr "type" "mov_reg,mov_reg,mov_reg,arlo_reg,load1,load1,store1,store1,\ + mov_reg,mov_reg,mov_reg,mov_reg,mov_reg") (set_attr "mode" "SI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")] ) @@ -871,6 +854,8 @@ fmov\\t%d0, %d1 movi\\t%d0, %1" [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ + mov_reg,mov_reg,mov_reg,mov_reg,mov_reg,mov_reg") (set_attr "mode" "DI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] @@ -885,6 +870,7 @@ && UINTVAL (operands[1]) % 16 == 0" "movk\\t%0, %X2, lsl %1" [(set_attr "v8type" "movk") + (set_attr "type" "mov_imm") (set_attr "mode" "")] ) @@ -917,6 +903,8 @@ str\\t%q1, %0" [(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \ load2,store2,store2,fpsimd_load,fpsimd_store") + (set_attr "type" "mov_reg,r_2_f,f_2_r,*, \ + load2,store2,store2,f_loadd,f_stored") (set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*") (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") (set_attr "length" "8,8,8,4,4,4,4,4,4") @@ -970,6 +958,8 @@ [(set_attr "v8type" "fmovi2f,fmovf2i,\ fmov,fconst,fpsimd_load,\ fpsimd_store,fpsimd_load,fpsimd_store,fmov") + (set_attr "type" "r_2_f,f_2_r,mov_reg,fconsts,\ + f_loads,f_stores,f_loads,f_stores,mov_reg") (set_attr "mode" "SF")] ) @@ -991,6 +981,8 @@ [(set_attr "v8type" "fmovi2f,fmovf2i,\ fmov,fconst,fpsimd_load,\ fpsimd_store,fpsimd_load,fpsimd_store,move") + (set_attr "type" "r_2_f,f_2_r,mov_reg,fconstd,\ + f_loadd,f_stored,f_loadd,f_stored,mov_reg") (set_attr "mode" "DF")] ) @@ -1029,6 +1021,8 @@ ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0" [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2") + (set_attr "type" "arlo_reg,mov_reg,r_2_f,f_2_r,fconstd,fconstd,\ + f_loadd,f_stored,f_loadd,f_stored") (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*") @@ -1059,6 +1053,7 @@ GET_MODE_SIZE (mode)))" "ldp\\t%0, %2, %1" [(set_attr "v8type" "load2") + (set_attr "type" "load2") (set_attr "mode" "")] ) @@ -1075,6 +1070,7 @@ GET_MODE_SIZE (mode)))" "stp\\t%1, %3, %0" [(set_attr "v8type" "store2") + (set_attr "type" "store2") (set_attr "mode" "")] ) @@ -1091,6 +1087,7 @@ GET_MODE_SIZE (mode)))" "ldp\\t%0, %2, %1" [(set_attr "v8type" "fpsimd_load2") + (set_attr "type" "f_load") (set_attr "mode" "")] ) @@ -1107,6 +1104,7 @@ GET_MODE_SIZE (mode)))" "stp\\t%1, %3, %0" [(set_attr "v8type" "fpsimd_load2") + (set_attr "type" "f_load") (set_attr "mode" "")] ) @@ -1126,6 +1124,7 @@ "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" "ldp\\t%2, %3, [%1], %4" [(set_attr "v8type" "load2") + (set_attr "type" "load2") (set_attr "mode" "")] ) @@ -1145,6 +1144,7 @@ "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" "stp\\t%2, %3, [%0, %4]!" [(set_attr "v8type" "store2") + (set_attr "type" "store2") (set_attr "mode" "")] ) @@ -1166,6 +1166,7 @@ sxtw\t%0, %w1 ldrsw\t%0, %1" [(set_attr "v8type" "extend,load1") + (set_attr "type" "extend,load1") (set_attr "mode" "DI")] ) @@ -1177,6 +1178,7 @@ uxtw\t%0, %w1 ldr\t%w0, %1" [(set_attr "v8type" "extend,load1") + (set_attr "type" "extend,load1") (set_attr "mode" "DI")] ) @@ -1194,6 +1196,7 @@ sxt\t%0, %w1 ldrs\t%0, %1" [(set_attr "v8type" "extend,load1") + (set_attr "type" "extend,load1") (set_attr "mode" "")] ) @@ -1206,6 +1209,7 @@ ldr\t%w0, %1 ldr\t%0, %1" [(set_attr "v8type" "extend,load1,load1") + (set_attr "type" "extend,load1,load1") (set_attr "mode" "")] ) @@ -1223,6 +1227,7 @@ xtb\t%w0, %w1 b\t%w0, %1" [(set_attr "v8type" "extend,load1") + (set_attr "type" "extend,load1") (set_attr "mode" "HI")] ) @@ -1267,6 +1272,7 @@ add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_imm,arlo_reg,arlo_imm") (set_attr "mode" "SI")] ) @@ -1283,6 +1289,7 @@ add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_imm,arlo_reg,arlo_imm") (set_attr "mode" "SI")] ) @@ -1299,6 +1306,7 @@ sub\\t%x0, %x1, #%n2 add\\t%d0, %d1, %d2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_imm,arlo_reg,arlo_imm,arlo_reg") (set_attr "mode" "DI") (set_attr "simd" "*,*,*,yes")] ) @@ -1306,16 +1314,18 @@ (define_insn "*add3_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ - (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r") - (match_operand:GPI 2 "aarch64_plus_operand" "rI,J")) + (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r,r") + (match_operand:GPI 2 "aarch64_plus_operand" "r,I,J")) (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r,r") + (set (match_operand:GPI 0 "register_operand" "=r,r,r") (plus:GPI (match_dup 1) (match_dup 2)))] "" "@ adds\\t%0, %1, %2 + adds\\t%0, %1, %2 subs\\t%0, %1, #%n2" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg,arlo_imm,arlo_imm") (set_attr "mode" "")] ) @@ -1323,16 +1333,18 @@ (define_insn "*addsi3_compare0_uxtw" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ - (plus:SI (match_operand:SI 1 "register_operand" "%r,r") - (match_operand:SI 2 "aarch64_plus_operand" "rI,J")) + (plus:SI (match_operand:SI 1 "register_operand" "%r,r,r") + (match_operand:SI 2 "aarch64_plus_operand" "r,I,J")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=r,r") + (set (match_operand:DI 0 "register_operand" "=r,r,r") (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] "" "@ adds\\t%w0, %w1, %w2 + adds\\t%w0, %w1, %w2 subs\\t%w0, %w1, #%n2" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg,arlo_imm,arlo_imm") (set_attr "mode" "SI")] ) @@ -1350,6 +1362,7 @@ "" "adds\\t%0, %3, %1, lsl %p2" [(set_attr "v8type" "alus_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1367,6 +1380,7 @@ "" "subs\\t%0, %1, %2, lsl %p3" [(set_attr "v8type" "alus_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1382,6 +1396,7 @@ "" "adds\\t%0, %2, %1, xt" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1397,6 +1412,7 @@ "" "subs\\t%0, %1, %2, xt" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1418,6 +1434,7 @@ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" "adds\\t%0, %4, %1, xt%e3 %p2" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1439,20 +1456,23 @@ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" "subs\\t%0, %4, %1, xt%e3 %p2" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ - (plus:GPI (match_operand:GPI 0 "register_operand" "%r,r") - (match_operand:GPI 1 "aarch64_plus_operand" "rI,J")) + (plus:GPI (match_operand:GPI 0 "register_operand" "%r,r,r") + (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")) (const_int 0)))] "" "@ cmn\\t%0, %1 + cmn\\t%0, %1 cmp\\t%0, #%n1" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg,arlo_imm,arlo_imm") (set_attr "mode" "")] ) @@ -1464,6 +1484,7 @@ "" "cmn\\t%0, %1" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1475,6 +1496,7 @@ "" "add\\t%0, %3, %1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1488,6 +1510,7 @@ "" "add\\t%w0, %w3, %w1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -1499,6 +1522,7 @@ "" "add\\t%0, %3, %1, lsl %p2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1509,6 +1533,7 @@ "" "add\\t%0, %2, %1, xt" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1521,6 +1546,7 @@ "" "add\\t%w0, %w2, %w1, xt" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1533,6 +1559,7 @@ "" "add\\t%0, %3, %1, xt %2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1547,6 +1574,7 @@ "" "add\\t%w0, %w3, %w1, xt %2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1559,6 +1587,7 @@ "" "add\\t%0, %3, %1, xt %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1572,6 +1601,7 @@ "" "add\\t%w0, %w3, %w1, xt %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1586,6 +1616,7 @@ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" "add\\t%0, %4, %1, xt%e3 %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1602,6 +1633,7 @@ "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "add\\t%w0, %w4, %w1, xt%e3 %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1615,6 +1647,7 @@ "" "adc\\t%0, %1, %2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1630,6 +1663,7 @@ "" "adc\\t%w0, %w1, %w2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1643,6 +1677,7 @@ "" "adc\\t%0, %1, %2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1658,6 +1693,7 @@ "" "adc\\t%w0, %w1, %w2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1671,6 +1707,7 @@ "" "adc\\t%0, %1, %2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1686,6 +1723,7 @@ "" "adc\\t%w0, %w1, %w2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1699,6 +1737,7 @@ "" "adc\\t%0, %1, %2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1714,6 +1753,7 @@ "" "adc\\t%w0, %w1, %w2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1730,6 +1770,7 @@ INTVAL (operands[3]))); return \"add\t%0, %4, %1, uxt%e3 %p2\";" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1748,6 +1789,7 @@ INTVAL (operands[3]))); return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1758,6 +1800,7 @@ "" "sub\\t%w0, %w1, %w2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1770,6 +1813,7 @@ "" "sub\\t%w0, %w1, %w2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1782,6 +1826,7 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "DI") (set_attr "simd" "*,yes")] ) @@ -1797,6 +1842,7 @@ "" "subs\\t%0, %1, %2" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1811,6 +1857,7 @@ "" "subs\\t%w0, %w1, %w2" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1823,6 +1870,7 @@ "" "sub\\t%0, %3, %1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1837,6 +1885,7 @@ "" "sub\\t%w0, %w3, %w1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -1849,6 +1898,7 @@ "" "sub\\t%0, %3, %1, lsl %p2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -1863,6 +1913,7 @@ "" "sub\\t%w0, %w3, %w1, lsl %p2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -1874,6 +1925,7 @@ "" "sub\\t%0, %1, %2, xt" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1887,6 +1939,7 @@ "" "sub\\t%w0, %w1, %w2, xt" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1899,6 +1952,7 @@ "" "sub\\t%0, %1, %2, xt %3" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1913,6 +1967,7 @@ "" "sub\\t%w0, %w1, %w2, xt %3" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1927,6 +1982,7 @@ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" "sub\\t%0, %4, %1, xt%e3 %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1943,6 +1999,7 @@ "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "sub\\t%w0, %w4, %w1, xt%e3 %p2" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1956,6 +2013,7 @@ "" "sbc\\t%0, %1, %2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -1971,6 +2029,7 @@ "" "sbc\\t%w0, %w1, %w2" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -1987,6 +2046,7 @@ INTVAL (operands[3]))); return \"sub\t%0, %4, %1, uxt%e3 %p2\";" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2005,6 +2065,7 @@ INTVAL (operands[3]))); return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" [(set_attr "v8type" "alu_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2037,6 +2098,7 @@ DONE; } [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "DI")] ) @@ -2048,6 +2110,7 @@ neg\\t%0, %1 neg\\t%0, %1" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "simd_type" "*,simd_negabs") (set_attr "simd" "*,yes") (set_attr "mode" "") @@ -2061,6 +2124,7 @@ "" "neg\\t%w0, %w1" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2071,6 +2135,7 @@ "" "ngc\\t%0, %1" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2082,6 +2147,7 @@ "" "ngc\\t%w0, %w1" [(set_attr "v8type" "adc") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2094,6 +2160,7 @@ "" "negs\\t%0, %1" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2107,6 +2174,7 @@ "" "negs\\t%w0, %w1" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2122,6 +2190,7 @@ "" "negs\\t%0, %1, %2" [(set_attr "v8type" "alus_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -2133,6 +2202,7 @@ "" "neg\\t%0, %1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -2146,6 +2216,7 @@ "" "neg\\t%w0, %w1, %2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -2157,6 +2228,7 @@ "" "neg\\t%0, %1, lsl %p2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -2170,6 +2242,7 @@ "" "neg\\t%w0, %w1, lsl %p2" [(set_attr "v8type" "alu_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -2180,6 +2253,7 @@ "" "mul\\t%0, %1, %2" [(set_attr "v8type" "mult") + (set_attr "type" "mul") (set_attr "mode" "")] ) @@ -2192,6 +2266,7 @@ "" "mul\\t%w0, %w1, %w2" [(set_attr "v8type" "mult") + (set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2203,6 +2278,7 @@ "" "madd\\t%0, %1, %2, %3" [(set_attr "v8type" "madd") + (set_attr "type" "mul") (set_attr "mode" "")] ) @@ -2216,6 +2292,7 @@ "" "madd\\t%w0, %w1, %w2, %w3" [(set_attr "v8type" "madd") + (set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2228,6 +2305,7 @@ "" "msub\\t%0, %1, %2, %3" [(set_attr "v8type" "madd") + (set_attr "type" "mul") (set_attr "mode" "")] ) @@ -2242,6 +2320,7 @@ "" "msub\\t%w0, %w1, %w2, %w3" [(set_attr "v8type" "madd") + (set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2253,6 +2332,7 @@ "" "mneg\\t%0, %1, %2" [(set_attr "v8type" "mult") + (set_attr "type" "mul") (set_attr "mode" "")] ) @@ -2266,6 +2346,7 @@ "" "mneg\\t%w0, %w1, %w2" [(set_attr "v8type" "mult") + (set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2276,6 +2357,7 @@ "" "mull\\t%0, %w1, %w2" [(set_attr "v8type" "mull") + (set_attr "type" "mull") (set_attr "mode" "DI")] ) @@ -2288,6 +2370,7 @@ "" "maddl\\t%0, %w1, %w2, %3" [(set_attr "v8type" "maddl") + (set_attr "type" "mul") (set_attr "mode" "DI")] ) @@ -2301,6 +2384,7 @@ "" "msubl\\t%0, %w1, %w2, %3" [(set_attr "v8type" "maddl") + (set_attr "type" "mul") (set_attr "mode" "DI")] ) @@ -2312,6 +2396,7 @@ "" "mnegl\\t%0, %w1, %w2" [(set_attr "v8type" "mull") + (set_attr "type" "mull") (set_attr "mode" "DI")] ) @@ -2326,6 +2411,7 @@ "" "mulh\\t%0, %1, %2" [(set_attr "v8type" "mulh") + (set_attr "type" "mull") (set_attr "mode" "DI")] ) @@ -2336,6 +2422,7 @@ "" "div\\t%0, %1, %2" [(set_attr "v8type" "div") + (set_attr "type" "div") (set_attr "mode" "")] ) @@ -2348,6 +2435,7 @@ "" "div\\t%w0, %w1, %w2" [(set_attr "v8type" "div") + (set_attr "type" "div") (set_attr "mode" "SI")] ) @@ -2357,13 +2445,15 @@ (define_insn "*cmp" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:GPI 0 "register_operand" "r,r") - (match_operand:GPI 1 "aarch64_plus_operand" "rI,J")))] + (compare:CC (match_operand:GPI 0 "register_operand" "r,r,r") + (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))] "" "@ cmp\\t%0, %1 + cmp\\t%0, %1 cmn\\t%0, #%n1" [(set_attr "v8type" "alus") + (set_attr "type" "arlo_reg,arlo_imm,arlo_imm") (set_attr "mode" "")] ) @@ -2376,6 +2466,7 @@ fcmp\\t%0, #0.0 fcmp\\t%0, %1" [(set_attr "v8type" "fcmp") + (set_attr "type" "fcmp") (set_attr "mode" "")] ) @@ -2388,6 +2479,7 @@ fcmpe\\t%0, #0.0 fcmpe\\t%0, %1" [(set_attr "v8type" "fcmp") + (set_attr "type" "fcmp") (set_attr "mode" "")] ) @@ -2400,6 +2492,7 @@ "" "cmp\\t%2, %0, %1" [(set_attr "v8type" "alus_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -2411,6 +2504,7 @@ "" "cmp\\t%1, %0, xt" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2424,6 +2518,7 @@ "" "cmp\\t%2, %0, xt %1" [(set_attr "v8type" "alus_ext") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2464,6 +2559,7 @@ "" "cset\\t%0, %m1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2476,6 +2572,7 @@ "" "cset\\t%w0, %m1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2486,6 +2583,7 @@ "" "csetm\\t%0, %m1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2498,6 +2596,7 @@ "" "csetm\\t%w0, %m1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2552,6 +2651,7 @@ mov\\t%0, -1 mov\\t%0, 1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2576,6 +2676,7 @@ mov\\t%w0, -1 mov\\t%w0, 1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -2589,6 +2690,7 @@ "TARGET_FLOAT" "fcsel\\t%0, %3, %4, %m1" [(set_attr "v8type" "fcsel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2638,6 +2740,7 @@ "" "csinc\\t%0, %1, %1, %M2" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) (define_insn "csinc3_insn" @@ -2651,6 +2754,7 @@ "" "csinc\\t%0, %4, %3, %M1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -2664,6 +2768,7 @@ "" "csinv\\t%0, %4, %3, %M1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) (define_insn "*csneg3_insn" @@ -2676,6 +2781,7 @@ "" "csneg\\t%0, %4, %3, %M1" [(set_attr "v8type" "csel") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) ;; ------------------------------------------------------------------- @@ -2689,6 +2795,7 @@ "" "\\t%0, %1, %2" [(set_attr "v8type" "logic,logic_imm") + (set_attr "type" "arlo_reg,arlo_imm") (set_attr "mode" "")]) ;; zero_extend version of above @@ -2700,6 +2807,7 @@ "" "\\t%w0, %w1, %w2" [(set_attr "v8type" "logic,logic_imm") + (set_attr "type" "arlo_reg,arlo_imm") (set_attr "mode" "SI")]) (define_insn "*and3_compare0" @@ -2713,6 +2821,7 @@ "" "ands\\t%0, %1, %2" [(set_attr "v8type" "logics,logics_imm") + (set_attr "type" "arlo_reg,arlo_imm") (set_attr "mode" "")] ) @@ -2728,6 +2837,7 @@ "" "ands\\t%w0, %w1, %w2" [(set_attr "v8type" "logics,logics_imm") + (set_attr "type" "arlo_reg,arlo_imm") (set_attr "mode" "SI")] ) @@ -2744,6 +2854,7 @@ "" "ands\\t%0, %3, %1, %2" [(set_attr "v8type" "logics_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")] ) @@ -2762,6 +2873,7 @@ "" "ands\\t%w0, %w3, %w1, %2" [(set_attr "v8type" "logics_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")] ) @@ -2774,6 +2886,7 @@ "" "\\t%0, %3, %1, %2" [(set_attr "v8type" "logic_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")]) ;; zero_extend version of above @@ -2787,6 +2900,7 @@ "" "\\t%w0, %w3, %w1, %2" [(set_attr "v8type" "logic_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")]) (define_insn "one_cmpl2" @@ -2795,6 +2909,7 @@ "" "mvn\\t%0, %1" [(set_attr "v8type" "logic") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) (define_insn "*one_cmpl_2" @@ -2804,6 +2919,7 @@ "" "mvn\\t%0, %1, %2" [(set_attr "v8type" "logic_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")]) (define_insn "*_one_cmpl3" @@ -2814,6 +2930,7 @@ "" "\\t%0, %2, %1" [(set_attr "v8type" "logic") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) (define_insn "*and_one_cmpl3_compare0" @@ -2828,6 +2945,7 @@ "" "bics\\t%0, %2, %1" [(set_attr "v8type" "logics") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) ;; zero_extend version of above @@ -2843,6 +2961,7 @@ "" "bics\\t%w0, %w2, %w1" [(set_attr "v8type" "logics") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")]) (define_insn "*_one_cmpl_3" @@ -2855,6 +2974,7 @@ "" "\\t%0, %3, %1, %2" [(set_attr "v8type" "logic_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")]) (define_insn "*and_one_cmpl_3_compare0" @@ -2873,6 +2993,7 @@ "" "bics\\t%0, %3, %1, %2" [(set_attr "v8type" "logics_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")]) ;; zero_extend version of above @@ -2892,6 +3013,7 @@ "" "bics\\t%w0, %w3, %w1, %2" [(set_attr "v8type" "logics_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "SI")]) (define_insn "clz2" @@ -2900,6 +3022,7 @@ "" "clz\\t%0, %1" [(set_attr "v8type" "clz") + (set_attr "type" "clz") (set_attr "mode" "")]) (define_expand "ffs2" @@ -2923,6 +3046,7 @@ "" "cls\\t%0, %1" [(set_attr "v8type" "clz") + (set_attr "type" "clz") (set_attr "mode" "")]) (define_insn "rbit2" @@ -2931,6 +3055,7 @@ "" "rbit\\t%0, %1" [(set_attr "v8type" "rbit") + (set_attr "type" "clz") (set_attr "mode" "")]) (define_expand "ctz2" @@ -2953,6 +3078,7 @@ "" "tst\\t%0, %1" [(set_attr "v8type" "logics") + (set_attr "type" "arlo_reg") (set_attr "mode" "")]) (define_insn "*and_3nr_compare0" @@ -2966,6 +3092,7 @@ "" "tst\\t%2, %0, %1" [(set_attr "v8type" "logics_shift") + (set_attr "type" "arlo_shift") (set_attr "mode" "")]) ;; ------------------------------------------------------------------- @@ -3063,6 +3190,7 @@ "" "\\t%0, %1, %2" [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "")] ) @@ -3075,6 +3203,7 @@ "" "\\t%w0, %w1, %w2" [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "SI")] ) @@ -3085,6 +3214,7 @@ "" "lsl\\t%0, %1, %2" [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "")] ) @@ -3098,6 +3228,7 @@ return "\t%w0, %w1, %2, %3"; } [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3111,6 +3242,7 @@ (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (mode))" "extr\\t%0, %1, %2, %4" [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "")] ) @@ -3126,6 +3258,7 @@ (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "SI")] ) @@ -3139,6 +3272,7 @@ return "ror\\t%0, %1, %3"; } [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "")] ) @@ -3154,6 +3288,7 @@ return "ror\\t%w0, %w1, %3"; } [(set_attr "v8type" "shift") + (set_attr "type" "shift") (set_attr "mode" "SI")] ) @@ -3168,6 +3303,7 @@ return "bfiz\t%0, %1, %2, %3"; } [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3182,6 +3318,7 @@ return "ubfx\t%0, %1, %2, %3"; } [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3196,6 +3333,7 @@ return "sbfx\\t%0, %1, %2, %3"; } [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3220,6 +3358,7 @@ "" "bfx\\t%0, %1, %3, %2" [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3264,6 +3403,7 @@ > GET_MODE_BITSIZE (mode)))" "bfi\\t%0, %3, %2, %1" [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3279,6 +3419,7 @@ > GET_MODE_BITSIZE (mode)))" "bfxil\\t%0, %2, %3, %1" [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3295,6 +3436,7 @@ return "bfiz\t%0, %1, %2, %3"; } [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3309,6 +3451,7 @@ && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0" "ubfiz\\t%0, %1, %2, %P3" [(set_attr "v8type" "bfm") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3318,6 +3461,7 @@ "" "rev\\t%0, %1" [(set_attr "v8type" "rev") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3327,6 +3471,7 @@ "" "rev16\\t%w0, %w1" [(set_attr "v8type" "rev") + (set_attr "type" "arlo_reg") (set_attr "mode" "HI")] ) @@ -3337,6 +3482,7 @@ "" "rev\\t%w0, %w1" [(set_attr "v8type" "rev") + (set_attr "type" "arlo_reg") (set_attr "mode" "SI")] ) @@ -3354,6 +3500,7 @@ "TARGET_FLOAT" "frint\\t%0, %1" [(set_attr "v8type" "frint") + (set_attr "type" "f_rint") (set_attr "mode" "")] ) @@ -3366,6 +3513,7 @@ "TARGET_FLOAT" "fcvt\\t%0, %1" [(set_attr "v8type" "fcvtf2i") + (set_attr "type" "f_cvt") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3380,6 +3528,7 @@ "TARGET_FLOAT" "fmadd\\t%0, %1, %2, %3" [(set_attr "v8type" "fmadd") + (set_attr "type" "fmac") (set_attr "mode" "")] ) @@ -3391,6 +3540,7 @@ "TARGET_FLOAT" "fmsub\\t%0, %1, %2, %3" [(set_attr "v8type" "fmadd") + (set_attr "type" "fmac") (set_attr "mode" "")] ) @@ -3402,6 +3552,7 @@ "TARGET_FLOAT" "fnmsub\\t%0, %1, %2, %3" [(set_attr "v8type" "fmadd") + (set_attr "type" "fmac") (set_attr "mode" "")] ) @@ -3413,6 +3564,7 @@ "TARGET_FLOAT" "fnmadd\\t%0, %1, %2, %3" [(set_attr "v8type" "fmadd") + (set_attr "type" "fmac") (set_attr "mode" "")] ) @@ -3425,6 +3577,7 @@ "!HONOR_SIGNED_ZEROS (mode) && TARGET_FLOAT" "fnmadd\\t%0, %1, %2, %3" [(set_attr "v8type" "fmadd") + (set_attr "type" "fmac") (set_attr "mode" "")] ) @@ -3438,6 +3591,7 @@ "TARGET_FLOAT" "fcvt\\t%d0, %s1" [(set_attr "v8type" "fcvt") + (set_attr "type" "f_cvt") (set_attr "mode" "DF") (set_attr "mode2" "SF")] ) @@ -3448,6 +3602,7 @@ "TARGET_FLOAT" "fcvt\\t%s0, %d1" [(set_attr "v8type" "fcvt") + (set_attr "type" "f_cvt") (set_attr "mode" "SF") (set_attr "mode2" "DF")] ) @@ -3458,6 +3613,7 @@ "TARGET_FLOAT" "fcvtzs\\t%0, %1" [(set_attr "v8type" "fcvtf2i") + (set_attr "type" "f_cvt") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3468,6 +3624,7 @@ "TARGET_FLOAT" "fcvtzu\\t%0, %1" [(set_attr "v8type" "fcvtf2i") + (set_attr "type" "f_cvt") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3478,6 +3635,7 @@ "TARGET_FLOAT" "scvtf\\t%0, %1" [(set_attr "v8type" "fcvti2f") + (set_attr "type" "f_cvt") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3488,6 +3646,7 @@ "TARGET_FLOAT" "ucvtf\\t%0, %1" [(set_attr "v8type" "fcvt") + (set_attr "type" "f_cvt") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3504,6 +3663,7 @@ "TARGET_FLOAT" "fadd\\t%0, %1, %2" [(set_attr "v8type" "fadd") + (set_attr "type" "fadd") (set_attr "mode" "")] ) @@ -3515,6 +3675,7 @@ "TARGET_FLOAT" "fsub\\t%0, %1, %2" [(set_attr "v8type" "fadd") + (set_attr "type" "fadd") (set_attr "mode" "")] ) @@ -3526,6 +3687,7 @@ "TARGET_FLOAT" "fmul\\t%0, %1, %2" [(set_attr "v8type" "fmul") + (set_attr "type" "fmul") (set_attr "mode" "")] ) @@ -3537,6 +3699,7 @@ "TARGET_FLOAT" "fnmul\\t%0, %1, %2" [(set_attr "v8type" "fmul") + (set_attr "type" "fmul") (set_attr "mode" "")] ) @@ -3548,6 +3711,7 @@ "TARGET_FLOAT" "fdiv\\t%0, %1, %2" [(set_attr "v8type" "fdiv") + (set_attr "type" "fdiv") (set_attr "mode" "")] ) @@ -3557,6 +3721,7 @@ "TARGET_FLOAT" "fneg\\t%0, %1" [(set_attr "v8type" "ffarith") + (set_attr "type" "ffarith") (set_attr "mode" "")] ) @@ -3566,6 +3731,7 @@ "TARGET_FLOAT" "fsqrt\\t%0, %1" [(set_attr "v8type" "fsqrt") + (set_attr "type" "fdiv") (set_attr "mode" "")] ) @@ -3575,6 +3741,7 @@ "TARGET_FLOAT" "fabs\\t%0, %1" [(set_attr "v8type" "ffarith") + (set_attr "type" "ffarith") (set_attr "mode" "")] ) @@ -3589,6 +3756,7 @@ "TARGET_FLOAT" "fmaxnm\\t%0, %1, %2" [(set_attr "v8type" "fminmax") + (set_attr "type" "f_minmax") (set_attr "mode" "")] ) @@ -3599,6 +3767,7 @@ "TARGET_FLOAT" "fminnm\\t%0, %1, %2" [(set_attr "v8type" "fminmax") + (set_attr "type" "f_minmax") (set_attr "mode" "")] ) @@ -3609,6 +3778,7 @@ "TARGET_FLOAT" "frecp\\t%0, %1" [(set_attr "v8type" "frecp") + (set_attr "type" "ffarith") (set_attr "mode" "")] ) @@ -3620,6 +3790,7 @@ "TARGET_FLOAT" "frecps\\t%0, %1, %2" [(set_attr "v8type" "frecps") + (set_attr "type" "ffarith") (set_attr "mode" "")] ) @@ -3685,6 +3856,7 @@ "reload_completed || reload_in_progress" "fmov\\t%x0, %d1" [(set_attr "v8type" "fmovf2i") + (set_attr "type" "f_2_r") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3697,6 +3869,7 @@ "reload_completed || reload_in_progress" "fmov\\t%x0, %1.d[1]" [(set_attr "v8type" "fmovf2i") + (set_attr "type" "f_2_r") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3708,6 +3881,7 @@ "reload_completed || reload_in_progress" "fmov\\t%0.d[1], %x1" [(set_attr "v8type" "fmovi2f") + (set_attr "type" "r_2_f") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3718,6 +3892,7 @@ "reload_completed || reload_in_progress" "fmov\\t%d0, %x1" [(set_attr "v8type" "fmovi2f") + (set_attr "type" "r_2_f") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3729,6 +3904,7 @@ "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" [(set_attr "v8type" "fmovi2f") + (set_attr "type" "r_2_f") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3761,6 +3937,7 @@ "" "add\\t%0, %1, :lo12:%a2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "")] ) @@ -3773,6 +3950,7 @@ "" "ldr\\t%0, [%1, #:got_lo12:%a2]" [(set_attr "v8type" "load1") + (set_attr "type" "load1") (set_attr "mode" "")] ) @@ -3786,6 +3964,7 @@ "TARGET_ILP32" "ldr\\t%w0, [%1, #:got_lo12:%a2]" [(set_attr "v8type" "load1") + (set_attr "type" "load1") (set_attr "mode" "DI")] ) @@ -3796,6 +3975,7 @@ "" "ldr\\t%0, %L1" [(set_attr "v8type" "load1") + (set_attr "type" "load1") (set_attr "mode" "DI")] ) @@ -3805,6 +3985,7 @@ "" "mrs\\t%0, tpidr_el0" [(set_attr "v8type" "mrs") + (set_attr "type" "mov_reg") (set_attr "mode" "DI")] ) @@ -3830,6 +4011,7 @@ "" "adrp\\tx0, %A1\;add\\tx0, x0, %L1\;bl\\t%2\;nop" [(set_attr "v8type" "call") + (set_attr "type" "call") (set_attr "length" "16")]) (define_insn "tlsie_small" @@ -3839,6 +4021,7 @@ "" "adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]" [(set_attr "v8type" "load1") + (set_attr "type" "load1") (set_attr "mode" "DI") (set_attr "length" "8")] ) @@ -3851,6 +4034,7 @@ "" "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" [(set_attr "v8type" "alu") + (set_attr "type" "arlo_reg") (set_attr "mode" "DI") (set_attr "length" "8")] ) @@ -3864,6 +4048,7 @@ "TARGET_TLS_DESC" "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1" [(set_attr "v8type" "call") + (set_attr "type" "call") (set_attr "length" "16")]) (define_insn "stack_tie" -- 2.7.4