From 34aff47521c3e0cbac58b0d5793197f76a304295 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 17 Feb 2023 14:36:48 -0800 Subject: [PATCH] [RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC Rather than using operator[] on getFeatureBits we can use hasFeature to shorten the code. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D144300 --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 15 +++++--------- .../RISCV/Disassembler/RISCVDisassembler.cpp | 24 ++++++++++------------ .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 16 +++++++-------- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 8 ++++---- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-- 5 files changed, 29 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index d7529a7..d37ae8c 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -183,19 +183,15 @@ class RISCVAsmParser : public MCTargetAsmParser { bool parseDirectiveVariantCC(); void setFeatureBits(uint64_t Feature, StringRef FeatureString) { - if (!(getSTI().getFeatureBits()[Feature])) { + if (!(getSTI().hasFeature(Feature))) { MCSubtargetInfo &STI = copySTI(); setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } } - bool getFeatureBits(uint64_t Feature) { - return getSTI().getFeatureBits()[Feature]; - } - void clearFeatureBits(uint64_t Feature, StringRef FeatureString) { - if (getSTI().getFeatureBits()[Feature]) { + if (getSTI().hasFeature(Feature)) { MCSubtargetInfo &STI = copySTI(); setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); @@ -249,13 +245,12 @@ public: setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); auto ABIName = StringRef(Options.ABIName); - if (ABIName.endswith("f") && - !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { + if (ABIName.endswith("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) { errs() << "Hard-float 'f' ABI can't be used for a target that " "doesn't support the F instruction set extension (ignoring " "target-abi)\n"; } else if (ABIName.endswith("d") && - !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { + !getSTI().hasFeature(RISCV::FeatureStdExtD)) { errs() << "Hard-float 'd' ABI can't be used for a target that " "doesn't support the D instruction set extension (ignoring " "target-abi)\n"; @@ -2045,7 +2040,7 @@ bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info, // cause relaxations. Unfortunately instruction processing stage occurs in the // same pass as relocation emission, so it's too late to set a 'sticky bit' // for the entire file. - if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) { + if (getSTI().hasFeature(RISCV::FeatureRelax)) { auto *Assembler = getTargetStreamer().getStreamer().getAssemblerPtr(); if (Assembler != nullptr) { RISCVAsmBackend &MAB = diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b379976..cb20115 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -61,9 +61,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { - const FeatureBitset &FeatureBits = - Decoder->getSubtargetInfo().getFeatureBits(); - bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + bool IsRV32E = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRV32E); if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) return MCDisassembler::Fail; @@ -448,8 +446,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Insn = support::endian::read32le(Bytes.data()); - if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] && - !STI.getFeatureBits()[RISCV::Feature64Bit]) { + if (STI.hasFeature(RISCV::FeatureStdExtZdinx) && + !STI.hasFeature(RISCV::Feature64Bit)) { LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and" "rv32)\n"); Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address, @@ -457,49 +455,49 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) { + if (STI.hasFeature(RISCV::FeatureStdExtZfinx)) { LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n"); Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) { + if (STI.hasFeature(RISCV::FeatureVendorXVentanaCondOps)) { LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n"); Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBa]) { + if (STI.hasFeature(RISCV::FeatureVendorXTHeadBa)) { LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBb]) { + if (STI.hasFeature(RISCV::FeatureVendorXTHeadBb)) { LLVM_DEBUG(dbgs() << "Trying XTHeadBb custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadBb32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBs]) { + if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) { LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadMac]) { + if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) { LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) { + if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) { LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI); @@ -519,7 +517,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Insn = support::endian::read16le(Bytes.data()); - if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { + if (!STI.hasFeature(RISCV::Feature64Bit)) { LLVM_DEBUG( dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n"); // Calling the auto-generated decoder function. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 22cc65d..1232b32 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -134,7 +134,7 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, return true; } - return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; + return STI.hasFeature(RISCV::FeatureRelax) || ForceRelocs; } bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, @@ -374,11 +374,11 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, Count -= 1; } - bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC]; - bool HasStdExtZca = STI->getFeatureBits()[RISCV::FeatureExtZca]; + bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) || + STI->hasFeature(RISCV::FeatureExtZca); // The canonical nop on RVC is c.nop. if (Count % 4 == 2) { - OS.write((HasStdExtC || HasStdExtZca) ? "\x01\0" : "\0\0", 2); + OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2); Count -= 2; } @@ -602,11 +602,11 @@ bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign( const MCAlignFragment &AF, unsigned &Size) { // Calculate Nops Size only when linker relaxation enabled. const MCSubtargetInfo *STI = AF.getSubtargetInfo(); - if (!STI->getFeatureBits()[RISCV::FeatureRelax]) + if (!STI->hasFeature(RISCV::FeatureRelax)) return false; - bool UseCompressedNop = STI->getFeatureBits()[RISCV::FeatureStdExtC] || - STI->getFeatureBits()[RISCV::FeatureExtZca]; + bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) || + STI->hasFeature(RISCV::FeatureExtZca); unsigned MinNopLen = UseCompressedNop ? 2 : 4; if (AF.getAlignment() <= MinNopLen) { @@ -627,7 +627,7 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, MCAlignFragment &AF) { // Insert the fixup only when linker relaxation enabled. const MCSubtargetInfo *STI = AF.getSubtargetInfo(); - if (!STI->getFeatureBits()[RISCV::FeatureRelax]) + if (!STI->hasFeature(RISCV::FeatureRelax)) return false; // Calculate total Nops we need to insert. If there are none to insert diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index c01f3aa..f5c5fb5 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -168,7 +168,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. - if (STI.getFeatureBits()[RISCV::FeatureRelax]) { + if (STI.hasFeature(RISCV::FeatureRelax)) { const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); Fixups.push_back(MCFixup::create( 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); @@ -215,8 +215,8 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS, Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ; bool UseCompressedBr = false; - if (IsEqTest && (STI.getFeatureBits()[RISCV::FeatureStdExtC] || - STI.getFeatureBits()[RISCV::FeatureExtZca])) { + if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) || + STI.hasFeature(RISCV::FeatureExtZca))) { if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 && SrcReg2.id() == RISCV::X0) { UseCompressedBr = true; @@ -344,7 +344,7 @@ RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; + bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax); const MCOperand &MO = MI.getOperand(OpNo); MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ebb32bd..0f00fc8 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12704,8 +12704,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments( case CallingConv::Fast: break; case CallingConv::GHC: - if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] || - !MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD]) + if (!Subtarget.hasStdExtF() || !Subtarget.hasStdExtD()) report_fatal_error( "GHC calling convention requires the F and D instruction set extensions"); } -- 2.7.4