From 34978602032fbd312998c8c3ef32316717013254 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 20 Aug 2020 17:46:16 +0100 Subject: [PATCH] [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister ... in favour of the isPhysical/isVirtual methods. --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 2 +- .../Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 29 +++---- llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 2 +- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | 88 +++++++++++----------- llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 15 ++-- llvm/lib/Target/AMDGPU/GCNRegPressure.h | 2 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 10 +-- llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp | 6 +- llvm/lib/Target/AMDGPU/R600MachineScheduler.h | 2 +- llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/R600RegisterInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 18 ++--- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 11 ++- llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 20 ++--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 43 +++++------ llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 13 ++-- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 4 +- llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 14 ++-- llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 20 ++--- .../Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 8 +- llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 12 +-- llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 4 +- llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 30 ++++---- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 11 ++- 27 files changed, 182 insertions(+), 200 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index d78329f..2dd5351 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -555,8 +555,8 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N, unsigned OpNo) const { if (!N->isMachineOpcode()) { if (N->getOpcode() == ISD::CopyToReg) { - unsigned Reg = cast(N->getOperand(1))->getReg(); - if (Register::isVirtualRegister(Reg)) { + Register Reg = cast(N->getOperand(1))->getReg(); + if (Reg.isVirtual()) { MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo(); return MRI.getRegClass(Reg); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index c9f9eb6..cb6f769 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -175,7 +175,7 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const { } for (const MachineOperand &MO : I.operands()) { - if (Register::isPhysicalRegister(MO.getReg())) + if (MO.getReg().isPhysical()) continue; const TargetRegisterClass *RC = diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index f61af5a..db522ff 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -342,11 +342,11 @@ protected: LinearizedRegion *Parent; RegionMRT *RMRT; - void storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, + void storeLiveOutReg(MachineBasicBlock *MBB, Register Reg, MachineInstr *DefInstr, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo); - void storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg, + void storeLiveOutRegRegion(RegionMRT *Region, Register Reg, MachineInstr *DefInstr, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, @@ -397,7 +397,7 @@ public: void replaceLiveOut(unsigned OldReg, unsigned NewReg); - void replaceRegister(unsigned Register, unsigned NewRegister, + void replaceRegister(unsigned Register, class Register NewRegister, MachineRegisterInfo *MRI, bool ReplaceInside, bool ReplaceOutside, bool IncludeLoopPHIs); @@ -690,12 +690,12 @@ RegionMRT *MRT::buildMRT(MachineFunction &MF, return Result; } -void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, +void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, Register Reg, MachineInstr *DefInstr, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); // If this is a source register to a PHI we are chaining, it @@ -730,12 +730,12 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, } } -void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg, +void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, Register Reg, MachineInstr *DefInstr, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); for (auto &UI : MRI->use_operands(Reg)) { @@ -907,7 +907,8 @@ void LinearizedRegion::replaceLiveOut(unsigned OldReg, unsigned NewReg) { } } -void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, +void LinearizedRegion::replaceRegister(unsigned Register, + class Register NewRegister, MachineRegisterInfo *MRI, bool ReplaceInside, bool ReplaceOutside, bool IncludeLoopPHI) { @@ -950,7 +951,7 @@ void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, (IncludeLoopPHI && IsLoopPHI); if (ShouldReplace) { - if (Register::isPhysicalRegister(NewRegister)) { + if (NewRegister.isPhysical()) { LLVM_DEBUG(dbgs() << "Trying to substitute physical register: " << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); @@ -1025,7 +1026,7 @@ void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) { for (auto &RI : II.uses()) { if (RI.isReg()) { Register Reg = RI.getReg(); - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { if (hasNoDef(Reg, MRI)) continue; if (!MRI->hasOneDef(Reg)) { @@ -1168,7 +1169,7 @@ private: void createEntryPHIs(LinearizedRegion *CurrentRegion); void resolvePHIInfos(MachineBasicBlock *FunctionEntry); - void replaceRegisterWith(unsigned Register, unsigned NewRegister); + void replaceRegisterWith(unsigned Register, class Register NewRegister); MachineBasicBlock *createIfRegion(MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBB, @@ -2224,8 +2225,8 @@ void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegi PHIInfo.clear(); } -void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, - unsigned NewRegister) { +void AMDGPUMachineCFGStructurizer::replaceRegisterWith( + unsigned Register, class Register NewRegister) { assert(Register != NewRegister && "Cannot replace a reg with itself"); for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register), @@ -2233,7 +2234,7 @@ void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, I != E;) { MachineOperand &O = *I; ++I; - if (Register::isPhysicalRegister(NewRegister)) { + if (NewRegister.isPhysical()) { LLVM_DEBUG(dbgs() << "Trying to substitute physical register: " << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp index 5734608..ff9228e 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -175,7 +175,7 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const { for (unsigned I = 0; I < Info->VAddrDwords; ++I) { const MachineOperand &Op = MI.getOperand(VAddr0Idx + I); Register Reg = Op.getReg(); - if (Register::isPhysicalRegister(Reg) || !VRM->isAssignedReg(Reg)) + if (Reg.isPhysical() || !VRM->isAssignedReg(Reg)) return NSA_Status::FIXED; Register PhysReg = VRM->getPhys(Reg); diff --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp index 79b33e2..d66e26c 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp @@ -76,14 +76,14 @@ class GCNRegBankReassign : public MachineFunctionPass { public: OperandMask(unsigned r, unsigned s, unsigned m) : Reg(r), SubReg(s), Mask(m) {} - unsigned Reg; + Register Reg; unsigned SubReg; unsigned Mask; }; class Candidate { public: - Candidate(MachineInstr *mi, unsigned reg, unsigned subreg, + Candidate(MachineInstr *mi, Register reg, unsigned subreg, unsigned freebanks, unsigned weight) : MI(mi), Reg(reg), SubReg(subreg), FreeBanks(freebanks), Weight(weight) {} @@ -100,7 +100,7 @@ class GCNRegBankReassign : public MachineFunctionPass { #endif MachineInstr *MI; - unsigned Reg; + Register Reg; unsigned SubReg; unsigned FreeBanks; unsigned Weight; @@ -164,32 +164,32 @@ private: const MCPhysReg *CSRegs; // Returns bank for a phys reg. - unsigned getPhysRegBank(unsigned Reg, unsigned SubReg) const; + unsigned getPhysRegBank(Register Reg, unsigned SubReg) const; // Return a bit set for each register bank used. 4 banks for VGPRs and // 8 banks for SGPRs. // Registers already processed and recorded in RegsUsed are excluded. // If Bank is not -1 assume Reg:SubReg to belong to that Bank. - uint32_t getRegBankMask(unsigned Reg, unsigned SubReg, int Bank); + uint32_t getRegBankMask(Register Reg, unsigned SubReg, int Bank); // Analyze one instruction returning the number of stalls and a mask of the // banks used by all operands. // If Reg and Bank are provided, assume all uses of Reg will be replaced with // a register chosen from Bank. std::pair analyzeInst(const MachineInstr &MI, - unsigned Reg = AMDGPU::NoRegister, + Register Reg = Register(), unsigned SubReg = 0, int Bank = -1); // Return true if register is regular VGPR or SGPR or their tuples. // Returns false for special registers like m0, vcc etc. - bool isReassignable(unsigned Reg) const; + bool isReassignable(Register Reg) const; // Check if registers' defs are old and may be pre-loaded. // Returns 0 if both registers are old enough, 1 or 2 if one or both // registers will not likely be pre-loaded. unsigned getOperandGatherWeight(const MachineInstr& MI, - unsigned Reg1, - unsigned Reg2, + Register Reg1, + Register Reg2, unsigned StallCycles) const; @@ -199,7 +199,7 @@ private: // Find all bank bits in UsedBanks where Mask can be relocated to. // Bank is relative to the register and not its subregister component. // Returns 0 is a register is not reassignable. - unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask, + unsigned getFreeBanks(Register Reg, unsigned SubReg, unsigned Mask, unsigned UsedBanks) const; // Add cadidate instruction to the work list. @@ -211,13 +211,13 @@ private: unsigned collectCandidates(MachineFunction &MF, bool Collect = true); // Remove all candidates that read specified register. - void removeCandidates(unsigned Reg); + void removeCandidates(Register Reg); // Compute stalls within the uses of SrcReg replaced by a register from // Bank. If Bank is -1 does not perform substitution. If Collect is set // candidates are collected and added to work list. - unsigned computeStallCycles(unsigned SrcReg, - unsigned Reg = AMDGPU::NoRegister, + unsigned computeStallCycles(Register SrcReg, + Register Reg = Register(), unsigned SubReg = 0, int Bank = -1, bool Collect = false); @@ -234,9 +234,9 @@ private: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) public: - Printable printReg(unsigned Reg, unsigned SubReg = 0) const { + Printable printReg(Register Reg, unsigned SubReg = 0) const { return Printable([Reg, SubReg, this](raw_ostream &OS) { - if (Register::isPhysicalRegister(Reg)) { + if (Reg.isPhysical()) { OS << llvm::printReg(Reg, TRI); return; } @@ -280,9 +280,9 @@ char GCNRegBankReassign::ID = 0; char &llvm::GCNRegBankReassignID = GCNRegBankReassign::ID; -unsigned GCNRegBankReassign::getPhysRegBank(unsigned Reg, +unsigned GCNRegBankReassign::getPhysRegBank(Register Reg, unsigned SubReg) const { - assert(Register::isPhysicalRegister(Reg)); + assert(Reg.isPhysical()); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); unsigned Size = TRI->getRegSizeInBits(*RC); @@ -300,17 +300,17 @@ unsigned GCNRegBankReassign::getPhysRegBank(unsigned Reg, } if (TRI->hasVGPRs(RC)) { - Reg -= AMDGPU::VGPR0; - return Reg % NUM_VGPR_BANKS; + unsigned RegNo = Reg - AMDGPU::VGPR0; + return RegNo % NUM_VGPR_BANKS; } - Reg = TRI->getEncodingValue(Reg) / 2; - return Reg % NUM_SGPR_BANKS + SGPR_BANK_OFFSET; + unsigned RegNo = TRI->getEncodingValue(Reg) / 2; + return RegNo % NUM_SGPR_BANKS + SGPR_BANK_OFFSET; } -uint32_t GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, +uint32_t GCNRegBankReassign::getRegBankMask(Register Reg, unsigned SubReg, int Bank) { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { if (!VRM->isAssignedReg(Reg)) return 0; @@ -335,23 +335,23 @@ uint32_t GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, if (TRI->hasVGPRs(RC)) { // VGPRs have 4 banks assigned in a round-robin fashion. - Reg -= AMDGPU::VGPR0; + unsigned RegNo = Reg - AMDGPU::VGPR0; uint32_t Mask = maskTrailingOnes(Size); unsigned Used = 0; // Bitmask lacks an extract method for (unsigned I = 0; I < Size; ++I) - if (RegsUsed.test(Reg + I)) + if (RegsUsed.test(RegNo + I)) Used |= 1 << I; - RegsUsed.set(Reg, Reg + Size); + RegsUsed.set(RegNo, RegNo + Size); Mask &= ~Used; - Mask <<= (Bank == -1) ? Reg % NUM_VGPR_BANKS : uint32_t(Bank); + Mask <<= (Bank == -1) ? RegNo % NUM_VGPR_BANKS : uint32_t(Bank); return (Mask | (Mask >> NUM_VGPR_BANKS)) & VGPR_BANK_MASK; } // SGPRs have 8 banks holding 2 consequitive registers each. - Reg = TRI->getEncodingValue(Reg) / 2; + unsigned RegNo = TRI->getEncodingValue(Reg) / 2; unsigned StartBit = AMDGPU::VGPR_32RegClass.getNumRegs(); - if (Reg + StartBit >= RegsUsed.size()) + if (RegNo + StartBit >= RegsUsed.size()) return 0; if (Size > 1) @@ -359,11 +359,11 @@ uint32_t GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, unsigned Mask = (1 << Size) - 1; unsigned Used = 0; for (unsigned I = 0; I < Size; ++I) - if (RegsUsed.test(StartBit + Reg + I)) + if (RegsUsed.test(StartBit + RegNo + I)) Used |= 1 << I; - RegsUsed.set(StartBit + Reg, StartBit + Reg + Size); + RegsUsed.set(StartBit + RegNo, StartBit + RegNo + Size); Mask &= ~Used; - Mask <<= (Bank == -1) ? Reg % NUM_SGPR_BANKS + Mask <<= (Bank == -1) ? RegNo % NUM_SGPR_BANKS : unsigned(Bank - SGPR_BANK_OFFSET); Mask = (Mask | (Mask >> NUM_SGPR_BANKS)) & SGPR_BANK_SHIFTED_MASK; // Reserve 4 bank ids for VGPRs. @@ -371,7 +371,7 @@ uint32_t GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, } std::pair -GCNRegBankReassign::analyzeInst(const MachineInstr &MI, unsigned Reg, +GCNRegBankReassign::analyzeInst(const MachineInstr &MI, Register Reg, unsigned SubReg, int Bank) { unsigned StallCycles = 0; unsigned UsedBanks = 0; @@ -434,8 +434,8 @@ GCNRegBankReassign::analyzeInst(const MachineInstr &MI, unsigned Reg, } unsigned GCNRegBankReassign::getOperandGatherWeight(const MachineInstr& MI, - unsigned Reg1, - unsigned Reg2, + Register Reg1, + Register Reg2, unsigned StallCycles) const { unsigned Defs = 0; @@ -455,8 +455,8 @@ unsigned GCNRegBankReassign::getOperandGatherWeight(const MachineInstr& MI, return countPopulation(Defs); } -bool GCNRegBankReassign::isReassignable(unsigned Reg) const { - if (Register::isPhysicalRegister(Reg) || !VRM->isAssignedReg(Reg)) +bool GCNRegBankReassign::isReassignable(Register Reg) const { + if (Reg.isPhysical() || !VRM->isAssignedReg(Reg)) return false; const MachineInstr *Def = MRI->getUniqueVRegDef(Reg); @@ -531,7 +531,7 @@ unsigned GCNRegBankReassign::getFreeBanks(unsigned Mask, return FreeBanks; } -unsigned GCNRegBankReassign::getFreeBanks(unsigned Reg, +unsigned GCNRegBankReassign::getFreeBanks(Register Reg, unsigned SubReg, unsigned Mask, unsigned UsedBanks) const { @@ -581,8 +581,8 @@ void GCNRegBankReassign::collectCandidates(MachineInstr& MI, if (!(OperandMasks[I].Mask & OperandMasks[J].Mask)) continue; - unsigned Reg1 = OperandMasks[I].Reg; - unsigned Reg2 = OperandMasks[J].Reg; + Register Reg1 = OperandMasks[I].Reg; + Register Reg2 = OperandMasks[J].Reg; unsigned SubReg1 = OperandMasks[I].SubReg; unsigned SubReg2 = OperandMasks[J].SubReg; unsigned Mask1 = OperandMasks[I].Mask; @@ -610,7 +610,7 @@ void GCNRegBankReassign::collectCandidates(MachineInstr& MI, } } -unsigned GCNRegBankReassign::computeStallCycles(unsigned SrcReg, unsigned Reg, +unsigned GCNRegBankReassign::computeStallCycles(Register SrcReg, Register Reg, unsigned SubReg, int Bank, bool Collect) { unsigned TotalStallCycles = 0; @@ -640,7 +640,7 @@ unsigned GCNRegBankReassign::scavengeReg(LiveInterval &LI, unsigned Bank, unsigned MaxReg = MaxNumRegs + (Bank < NUM_VGPR_BANKS ? AMDGPU::VGPR0 : AMDGPU::SGPR0); - for (unsigned Reg : RC->getRegisters()) { + for (Register Reg : RC->getRegisters()) { // Check occupancy limit. if (TRI->isSubRegisterEq(Reg, MaxReg)) break; @@ -708,7 +708,7 @@ unsigned GCNRegBankReassign::tryReassign(Candidate &C) { LRM->unassign(LI); while (!BankStalls.empty()) { BankStall BS = BankStalls.pop_back_val(); - unsigned Reg = scavengeReg(LI, BS.Bank, C.SubReg); + Register Reg = scavengeReg(LI, BS.Bank, C.SubReg); if (Reg == AMDGPU::NoRegister) { LLVM_DEBUG(dbgs() << "No free registers in bank " << printBank(BS.Bank) << '\n'); @@ -760,7 +760,7 @@ unsigned GCNRegBankReassign::collectCandidates(MachineFunction &MF, return TotalStallCycles; } -void GCNRegBankReassign::removeCandidates(unsigned Reg) { +void GCNRegBankReassign::removeCandidates(Register Reg) { Candidates.remove_if([Reg, this](const Candidate& C) { return C.MI->readsRegister(Reg, TRI); }); diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index 86a3cb9..245043a 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -87,9 +87,9 @@ bool llvm::isEqual(const GCNRPTracker::LiveRegSet &S1, /////////////////////////////////////////////////////////////////////////////// // GCNRegPressure -unsigned GCNRegPressure::getRegKind(unsigned Reg, +unsigned GCNRegPressure::getRegKind(Register Reg, const MachineRegisterInfo &MRI) { - assert(Register::isVirtualRegister(Reg)); + assert(Reg.isVirtual()); const auto RC = MRI.getRegClass(Reg); auto STI = static_cast(MRI.getTargetRegisterInfo()); return STI->isSGPRClass(RC) ? @@ -199,7 +199,7 @@ void GCNRegPressure::print(raw_ostream &OS, const GCNSubtarget *ST) const { static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI) { - assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg())); + assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual()); // We don't rely on read-undef flag because in case of tentative schedule // tracking it isn't set correctly yet. This works correctly however since @@ -212,7 +212,7 @@ static LaneBitmask getDefRegMask(const MachineOperand &MO, static LaneBitmask getUsedRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI, const LiveIntervals &LIS) { - assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg())); + assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual()); if (auto SubReg = MO.getSubReg()) return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg); @@ -233,7 +233,7 @@ collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI) { SmallVector Res; for (const auto &MO : MI.operands()) { - if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) + if (!MO.isReg() || !MO.getReg().isVirtual()) continue; if (!MO.isUse() || !MO.readsReg()) continue; @@ -330,8 +330,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) { MaxPressure = max(AtMIPressure, MaxPressure); for (const auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef() || - !Register::isVirtualRegister(MO.getReg()) || MO.isDead()) + if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead()) continue; auto Reg = MO.getReg(); @@ -410,7 +409,7 @@ void GCNDownwardRPTracker::advanceToNext() { if (!MO.isReg() || !MO.isDef()) continue; Register Reg = MO.getReg(); - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) continue; auto &LiveMask = LiveRegs[Reg]; auto PrevMask = LiveMask; diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h index 2ef7941..f0eab84 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h @@ -90,7 +90,7 @@ struct GCNRegPressure { private: unsigned Value[TOTAL_KINDS]; - static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI); + static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI); friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2); diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index dc2e73e..f7f2de3 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -338,7 +338,7 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, case R600::MASK_WRITE: { Register maskedRegister = MI.getOperand(0).getReg(); - assert(Register::isVirtualRegister(maskedRegister)); + assert(maskedRegister.isVirtual()); MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); TII->addFlag(*defInstr, 0, MO_FLAG_MASK); break; diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 088cf16..cf5791f 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -97,7 +97,7 @@ bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const { for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(), E = MBBI->operands_end(); I != E; ++I) { - if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() && + if (I->isReg() && !I->getReg().isVirtual() && I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg())) return false; } @@ -242,7 +242,7 @@ bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { for (MachineInstr::const_mop_iterator I = MI.operands_begin(), E = MI.operands_end(); I != E; ++I) { - if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg())) + if (!I->isReg() || !I->isUse() || I->getReg().isVirtual()) continue; if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg())) @@ -1191,15 +1191,15 @@ int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); for (std::pair LI : MRI.liveins()) { - unsigned Reg = LI.first; - if (Register::isVirtualRegister(Reg) || !IndirectRC->contains(Reg)) + Register Reg = LI.first; + if (Reg.isVirtual() || !IndirectRC->contains(Reg)) continue; unsigned RegIndex; unsigned RegEnd; for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; ++RegIndex) { - if (IndirectRC->getRegister(RegIndex) == Reg) + if (IndirectRC->getRegister(RegIndex) == (unsigned)Reg) break; } Offset = std::max(Offset, (int)RegIndex); diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp index 7569a262..d7d53c6 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp @@ -183,7 +183,7 @@ isPhysicalRegCopy(MachineInstr *MI) { if (MI->getOpcode() != R600::COPY) return false; - return !Register::isVirtualRegister(MI->getOperand(1).getReg()); + return !MI->getOperand(1).getReg().isVirtual(); } void R600SchedStrategy::releaseTopNode(SUnit *SU) { @@ -207,9 +207,9 @@ void R600SchedStrategy::releaseBottomNode(SUnit *SU) { } -bool R600SchedStrategy::regBelongsToClass(unsigned Reg, +bool R600SchedStrategy::regBelongsToClass(Register Reg, const TargetRegisterClass *RC) const { - if (!Register::isVirtualRegister(Reg)) { + if (!Reg.isVirtual()) { return RC->contains(Reg); } else { return MRI->getRegClass(Reg) == RC; diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.h b/llvm/lib/Target/AMDGPU/R600MachineScheduler.h index bc66f2e..abcc37f 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.h +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.h @@ -80,7 +80,7 @@ private: bool VLIW5; int getInstKind(SUnit *SU); - bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const; + bool regBelongsToClass(Register Reg, const TargetRegisterClass *RC) const; AluKind getAluKind(SUnit *SU) const; void LoadAlu(); unsigned AvailablesAluCount() const; diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp index 78ef71c..3ca03d2 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -94,8 +94,8 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( } } -bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { - assert(!Register::isVirtualRegister(Reg)); +bool R600RegisterInfo::isPhysRegLiveAcrossClauses(Register Reg) const { + assert(!Reg.isVirtual()); switch (Reg) { case R600::OQAP: diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h index 06981c4..1308e9f 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h @@ -45,7 +45,7 @@ struct R600RegisterInfo final : public R600GenRegisterInfo { // \returns true if \p Reg can be defined in one ALU clause and used in // another. - bool isPhysRegLiveAcrossClauses(unsigned Reg) const; + bool isPhysRegLiveAcrossClauses(Register Reg) const; void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index ef64c56..9b3b9f5 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -154,8 +154,7 @@ static bool hasVectorOperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { - if (!MI.getOperand(i).isReg() || - !Register::isVirtualRegister(MI.getOperand(i).getReg())) + if (!MI.getOperand(i).isReg() || !MI.getOperand(i).getReg().isVirtual()) continue; if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) @@ -171,14 +170,14 @@ getCopyRegClasses(const MachineInstr &Copy, Register DstReg = Copy.getOperand(0).getReg(); Register SrcReg = Copy.getOperand(1).getReg(); - const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg) + const TargetRegisterClass *SrcRC = SrcReg.isVirtual() ? MRI.getRegClass(SrcReg) : TRI.getPhysRegClass(SrcReg); // We don't really care about the subregister here. // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg()); - const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg) + const TargetRegisterClass *DstRC = DstReg.isVirtual() ? MRI.getRegClass(DstReg) : TRI.getPhysRegClass(DstReg); @@ -206,8 +205,7 @@ static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, auto &Src = MI.getOperand(1); Register DstReg = MI.getOperand(0).getReg(); Register SrcReg = Src.getReg(); - if (!Register::isVirtualRegister(SrcReg) || - !Register::isVirtualRegister(DstReg)) + if (!SrcReg.isVirtual() || !DstReg.isVirtual()) return false; for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { @@ -255,7 +253,7 @@ static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, return false; // It is illegal to have vreg inputs to a physreg defining reg_sequence. - if (Register::isPhysicalRegister(CopyUse.getOperand(0).getReg())) + if (CopyUse.getOperand(0).getReg().isPhysical()) return false; const TargetRegisterClass *SrcRC, *DstRC; @@ -619,7 +617,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *SrcRC, *DstRC; std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); - if (!Register::isVirtualRegister(DstReg)) { + if (!DstReg.isVirtual()) { // If the destination register is a physical register there isn't // really much we can do to fix this. // Some special instructions use M0 as an input. Some even only use @@ -639,7 +637,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) { Register SrcReg = MI.getOperand(1).getReg(); - if (!Register::isVirtualRegister(SrcReg)) { + if (!SrcReg.isVirtual()) { TII->moveToVALU(MI, MDT); break; } @@ -721,7 +719,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { // that can't be resolved in later operand folding pass bool Resolved = false; for (MachineOperand *MO : {&Src0, &Src1}) { - if (Register::isVirtualRegister(MO->getReg())) { + if (MO->getReg().isVirtual()) { MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); if (DefMI && TII->isFoldableCopy(*DefMI)) { const MachineOperand &Def = DefMI->getOperand(0); diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 73f09cc..ab89257a 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -539,7 +539,7 @@ static bool tryToFoldACImm(const SIInstrInfo *TII, return false; Register UseReg = OpToFold.getReg(); - if (!Register::isVirtualRegister(UseReg)) + if (!UseReg.isVirtual()) return false; if (llvm::find_if(FoldList, [UseMI](const FoldCandidate &FC) { @@ -1006,8 +1006,7 @@ static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI, MachineOperand &Op) { if (Op.isReg()) { // If this has a subregister, it obviously is a register source. - if (Op.getSubReg() != AMDGPU::NoSubRegister || - !Register::isVirtualRegister(Op.getReg())) + if (Op.getSubReg() != AMDGPU::NoSubRegister || !Op.getReg().isVirtual()) return &Op; MachineInstr *Def = MRI.getVRegDef(Op.getReg()); @@ -1277,7 +1276,7 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI, for (FoldCandidate &Fold : FoldList) { assert(!Fold.isReg() || Fold.OpToFold); - if (Fold.isReg() && Register::isVirtualRegister(Fold.OpToFold->getReg())) { + if (Fold.isReg() && Fold.OpToFold->getReg().isVirtual()) { Register Reg = Fold.OpToFold->getReg(); MachineInstr *DefMI = Fold.OpToFold->getParent(); if (DefMI->readsRegister(AMDGPU::EXEC, TRI) && @@ -1572,7 +1571,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { if (!FoldingImm && !OpToFold.isReg()) continue; - if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg())) + if (OpToFold.isReg() && !OpToFold.getReg().isVirtual()) continue; // Prevent folding operands backwards in the function. For example, @@ -1582,7 +1581,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { // ... // %vgpr0 = V_MOV_B32_e32 1, implicit %exec MachineOperand &Dst = MI.getOperand(0); - if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg())) + if (Dst.isReg() && !Dst.getReg().isVirtual()) continue; foldInstOperand(MI, OpToFold); diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp index 8ef02e7..8b3bc6b 100644 --- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp @@ -62,7 +62,7 @@ public: private: template - void forAllLanes(unsigned Reg, LaneBitmask LaneMask, Callable Func) const; + void forAllLanes(Register Reg, LaneBitmask LaneMask, Callable Func) const; bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const; bool checkPressure(const MachineInstr &MI, GCNDownwardRPTracker &RPT); @@ -145,15 +145,15 @@ static unsigned getMopState(const MachineOperand &MO) { S |= RegState::Kill; if (MO.isEarlyClobber()) S |= RegState::EarlyClobber; - if (Register::isPhysicalRegister(MO.getReg()) && MO.isRenamable()) + if (MO.getReg().isPhysical() && MO.isRenamable()) S |= RegState::Renamable; return S; } template -void SIFormMemoryClauses::forAllLanes(unsigned Reg, LaneBitmask LaneMask, +void SIFormMemoryClauses::forAllLanes(Register Reg, LaneBitmask LaneMask, Callable Func) const { - if (LaneMask.all() || Register::isPhysicalRegister(Reg) || + if (LaneMask.all() || Reg.isPhysical() || LaneMask == MRI->getMaxLaneMaskForVReg(Reg)) { Func(0); return; @@ -228,7 +228,7 @@ bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, if (Conflict == Map.end()) continue; - if (Register::isPhysicalRegister(Reg)) + if (Reg.isPhysical()) return false; LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); @@ -270,7 +270,7 @@ void SIFormMemoryClauses::collectRegUses(const MachineInstr &MI, if (!Reg) continue; - LaneBitmask Mask = Register::isVirtualRegister(Reg) + LaneBitmask Mask = Reg.isVirtual() ? TRI->getSubRegIndexLaneMask(MO.getSubReg()) : LaneBitmask::getAll(); RegUse &Map = MO.isDef() ? Defs : Uses; @@ -388,17 +388,17 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) { } for (auto &&R : Defs) { - unsigned Reg = R.first; + Register Reg = R.first; Uses.erase(Reg); - if (Register::isPhysicalRegister(Reg)) + if (Reg.isPhysical()) continue; LIS->removeInterval(Reg); LIS->createAndComputeVirtRegInterval(Reg); } for (auto &&R : Uses) { - unsigned Reg = R.first; - if (Register::isPhysicalRegister(Reg)) + Register Reg = R.first; + if (Reg.isPhysical()) continue; LIS->removeInterval(Reg); LIS->createAndComputeVirtRegInterval(Reg); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b744091..eb98798 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10783,8 +10783,7 @@ SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, // Insert a copy to a VReg_1 virtual register so LowerI1Copies doesn't have // to try understanding copies to physical registers. - if (SrcVal.getValueType() == MVT::i1 && - Register::isPhysicalRegister(DestReg->getReg())) { + if (SrcVal.getValueType() == MVT::i1 && DestReg->getReg().isPhysical()) { SDLoc SL(Node); MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); SDValue VReg = DAG.getRegister( @@ -10919,8 +10918,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, MachineOperand &Op = MI.getOperand(I); if ((OpInfo[I].RegClass != llvm::AMDGPU::AV_64RegClassID && OpInfo[I].RegClass != llvm::AMDGPU::AV_32RegClassID) || - !Register::isVirtualRegister(Op.getReg()) || - !TRI->isAGPR(MRI, Op.getReg())) + !Op.getReg().isVirtual() || !TRI->isAGPR(MRI, Op.getReg())) continue; auto *Src = MRI.getUniqueVRegDef(Op.getReg()); if (!Src || !Src->isCopy() || diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 18a3e36..11e487c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1331,7 +1331,7 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, // The SGPR spill/restore instructions only work on number sgprs, so we need // to make sure we are using the correct register class. - if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) { + if (SrcReg.isVirtual() && SpillSize == 4) { MachineRegisterInfo &MRI = MF->getRegInfo(); MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass); } @@ -2757,10 +2757,10 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, MRI->hasOneUse(Src0->getReg())) { Src0->ChangeToImmediate(Def->getOperand(1).getImm()); Src0Inlined = true; - } else if ((Register::isPhysicalRegister(Src0->getReg()) && + } else if ((Src0->getReg().isPhysical() && (ST.getConstantBusLimit(Opc) <= 1 && RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || - (Register::isVirtualRegister(Src0->getReg()) && + (Src0->getReg().isVirtual() && (ST.getConstantBusLimit(Opc) <= 1 && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))) return false; @@ -2775,9 +2775,9 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, MRI->hasOneUse(Src1->getReg()) && commuteInstruction(UseMI)) { Src0->ChangeToImmediate(Def->getOperand(1).getImm()); - } else if ((Register::isPhysicalRegister(Src1->getReg()) && + } else if ((Src1->getReg().isPhysical() && RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || - (Register::isVirtualRegister(Src1->getReg()) && + (Src1->getReg().isVirtual() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) return false; // VGPR is okay as Src1 - fallthrough @@ -3491,7 +3491,7 @@ bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, if (!MO.isUse()) return false; - if (Register::isVirtualRegister(MO.getReg())) + if (MO.getReg().isVirtual()) return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); // Null is free @@ -3560,7 +3560,7 @@ static bool shouldReadExec(const MachineInstr &MI) { static bool isSubRegOf(const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg) { - if (Register::isPhysicalRegister(SubReg.getReg())) + if (SubReg.getReg().isPhysical()) return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg()); return SubReg.getSubReg() != AMDGPU::NoSubRegister && @@ -3601,7 +3601,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, continue; Register Reg = Op.getReg(); - if (!Register::isVirtualRegister(Reg) && !RC->contains(Reg)) { + if (!Reg.isVirtual() && !RC->contains(Reg)) { ErrInfo = "inlineasm operand has incorrect register class."; return false; } @@ -3671,7 +3671,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, if (RegClass != -1) { Register Reg = MI.getOperand(i).getReg(); - if (Reg == AMDGPU::NoRegister || Register::isVirtualRegister(Reg)) + if (Reg == AMDGPU::NoRegister || Reg.isVirtual()) continue; const TargetRegisterClass *RC = RI.getRegClass(RegClass); @@ -3765,7 +3765,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, ErrInfo = "Dst register should be tied to implicit use of preserved register"; return false; - } else if (Register::isPhysicalRegister(TiedMO.getReg()) && + } else if (TiedMO.getReg().isPhysical() && Dst.getReg() != TiedMO.getReg()) { ErrInfo = "Dst register should use same physical register as preserved"; return false; @@ -4222,7 +4222,7 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, Desc.OpInfo[OpNo].RegClass == -1) { Register Reg = MI.getOperand(OpNo).getReg(); - if (Register::isVirtualRegister(Reg)) + if (Reg.isVirtual()) return MRI.getRegClass(Reg); return RI.getPhysRegClass(Reg); } @@ -4327,9 +4327,8 @@ bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI, return false; Register Reg = MO.getReg(); - const TargetRegisterClass *RC = Register::isVirtualRegister(Reg) - ? MRI.getRegClass(Reg) - : RI.getPhysRegClass(Reg); + const TargetRegisterClass *RC = + Reg.isVirtual() ? MRI.getRegClass(Reg) : RI.getPhysRegClass(Reg); const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); if (MO.getSubReg()) { @@ -4991,8 +4990,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI, if (MI.getOpcode() == AMDGPU::PHI) { const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { - if (!MI.getOperand(i).isReg() || - !Register::isVirtualRegister(MI.getOperand(i).getReg())) + if (!MI.getOperand(i).isReg() || !MI.getOperand(i).getReg().isVirtual()) continue; const TargetRegisterClass *OpRC = MRI.getRegClass(MI.getOperand(i).getReg()); @@ -5028,7 +5026,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI, // Update all the operands so they have the same type. for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { MachineOperand &Op = MI.getOperand(I); - if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) + if (!Op.isReg() || !Op.getReg().isVirtual()) continue; // MI is a PHI instruction. @@ -5053,7 +5051,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI, // subregister index types e.g. sub0_sub1 + sub2 + sub3 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { MachineOperand &Op = MI.getOperand(I); - if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) + if (!Op.isReg() || !Op.getReg().isVirtual()) continue; const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); @@ -5573,7 +5571,7 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst, unsigned NewDstReg = AMDGPU::NoRegister; if (HasDst) { Register DstReg = Inst.getOperand(0).getReg(); - if (Register::isPhysicalRegister(DstReg)) + if (DstReg.isPhysical()) continue; // Update the destination register class. @@ -5581,8 +5579,7 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst, if (!NewDstRC) continue; - if (Inst.isCopy() && - Register::isVirtualRegister(Inst.getOperand(1).getReg()) && + if (Inst.isCopy() && Inst.getOperand(1).getReg().isVirtual() && NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { // Instead of creating a copy where src and dst are the same register // class, we just replace all uses of dst with src. These kinds of @@ -7073,7 +7070,7 @@ static bool followSubRegDef(MachineInstr &MI, MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI) { assert(MRI.isSSA()); - if (!Register::isVirtualRegister(P.Reg)) + if (!P.Reg.isVirtual()) return nullptr; auto RSR = P; @@ -7084,7 +7081,7 @@ MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, case AMDGPU::COPY: case AMDGPU::V_MOV_B32_e32: { auto &Op1 = MI->getOperand(1); - if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg())) { + if (Op1.isReg() && Op1.getReg().isVirtual()) { if (Op1.isUndef()) return nullptr; RSR = getRegSubRegPair(Op1); diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 110d824..3d612d56a9 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -171,7 +171,7 @@ class SILoadStoreOptimizer : public MachineFunctionPass { return false; // TODO: We should be able to merge physical reg addreses. - if (Register::isPhysicalRegister(AddrOp->getReg())) + if (AddrOp->getReg().isPhysical()) return false; // If an address has only one use then there will be on other @@ -604,7 +604,7 @@ static void addDefsUsesToList(const MachineInstr &MI, if (Op.isReg()) { if (Op.isDef()) RegDefs.insert(Op.getReg()); - else if (Op.readsReg() && Register::isPhysicalRegister(Op.getReg())) + else if (Op.readsReg() && Op.getReg().isPhysical()) PhysRegUses.insert(Op.getReg()); } } @@ -633,11 +633,10 @@ static bool addToListsIfDependent(MachineInstr &MI, DenseSet &RegDefs, // be moved for merging, then we need to move the def-instruction as well. // This can only happen for physical registers such as M0; virtual // registers are in SSA form. - if (Use.isReg() && - ((Use.readsReg() && RegDefs.count(Use.getReg())) || - (Use.isDef() && RegDefs.count(Use.getReg())) || - (Use.isDef() && Register::isPhysicalRegister(Use.getReg()) && - PhysRegUses.count(Use.getReg())))) { + if (Use.isReg() && ((Use.readsReg() && RegDefs.count(Use.getReg())) || + (Use.isDef() && RegDefs.count(Use.getReg())) || + (Use.isDef() && Use.getReg().isPhysical() && + PhysRegUses.count(Use.getReg())))) { Insts.push_back(&MI); addDefsUsesToList(MI, RegDefs, PhysRegUses); return true; diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 140e1f0..8bb918f 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -541,7 +541,7 @@ void SILowerControlFlow::emitEndCf(MachineInstr &MI) { void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo, SmallVectorImpl &Src) const { MachineOperand &Op = MI.getOperand(OpNo); - if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) { + if (!Op.isReg() || !Op.getReg().isVirtual()) { Src.push_back(Op); return; } @@ -561,7 +561,7 @@ void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo, for (const auto &SrcOp : Def->explicit_operands()) if (SrcOp.isReg() && SrcOp.isUse() && - (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec)) + (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec)) Src.push_back(SrcOp); } diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp index 236a24a..85b3b85 100644 --- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -89,16 +89,15 @@ private: void lowerCopiesFromI1(); void lowerPhis(); void lowerCopiesToI1(); - bool isConstantLaneMask(unsigned Reg, bool &Val) const; + bool isConstantLaneMask(Register Reg, bool &Val) const; void buildMergeLaneMasks(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, unsigned PrevReg, unsigned CurReg); MachineBasicBlock::iterator getSaluInsertionAtEnd(MachineBasicBlock &MBB) const; - bool isVreg1(unsigned Reg) const { - return Register::isVirtualRegister(Reg) && - MRI->getRegClass(Reg) == &AMDGPU::VReg_1RegClass; + bool isVreg1(Register Reg) const { + return Reg.isVirtual() && MRI->getRegClass(Reg) == &AMDGPU::VReg_1RegClass; } bool isLaneMaskReg(unsigned Reg) const { @@ -703,8 +702,7 @@ void SILowerI1Copies::lowerCopiesToI1() { Register SrcReg = MI.getOperand(1).getReg(); assert(!MI.getOperand(1).getSubReg()); - if (!Register::isVirtualRegister(SrcReg) || - (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) { + if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) { assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); unsigned TmpReg = createLaneMaskReg(*MF); BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) @@ -740,7 +738,7 @@ void SILowerI1Copies::lowerCopiesToI1() { } } -bool SILowerI1Copies::isConstantLaneMask(unsigned Reg, bool &Val) const { +bool SILowerI1Copies::isConstantLaneMask(Register Reg, bool &Val) const { const MachineInstr *MI; for (;;) { MI = MRI->getUniqueVRegDef(Reg); @@ -748,7 +746,7 @@ bool SILowerI1Copies::isConstantLaneMask(unsigned Reg, bool &Val) const { break; Reg = MI->getOperand(1).getReg(); - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return false; if (!isLaneMaskReg(Reg)) return false; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 3ba05aa..a8b6076 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -375,8 +375,8 @@ void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock, // Comparing to LiveInRegs is not sufficient to differenciate 4 vs 5, 7 // The use of findDefBetween removes the case 4. for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) { - unsigned Reg = RegMaskPair.RegUnit; - if (Register::isVirtualRegister(Reg) && + Register Reg = RegMaskPair.RegUnit; + if (Reg.isVirtual() && isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(), LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI, LIS)) { @@ -1682,9 +1682,9 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() { // Tracking of currently alive registers to determine VGPR Usage. void SIScheduleBlockScheduler::addLiveRegs(std::set &Regs) { - for (unsigned Reg : Regs) { + for (Register Reg : Regs) { // For now only track virtual registers. - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) continue; // If not already in the live set, then add it. (void) LiveRegs.insert(Reg); @@ -1742,9 +1742,9 @@ SIScheduleBlockScheduler::checkRegUsageImpact(std::set &InRegs, std::vector DiffSetPressure; DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0); - for (unsigned Reg : InRegs) { + for (Register Reg : InRegs) { // For now only track virtual registers. - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) continue; if (LiveRegsConsumers[Reg] > 1) continue; @@ -1754,9 +1754,9 @@ SIScheduleBlockScheduler::checkRegUsageImpact(std::set &InRegs, } } - for (unsigned Reg : OutRegs) { + for (Register Reg : OutRegs) { // For now only track virtual registers. - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) continue; PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); for (; PSetI.isValid(); ++PSetI) { @@ -1902,9 +1902,9 @@ SIScheduleDAGMI::fillVgprSgprCost(_Iterator First, _Iterator End, VgprUsage = 0; SgprUsage = 0; for (_Iterator RegI = First; RegI != End; ++RegI) { - unsigned Reg = *RegI; + Register Reg = *RegI; // For now only track virtual registers - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) continue; PSetIterator PSetI = MRI.getPressureSets(Reg); for (; PSetI.isValid(); ++PSetI) { diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index 74546be..65f85ee 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -212,7 +212,7 @@ static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB, // Try to remove compare. Cmp value should not used in between of cmp // and s_and_b64 if VCC or just unused if any other register. - if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) || + if ((CmpReg.isVirtual() && MRI.use_nodbg_empty(CmpReg)) || (CmpReg == CondReg && std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(), [&](const MachineInstr &MI) { @@ -224,7 +224,7 @@ static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB, Cmp->eraseFromParent(); // Try to remove v_cndmask_b32. - if (Register::isVirtualRegister(SelReg) && MRI.use_nodbg_empty(SelReg)) { + if (SelReg.isVirtual() && MRI.use_nodbg_empty(SelReg)) { LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n'); LIS->RemoveMachineInstrFromMaps(*Sel); @@ -246,7 +246,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); LiveIntervals *LIS = &getAnalysis(); - DenseSet RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI}); + DenseSet RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI}); unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; bool Changed = false; @@ -352,7 +352,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { if (Changed) { for (auto Reg : RecalcRegs) { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { LIS->removeInterval(Reg); if (!MRI.reg_empty(Reg)) LIS->createAndComputeVirtRegInterval(Reg); diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 4774041..a1d3a3a 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -570,8 +570,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (Register::isPhysicalRegister(Src1->getReg()) || - Register::isPhysicalRegister(Dst->getReg())) + if (Src1->getReg().isPhysical() || Dst->getReg().isPhysical()) break; if (Opcode == AMDGPU::V_LSHLREV_B32_e32 || @@ -609,8 +608,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (Register::isPhysicalRegister(Src1->getReg()) || - Register::isPhysicalRegister(Dst->getReg())) + if (Src1->getReg().isPhysical() || Dst->getReg().isPhysical()) break; if (Opcode == AMDGPU::V_LSHLREV_B16_e32 || @@ -673,8 +671,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (Register::isPhysicalRegister(Src0->getReg()) || - Register::isPhysicalRegister(Dst->getReg())) + if (Src0->getReg().isPhysical() || Dst->getReg().isPhysical()) break; return std::make_unique( @@ -702,8 +699,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (Register::isPhysicalRegister(ValSrc->getReg()) || - Register::isPhysicalRegister(Dst->getReg())) + if (ValSrc->getReg().isPhysical() || Dst->getReg().isPhysical()) break; return std::make_unique( diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp index 09dfe87..b6e5235 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -96,7 +96,7 @@ bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) { if (!TRI->isVGPR(*MRI, Reg)) return false; - if (Register::isPhysicalRegister(Reg)) + if (Reg.isPhysical()) return false; if (VRM->hasPhys(Reg)) @@ -126,7 +126,7 @@ void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) { continue; const Register VirtReg = MO.getReg(); - if (Register::isPhysicalRegister(VirtReg)) + if (VirtReg.isPhysical()) continue; if (!VRM->hasPhys(VirtReg)) diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 8fd7b1a..9548c0f 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -78,7 +78,7 @@ static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, MachineOperand &Src0 = MI.getOperand(Src0Idx); if (Src0.isReg()) { Register Reg = Src0.getReg(); - if (Register::isVirtualRegister(Reg) && MRI.hasOneUse(Reg)) { + if (Reg.isVirtual() && MRI.hasOneUse(Reg)) { MachineInstr *Def = MRI.getUniqueVRegDef(Reg); if (Def && Def->isMoveImmediate()) { MachineOperand &MovSrc = Def->getOperand(1); @@ -367,7 +367,7 @@ static bool shrinkScalarLogicOp(const GCNSubtarget &ST, } if (NewImm != 0) { - if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) { + if (Dest->getReg().isVirtual() && SrcReg->isReg()) { MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); return true; @@ -397,17 +397,16 @@ static bool shrinkScalarLogicOp(const GCNSubtarget &ST, // This is the same as MachineInstr::readsRegister/modifiesRegister except // it takes subregs into account. static bool instAccessReg(iterator_range &&R, - unsigned Reg, unsigned SubReg, + Register Reg, unsigned SubReg, const SIRegisterInfo &TRI) { for (const MachineOperand &MO : R) { if (!MO.isReg()) continue; - if (Register::isPhysicalRegister(Reg) && - Register::isPhysicalRegister(MO.getReg())) { + if (Reg.isPhysical() && MO.getReg().isPhysical()) { if (TRI.regsOverlap(Reg, MO.getReg())) return true; - } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) { + } else if (MO.getReg() == Reg && Reg.isVirtual()) { LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) & TRI.getSubRegIndexLaneMask(MO.getSubReg()); if (Overlap.any()) @@ -430,10 +429,10 @@ static bool instModifiesReg(const MachineInstr *MI, } static TargetInstrInfo::RegSubRegPair -getSubRegForIndex(unsigned Reg, unsigned Sub, unsigned I, +getSubRegForIndex(Register Reg, unsigned Sub, unsigned I, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) { if (TRI.getRegSizeInBits(Reg, MRI) != 32) { - if (Register::isPhysicalRegister(Reg)) { + if (Reg.isPhysical()) { Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); } else { Sub = TRI.getSubRegFromChannel(I + TRI.getChannelFromSubReg(Sub)); @@ -589,8 +588,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { // optimizations happen because this will confuse them. // XXX - not exactly a check for post-regalloc run. MachineOperand &Src = MI.getOperand(1); - if (Src.isImm() && - Register::isPhysicalRegister(MI.getOperand(0).getReg())) { + if (Src.isImm() && MI.getOperand(0).getReg().isPhysical()) { int32_t ReverseImm; if (isReverseInlineImm(TII, Src, ReverseImm)) { MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); @@ -656,7 +654,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { // FIXME: This could work better if hints worked with subregisters. If // we have a vector add of a constant, we usually don't get the correct // allocation due to the subregister usage. - if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) { + if (Dest->getReg().isVirtual() && Src0->isReg()) { MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); continue; @@ -684,7 +682,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { const MachineOperand &Dst = MI.getOperand(0); MachineOperand &Src = MI.getOperand(1); - if (Src.isImm() && Register::isPhysicalRegister(Dst.getReg())) { + if (Src.isImm() && Dst.getReg().isPhysical()) { int32_t ReverseImm; if (isKImmOperand(TII, Src)) MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); @@ -733,7 +731,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { if (TII->isVOPC(Op32)) { Register DstReg = MI.getOperand(0).getReg(); - if (Register::isVirtualRegister(DstReg)) { + if (DstReg.isVirtual()) { // VOPC instructions can only write to the VCC register. We can't // force them to use VCC here, because this is only one register and // cannot deal with sequences which would require multiple copies of @@ -757,7 +755,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { if (!Src2->isReg()) continue; Register SReg = Src2->getReg(); - if (Register::isVirtualRegister(SReg)) { + if (SReg.isVirtual()) { MRI.setRegAllocationHint(SReg, 0, VCCReg); continue; } @@ -777,7 +775,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { bool Next = false; if (SDst->getReg() != VCCReg) { - if (Register::isVirtualRegister(SDst->getReg())) + if (SDst->getReg().isVirtual()) MRI.setRegAllocationHint(SDst->getReg(), 0, VCCReg); Next = true; } @@ -785,7 +783,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { // All of the instructions with carry outs also have an SGPR input in // src2. if (Src2 && Src2->getReg() != VCCReg) { - if (Register::isVirtualRegister(Src2->getReg())) + if (Src2->getReg().isVirtual()) MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg); Next = true; } diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index b1c73df..852accd 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -279,7 +279,7 @@ void SIWholeQuadMode::markInstructionUses(const MachineInstr &MI, char Flag, // Handle physical registers that we need to track; this is mostly relevant // for VCC, which can appear as the (implicit) input of a uniform branch, // e.g. when a loop counter is stored in a VGPR. - if (!Register::isVirtualRegister(Reg)) { + if (!Reg.isVirtual()) { if (Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO) continue; @@ -363,7 +363,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF, LowerToCopyInstrs.push_back(&MI); } else { Register Reg = Inactive.getReg(); - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { for (MachineInstr &DefMI : MRI->def_instructions(Reg)) markInstruction(DefMI, StateWWM, Worklist); } @@ -393,7 +393,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF, Register Reg = MO.getReg(); - if (!Register::isVirtualRegister(Reg) && + if (!Reg.isVirtual() && TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) { Flags = StateWQM; break; @@ -835,9 +835,8 @@ void SIWholeQuadMode::lowerCopyInstrs() { const Register Reg = MI->getOperand(0).getReg(); if (TRI->isVGPR(*MRI, Reg)) { - const TargetRegisterClass *regClass = Register::isVirtualRegister(Reg) - ? MRI->getRegClass(Reg) - : TRI->getPhysRegClass(Reg); + const TargetRegisterClass *regClass = + Reg.isVirtual() ? MRI->getRegClass(Reg) : TRI->getPhysRegClass(Reg); const unsigned MovOp = TII->getMovOpcode(regClass); MI->setDesc(TII->get(MovOp)); -- 2.7.4