From 342eca29749e3169cd9bb3ca0953519a41a7ca0f Mon Sep 17 00:00:00 2001
From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Tue, 25 Feb 2020 20:07:15 +0300
Subject: [PATCH] [NFC][Codegen] Add miscompile test for constant store merging
 from PR43446

This miscompile was introduced by rL354676 / https://reviews.llvm.org/D58468

https://bugs.llvm.org/show_bug.cgi?id=43446
---
 llvm/test/CodeGen/X86/stores-merging.ll | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/llvm/test/CodeGen/X86/stores-merging.ll b/llvm/test/CodeGen/X86/stores-merging.ll
index 25c93c3..5ef1d9f 100644
--- a/llvm/test/CodeGen/X86/stores-merging.ll
+++ b/llvm/test/CodeGen/X86/stores-merging.ll
@@ -219,3 +219,26 @@ define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #
   ret void
 }
 
+; These are miscompiles - we should store '1', not '-1'.
+; https://bugs.llvm.org/show_bug.cgi?id=43446
+define void @pr43446_0(i64 %x) {
+; CHECK-LABEL: pr43446_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movb $-1, (%rdi)
+; CHECK-NEXT:    retq
+  %a = inttoptr i64 %x to i8*
+  store i8 -2, i8* %a, align 1
+  %b = inttoptr i64 %x to i1*
+  store i1 true, i1* %b, align 1
+  ret void
+}
+define void @pr43446_1(i8* %a) {
+; CHECK-LABEL: pr43446_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movb $-1, (%rdi)
+; CHECK-NEXT:    retq
+  store i8 -2, i8* %a, align 1
+  %b = bitcast i8* %a to i1*
+  store i1 true, i1* %b, align 1
+  ret void
+}
-- 
2.7.4