From 33deff4f0582d2c073d34d4d6ec8344d2b1fbf7d Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 21 Jul 2015 18:42:27 +0300 Subject: [PATCH] i965/fs: Define logical texture sampling opcodes. Each logical variant is largely equivalent to the original opcode but instead of taking a single payload source it expects the arguments separately as individual sources, like: tex_logical dst, coordinates, shadow_c, lod, lod2, sample_index, mcs, sampler, offset, num_coordinate_components, num_grad_components This patch defines the opcodes and usual instruction boilerplate, including a placeholder lowering function provided mostly as documentation for their source registers. Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_defines.h | 31 +++++++++++ src/mesa/drivers/dri/i965/brw_fs.cpp | 92 ++++++++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_shader.cpp | 25 +++++++++ 3 files changed, 148 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2af7413..373d6b8 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -903,18 +903,49 @@ enum opcode { SHADER_OPCODE_SIN, SHADER_OPCODE_COS, + /** + * Texture sampling opcodes. + * + * LOGICAL opcodes are eventually translated to the matching non-LOGICAL + * opcode but instead of taking a single payload blob they expect their + * arguments separately as individual sources: + * + * Source 0: [optional] Texture coordinates. + * Source 1: [optional] Shadow comparitor. + * Source 2: [optional] dPdx if the operation takes explicit derivatives, + * otherwise LOD value. + * Source 3: [optional] dPdy if the operation takes explicit derivatives. + * Source 4: [optional] Sample index. + * Source 5: [optional] MCS data. + * Source 6: [required] Texture sampler. + * Source 7: [optional] Texel offset. + * Source 8: [required] Number of coordinate components (as UD immediate). + * Source 9: [required] Number derivative components (as UD immediate). + */ SHADER_OPCODE_TEX, + SHADER_OPCODE_TEX_LOGICAL, SHADER_OPCODE_TXD, + SHADER_OPCODE_TXD_LOGICAL, SHADER_OPCODE_TXF, + SHADER_OPCODE_TXF_LOGICAL, SHADER_OPCODE_TXL, + SHADER_OPCODE_TXL_LOGICAL, SHADER_OPCODE_TXS, + SHADER_OPCODE_TXS_LOGICAL, FS_OPCODE_TXB, + FS_OPCODE_TXB_LOGICAL, SHADER_OPCODE_TXF_CMS, + SHADER_OPCODE_TXF_CMS_LOGICAL, SHADER_OPCODE_TXF_UMS, + SHADER_OPCODE_TXF_UMS_LOGICAL, SHADER_OPCODE_TXF_MCS, + SHADER_OPCODE_TXF_MCS_LOGICAL, SHADER_OPCODE_LOD, + SHADER_OPCODE_LOD_LOGICAL, SHADER_OPCODE_TG4, + SHADER_OPCODE_TG4_LOGICAL, SHADER_OPCODE_TG4_OFFSET, + SHADER_OPCODE_TG4_OFFSET_LOGICAL, /** * Combines multiple sources of size 1 into a larger virtual GRF. diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 936f0d19..d9096f1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -686,6 +686,31 @@ fs_inst::components_read(unsigned i) const else return 1; + case SHADER_OPCODE_TEX_LOGICAL: + case SHADER_OPCODE_TXD_LOGICAL: + case SHADER_OPCODE_TXF_LOGICAL: + case SHADER_OPCODE_TXL_LOGICAL: + case SHADER_OPCODE_TXS_LOGICAL: + case FS_OPCODE_TXB_LOGICAL: + case SHADER_OPCODE_TXF_CMS_LOGICAL: + case SHADER_OPCODE_TXF_UMS_LOGICAL: + case SHADER_OPCODE_TXF_MCS_LOGICAL: + case SHADER_OPCODE_LOD_LOGICAL: + case SHADER_OPCODE_TG4_LOGICAL: + case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + assert(src[8].file == IMM && src[9].file == IMM); + /* Texture coordinates. */ + if (i == 0) + return src[8].fixed_hw_reg.dw1.ud; + /* Texture derivatives. */ + else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL) + return src[9].fixed_hw_reg.dw1.ud; + /* Texture offset. */ + else if (i == 7) + return 2; + else + return 1; + default: return 1; } @@ -3361,6 +3386,25 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, inst->header_size = header_size; } +static void +lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) +{ + const brw_device_info *devinfo = bld.shader->devinfo; + const fs_reg &coordinate = inst->src[0]; + const fs_reg &shadow_c = inst->src[1]; + const fs_reg &lod = inst->src[2]; + const fs_reg &lod2 = inst->src[3]; + const fs_reg &sample_index = inst->src[4]; + const fs_reg &mcs = inst->src[5]; + const fs_reg &sampler = inst->src[6]; + const fs_reg &offset_value = inst->src[7]; + assert(inst->src[8].file == IMM && inst->src[9].file == IMM); + const unsigned coord_components = inst->src[8].fixed_hw_reg.dw1.ud; + const unsigned grad_components = inst->src[9].fixed_hw_reg.dw1.ud; + + assert(!"Not implemented"); +} + bool fs_visitor::lower_logical_sends() { @@ -3380,6 +3424,54 @@ fs_visitor::lower_logical_sends() payload); break; + case SHADER_OPCODE_TEX_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TEX); + break; + + case SHADER_OPCODE_TXD_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXD); + break; + + case SHADER_OPCODE_TXF_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF); + break; + + case SHADER_OPCODE_TXL_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXL); + break; + + case SHADER_OPCODE_TXS_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXS); + break; + + case FS_OPCODE_TXB_LOGICAL: + lower_sampler_logical_send(ibld, inst, FS_OPCODE_TXB); + break; + + case SHADER_OPCODE_TXF_CMS_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS); + break; + + case SHADER_OPCODE_TXF_UMS_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_UMS); + break; + + case SHADER_OPCODE_TXF_MCS_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_MCS); + break; + + case SHADER_OPCODE_LOD_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_LOD); + break; + + case SHADER_OPCODE_TG4_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4); + break; + + case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET); + break; + default: continue; } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 1e660d7..9e3a974 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -567,28 +567,53 @@ brw_instruction_name(enum opcode op) case SHADER_OPCODE_TEX: return "tex"; + case SHADER_OPCODE_TEX_LOGICAL: + return "tex_logical"; case SHADER_OPCODE_TXD: return "txd"; + case SHADER_OPCODE_TXD_LOGICAL: + return "txd_logical"; case SHADER_OPCODE_TXF: return "txf"; + case SHADER_OPCODE_TXF_LOGICAL: + return "txf_logical"; case SHADER_OPCODE_TXL: return "txl"; + case SHADER_OPCODE_TXL_LOGICAL: + return "txl_logical"; case SHADER_OPCODE_TXS: return "txs"; + case SHADER_OPCODE_TXS_LOGICAL: + return "txs_logical"; case FS_OPCODE_TXB: return "txb"; + case FS_OPCODE_TXB_LOGICAL: + return "txb_logical"; case SHADER_OPCODE_TXF_CMS: return "txf_cms"; + case SHADER_OPCODE_TXF_CMS_LOGICAL: + return "txf_cms_logical"; case SHADER_OPCODE_TXF_UMS: return "txf_ums"; + case SHADER_OPCODE_TXF_UMS_LOGICAL: + return "txf_ums_logical"; case SHADER_OPCODE_TXF_MCS: return "txf_mcs"; + case SHADER_OPCODE_TXF_MCS_LOGICAL: + return "txf_mcs_logical"; case SHADER_OPCODE_LOD: return "lod"; + case SHADER_OPCODE_LOD_LOGICAL: + return "lod_logical"; case SHADER_OPCODE_TG4: return "tg4"; + case SHADER_OPCODE_TG4_LOGICAL: + return "tg4_logical"; case SHADER_OPCODE_TG4_OFFSET: return "tg4_offset"; + case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + return "tg4_offset_logical"; + case SHADER_OPCODE_SHADER_TIME_ADD: return "shader_time_add"; -- 2.7.4