From 33dda45dde678f6f2efa24d7ca837cd6ad8f44d7 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Sat, 15 Oct 2022 08:04:00 +0900 Subject: [PATCH] [VE] Change the way to lower selectcc Change to use VEISD::CMPI/CMPU/CMPF/CMPQ and VEISD::CMOV in combineSelectCC for better optimization. Support VEISD::CMPI/CMPU in combineTRUNCATE also to optimize truncate. Remove obsolete lower patterns from VEInstrInfo.td. Update regression tests also. Reviewed By: efocht Differential Revision: https://reviews.llvm.org/D136049 --- llvm/lib/Target/VE/VEISelLowering.cpp | 152 +++++++++++++++++ llvm/lib/Target/VE/VEISelLowering.h | 5 + llvm/lib/Target/VE/VEInstrInfo.td | 152 ++--------------- llvm/test/CodeGen/VE/Scalar/atomic.ll | 26 ++- llvm/test/CodeGen/VE/Scalar/br_cc.ll | 46 ++--- llvm/test/CodeGen/VE/Scalar/brind.ll | 5 +- llvm/test/CodeGen/VE/Scalar/cast.ll | 15 +- llvm/test/CodeGen/VE/Scalar/ctlz.ll | 10 +- llvm/test/CodeGen/VE/Scalar/cttz.ll | 18 +- llvm/test/CodeGen/VE/Scalar/int_to_fp.ll | 15 +- llvm/test/CodeGen/VE/Scalar/select_cc.ll | 252 +++++++++++++--------------- llvm/test/CodeGen/VE/Scalar/selectccf32c.ll | 19 +-- llvm/test/CodeGen/VE/Scalar/selectccf32i.ll | 24 --- llvm/test/CodeGen/VE/Scalar/selectccf64c.ll | 19 +-- llvm/test/CodeGen/VE/Scalar/selectccf64i.ll | 24 --- llvm/test/CodeGen/VE/Scalar/selectcci32.ll | 12 +- llvm/test/CodeGen/VE/Scalar/selectcci32c.ll | 19 +-- llvm/test/CodeGen/VE/Scalar/selectcci32i.ll | 66 +++----- llvm/test/CodeGen/VE/Scalar/selectcci64.ll | 4 +- llvm/test/CodeGen/VE/Scalar/selectcci64c.ll | 19 +-- llvm/test/CodeGen/VE/Scalar/selectcci64i.ll | 66 +++----- llvm/test/CodeGen/VE/Scalar/smax.ll | 45 +++-- llvm/test/CodeGen/VE/Scalar/smin.ll | 47 +++--- llvm/test/CodeGen/VE/Scalar/umax.ll | 53 +++--- llvm/test/CodeGen/VE/Scalar/umin.ll | 49 ++---- 25 files changed, 522 insertions(+), 640 deletions(-) diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index 4fe6aff..bf0e191 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -915,6 +915,7 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM, // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::TRUNCATE); setTargetDAGCombine(ISD::SELECT); + setTargetDAGCombine(ISD::SELECT_CC); // Set function alignment to 16 bytes setMinFunctionAlignment(Align(16)); @@ -932,6 +933,10 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((VEISD::NodeType)Opcode) { case VEISD::FIRST_NUMBER: break; + TARGET_NODE_CASE(CMPI) + TARGET_NODE_CASE(CMPU) + TARGET_NODE_CASE(CMPF) + TARGET_NODE_CASE(CMPQ) TARGET_NODE_CASE(CMOV) TARGET_NODE_CASE(CALL) TARGET_NODE_CASE(EH_SJLJ_LONGJMP) @@ -2687,6 +2692,28 @@ VETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, } } +static bool isSimm7(SDValue V) { + EVT VT = V.getValueType(); + if (VT.isVector()) + return false; + + if (VT.isInteger()) { + if (ConstantSDNode *C = dyn_cast(V)) + return isInt<7>(C->getSExtValue()); + } else if (VT.isFloatingPoint()) { + if (ConstantFPSDNode *C = dyn_cast(V)) { + if (VT == MVT::f32 || VT == MVT::f64) { + const APInt &Imm = C->getValueAPF().bitcastToAPInt(); + uint64_t Val = Imm.getSExtValue(); + if (Imm.getBitWidth() == 32) + Val <<= 32; // Immediate value of float place at higher bits on VE. + return isInt<7>(Val); + } + } + } + return false; +} + static bool isMImm(SDValue V) { EVT VT = V.getValueType(); if (VT.isVector()) @@ -2708,6 +2735,59 @@ static bool isMImm(SDValue V) { return false; } +static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) { + if (SrcVT.isFloatingPoint()) { + if (SrcVT == MVT::f128) + return VEISD::CMPQ; + return VEISD::CMPF; + } + return isSignedIntSetCC(CC) ? VEISD::CMPI : VEISD::CMPU; +} + +static EVT decideCompType(EVT SrcVT) { + if (SrcVT == MVT::f128) + return MVT::f64; + return SrcVT; +} + +static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, + bool WithCMov) { + if (SrcVT.isFloatingPoint()) { + // For the case of floating point setcc, only unordered comparison + // or general comparison with -enable-no-nans-fp-math option reach + // here, so it is safe even if values are NaN. Only f128 doesn't + // safe since VE uses f64 result of f128 comparison. + return SrcVT != MVT::f128; + } + if (isIntEqualitySetCC(CC)) { + // For the case of equal or not equal, it is safe without comparison with 0. + return true; + } + if (WithCMov) { + // For the case of integer setcc with cmov, all signed comparison with 0 + // are safe. + return isSignedIntSetCC(CC); + } + // For the case of integer setcc, only signed 64 bits comparison is safe. + // For unsigned, "CMPU 0x80000000, 0" has to be greater than 0, but it becomes + // less than 0 witout CMPU. For 32 bits, other half of 32 bits are + // uncoditional, so it is not safe too without CMPI.. + return isSignedIntSetCC(CC) && SrcVT == MVT::i64; +} + +static SDValue generateComparison(EVT VT, SDValue LHS, SDValue RHS, + ISD::CondCode CC, bool WithCMov, + const SDLoc &DL, SelectionDAG &DAG) { + // Compare values. If RHS is 0 and it is safe to calculate without + // comparison, we don't generate an instruction for comparison. + EVT CompVT = decideCompType(VT); + if (CompVT == VT && safeWithoutCompWithNull(VT, CC, WithCMov) && + (isNullConstant(RHS) || isNullFPConstant(RHS))) { + return LHS; + } + return DAG.getNode(decideComp(VT, CC), DL, CompVT, LHS, RHS); +} + SDValue VETargetLowering::combineSelect(SDNode *N, DAGCombinerInfo &DCI) const { assert(N->getOpcode() == ISD::SELECT && @@ -2749,6 +2829,74 @@ SDValue VETargetLowering::combineSelect(SDNode *N, return DAG.getNode(VEISD::CMOV, DL, VT, Ops); } +SDValue VETargetLowering::combineSelectCC(SDNode *N, + DAGCombinerInfo &DCI) const { + assert(N->getOpcode() == ISD::SELECT_CC && + "Should be called with a SELECT_CC node"); + ISD::CondCode CC = cast(N->getOperand(4))->get(); + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + SDValue True = N->getOperand(2); + SDValue False = N->getOperand(3); + + // We handle only scalar SELECT_CC. + EVT VT = N->getValueType(0); + if (VT.isVector()) + return SDValue(); + + // Peform combineSelectCC after leagalize DAG. + if (!DCI.isAfterLegalizeDAG()) + return SDValue(); + + // We handle only i32/i64/f32/f64/f128 comparisons. + EVT LHSVT = LHS.getValueType(); + assert(LHSVT == RHS.getValueType()); + switch (LHSVT.getSimpleVT().SimpleTy) { + case MVT::i32: + case MVT::i64: + case MVT::f32: + case MVT::f64: + case MVT::f128: + break; + default: + // Return SDValue to let llvm handle other types. + return SDValue(); + } + + if (isMImm(RHS)) { + // VE's comparison can handle MImm in RHS, so nothing to do. + } else if (isSimm7(RHS)) { + // VE's comparison can handle Simm7 in LHS, so swap LHS and RHS, and + // update condition code. + std::swap(LHS, RHS); + CC = getSetCCSwappedOperands(CC); + } + if (isMImm(True)) { + // VE's condition move can handle MImm in True clause, so nothing to do. + } else if (isMImm(False)) { + // VE's condition move can handle MImm in True clause, so swap True and + // False clauses if False has MImm value. And, update condition code. + std::swap(True, False); + CC = getSetCCInverse(CC, LHSVT); + } + + SDLoc DL(N); + SelectionDAG &DAG = DCI.DAG; + + bool WithCMov = true; + SDValue CompNode = generateComparison(LHSVT, LHS, RHS, CC, WithCMov, DL, DAG); + + VECC::CondCode VECCVal; + if (LHSVT.isFloatingPoint()) { + VECCVal = fpCondCode2Fcc(CC); + } else { + VECCVal = intCondCode2Icc(CC); + } + SDValue Ops[] = {CompNode, True, False, + DAG.getConstant(VECCVal, DL, MVT::i32)}; + return DAG.getNode(VEISD::CMOV, DL, VT, Ops); +} + static bool isI32InsnAllUses(const SDNode *User, const SDNode *N); static bool isI32Insn(const SDNode *User, const SDNode *N) { switch (User->getOpcode()) { @@ -2771,6 +2919,8 @@ static bool isI32Insn(const SDNode *User, const SDNode *N) { case ISD::BITCAST: case ISD::ATOMIC_CMP_SWAP: case ISD::ATOMIC_SWAP: + case VEISD::CMPU: + case VEISD::CMPI: return true; case ISD::SRL: if (N->getOperand(0).getOpcode() != ISD::SRL) @@ -2885,6 +3035,8 @@ SDValue VETargetLowering::PerformDAGCombine(SDNode *N, break; case ISD::SELECT: return combineSelect(N, DCI); + case ISD::SELECT_CC: + return combineSelectCC(N, DCI); case ISD::TRUNCATE: return combineTRUNCATE(N, DCI); } diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h index 6b8c37d..e4626a5 100644 --- a/llvm/lib/Target/VE/VEISelLowering.h +++ b/llvm/lib/Target/VE/VEISelLowering.h @@ -24,6 +24,10 @@ namespace VEISD { enum NodeType : unsigned { FIRST_NUMBER = ISD::BUILTIN_OP_END, + CMPI, // Compare between two signed integer values. + CMPU, // Compare between two unsigned integer values. + CMPF, // Compare between two floating-point values. + CMPQ, // Compare between two quad floating-point values. CMOV, // Select between two values using the result of comparison. CALL, // A call instruction. @@ -203,6 +207,7 @@ public: SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const; SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; /// } Custom DAGCombine diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 83c4fb1..e1b075e 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -446,6 +446,14 @@ def retflag : SDNode<"VEISD::RET_FLAG", SDTNone, def getGOT : Operand; +// Comparisons +def cmpi : SDNode<"VEISD::CMPI", SDTIntBinOp>; +def cmpu : SDNode<"VEISD::CMPU", SDTIntBinOp>; +def cmpf : SDNode<"VEISD::CMPF", SDTFPBinOp>; +def SDT_Cmpq : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisFP<0>, + SDTCisFP<2>]>; +def cmpq : SDNode<"VEISD::CMPQ", SDT_Cmpq>; + // res = cmov cmp, t, f, cond def SDT_Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, i32>]>; @@ -1240,15 +1248,15 @@ defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>; let isReMaterializable = 1, isAsCheapAsAMove = 1 in { // Section 8.4.14 - CMP (Compare) -defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>; -let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>; +defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64, cmpu>; +let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32, cmpu>; // Section 8.4.15 - CPS (Compare Single) defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>; -let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32>; +let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32, cmpi>; // Section 8.4.16 - CPX (Compare) -defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64>; +defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64, cmpi>; // Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single) // cx: sx/zx, cw: max/min @@ -1405,9 +1413,9 @@ let cx = 1 in defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>; // Section 8.7.5 - FCP (Floating Compare) -defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64>; +defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64, cmpf>; let cx = 1 in -defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, null_frag, simm7fp, mimmfp32>; +defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, cmpf, simm7fp, mimmfp32>; // Section 8.7.6 - CMS (Compare and Select Maximum/Minimum Single) // cx: double/float, cw: max/min @@ -1430,7 +1438,7 @@ defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128, fsub>; defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128, fmul>; // Section 8.7.10 - FCQ (Floating Compare Quadruple) -defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp, +defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, cmpq, simm7fp, mimmfp>; // Section 8.7.11 - FIX (Convert to Fixed Point) @@ -2073,136 +2081,6 @@ def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)), def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)), (setccrr (fcond2cc $cond), (FCMPQrr $l, $r))>; -// Helper classes to construct cmov patterns for the ease. -// -// Hiding INSERT_SUBREG/EXTRACT_SUBREG patterns. - -class cmovrr : - OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), - (INSN $cond, $comp, $t, $f)>; -class cmovrm : - OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), - (INSN $cond, $comp, (MOP $t), $f)>; -class cmov32rr : - OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), - (EXTRACT_SUBREG - (INSN $cond, $comp, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_oty), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)), - sub_oty)>; -class cmov32rm : - OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), - (EXTRACT_SUBREG - (INSN $cond, $comp, - (MOP $t), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)), - sub_oty)>; -class cmov128rr : - OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), - (INSERT_SUBREG - (INSERT_SUBREG (f128 (IMPLICIT_DEF)), - (INSN $cond, $comp, - (EXTRACT_SUBREG $t, sub_odd), - (EXTRACT_SUBREG $f, sub_odd)), sub_odd), - (INSN $cond, $comp, - (EXTRACT_SUBREG $t, sub_even), - (EXTRACT_SUBREG $f, sub_even)), sub_even)>; - -// Generic SELECTCC pattern matches -// -// CMP %tmp, %l, %r ; compare %l and %r -// or %res, %f, (0)1 ; initialize by %f -// CMOV %res, %t, %tmp ; set %t if %tmp is true - -def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCSIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPSWSXrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCUIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPUWrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCSIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPSLrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCUIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPULrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc f32:$l, f32:$r, i32:$t, i32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPSrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc f64:$l, f64:$r, i32:$t, i32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPDrr $l, $r), - $t, $f)>; -def : Pat<(i32 (selectcc f128:$l, f128:$r, i32:$t, i32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPQrr $l, $r), - $t, $f)>; - -def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCSIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCUIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCSIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCUIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc f32:$l, f32:$r, i64:$t, i64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; -def : Pat<(i64 (selectcc f128:$l, f128:$r, i64:$t, i64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; - -def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCSIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPSWSXrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCUIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPUWrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCSIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPSLrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCUIOp:$cond)), - (cmov32rr (icond2cc $cond), (CMPULrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc f32:$l, f32:$r, f32:$t, f32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPSrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc f64:$l, f64:$r, f32:$t, f32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPDrr $l, $r), - $t, $f)>; -def : Pat<(f32 (selectcc f128:$l, f128:$r, f32:$t, f32:$f, cond:$cond)), - (cmov32rr (fcond2cc $cond), (FCMPQrr $l, $r), - $t, $f)>; - -def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCSIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCUIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCSIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCUIOp:$cond)), - (cmovrr (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc f32:$l, f32:$r, f64:$t, f64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; -def : Pat<(f64 (selectcc f128:$l, f128:$r, f64:$t, f64:$f, cond:$cond)), - (cmovrr (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; - -def : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCSIOp:$cond)), - (cmov128rr (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCUIOp:$cond)), - (cmov128rr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCSIOp:$cond)), - (cmov128rr (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCUIOp:$cond)), - (cmov128rr (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc f32:$l, f32:$r, f128:$t, f128:$f, cond:$cond)), - (cmov128rr (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc f64:$l, f64:$r, f128:$t, f128:$f, cond:$cond)), - (cmov128rr (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; -def : Pat<(f128 (selectcc f128:$l, f128:$r, f128:$t, f128:$f, cond:$cond)), - (cmov128rr (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; - // Generic CMOV pattern matches // CMOV accepts i64 $t, $f, and result. So, we extend it to support // i32/f32/f64/f128 $t, $f, and result. diff --git a/llvm/test/CodeGen/VE/Scalar/atomic.ll b/llvm/test/CodeGen/VE/Scalar/atomic.ll index 405cdc3..c1d8ffc 100644 --- a/llvm/test/CodeGen/VE/Scalar/atomic.ll +++ b/llvm/test/CodeGen/VE/Scalar/atomic.ll @@ -232,15 +232,14 @@ define signext i32 @test_atomic_fetch_umax_4() { ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, i@hi(, %s0) ; CHECK-NEXT: ldl.sx %s1, (, %s0) -; CHECK-NEXT: or %s2, 1, (0)1 ; CHECK-NEXT: .LBB8_1: # %atomicrmw.start ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: or %s3, 0, %s1 -; CHECK-NEXT: cmpu.w %s4, %s1, %s2 -; CHECK-NEXT: or %s1, 1, (0)1 -; CHECK-NEXT: cmov.w.gt %s1, %s3, %s4 -; CHECK-NEXT: cas.w %s1, (%s0), %s3 -; CHECK-NEXT: brne.w %s1, %s3, .LBB8_1 +; CHECK-NEXT: or %s2, 0, %s1 +; CHECK-NEXT: cmpu.w %s3, %s1, (63)0 +; CHECK-NEXT: or %s1, 0, %s2 +; CHECK-NEXT: cmov.w.le %s1, (63)0, %s3 +; CHECK-NEXT: cas.w %s1, (%s0), %s2 +; CHECK-NEXT: brne.w %s1, %s2, .LBB8_1 ; CHECK-NEXT: # %bb.2: # %atomicrmw.end ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: fencem 3 @@ -259,15 +258,14 @@ define signext i32 @test_atomic_fetch_umin_4() { ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, i@hi(, %s0) ; CHECK-NEXT: ldl.sx %s1, (, %s0) -; CHECK-NEXT: or %s2, 2, (0)1 ; CHECK-NEXT: .LBB9_1: # %atomicrmw.start ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: or %s3, 0, %s1 -; CHECK-NEXT: cmpu.w %s4, %s1, %s2 -; CHECK-NEXT: or %s1, 1, (0)1 -; CHECK-NEXT: cmov.w.lt %s1, %s3, %s4 -; CHECK-NEXT: cas.w %s1, (%s0), %s3 -; CHECK-NEXT: brne.w %s1, %s3, .LBB9_1 +; CHECK-NEXT: or %s2, 0, %s1 +; CHECK-NEXT: cmpu.w %s3, 2, %s1 +; CHECK-NEXT: or %s1, 0, %s2 +; CHECK-NEXT: cmov.w.le %s1, (63)0, %s3 +; CHECK-NEXT: cas.w %s1, (%s0), %s2 +; CHECK-NEXT: brne.w %s1, %s2, .LBB9_1 ; CHECK-NEXT: # %bb.2: # %atomicrmw.end ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: fencem 3 diff --git a/llvm/test/CodeGen/VE/Scalar/br_cc.ll b/llvm/test/CodeGen/VE/Scalar/br_cc.ll index a72b813..92cb941 100644 --- a/llvm/test/CodeGen/VE/Scalar/br_cc.ll +++ b/llvm/test/CodeGen/VE/Scalar/br_cc.ll @@ -522,13 +522,13 @@ define void @br_cc_i128_imm(i128 %0) { ; CHECK-LABEL: br_cc_i128_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s1, %s1, (0)1 -; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 +; CHECK-NEXT: cmps.l %s3, %s1, (0)1 +; CHECK-NEXT: or %s4, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s4, (63)0, %s3 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 -; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1 +; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop @@ -551,13 +551,13 @@ define void @br_cc_u128_imm(i128 %0) { ; CHECK-LABEL: br_cc_u128_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s1, %s1, (0)1 -; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1 +; CHECK-NEXT: cmps.l %s3, %s1, (0)1 +; CHECK-NEXT: or %s4, 0, (0)1 +; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s3 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 -; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1 +; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop @@ -853,14 +853,15 @@ define void @br_cc_imm_u64(i64 %0) { define void @br_cc_imm_i128(i128 %0) { ; CHECK-LABEL: br_cc_imm_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s1, %s1, (0)0 -; CHECK-NEXT: or %s2, 0, (0)1 +; CHECK-NEXT: cmps.l %s2, %s1, (0)0 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s1 +; CHECK-NEXT: or %s4, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 -; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 -; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 +; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 +; CHECK-NEXT: cmpu.l %s0, %s1, (0)0 +; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0 +; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop @@ -882,14 +883,15 @@ define void @br_cc_imm_i128(i128 %0) { define void @br_cc_imm_u128(i128 %0) { ; CHECK-LABEL: br_cc_imm_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s1, %s1, (0)0 -; CHECK-NEXT: or %s2, 0, (0)1 +; CHECK-NEXT: cmps.l %s2, %s1, (0)0 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1 +; CHECK-NEXT: or %s4, 0, (0)1 +; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 -; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 -; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 +; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 +; CHECK-NEXT: cmpu.l %s0, %s1, (0)0 +; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0 +; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: #APP ; CHECK-NEXT: nop diff --git a/llvm/test/CodeGen/VE/Scalar/brind.ll b/llvm/test/CodeGen/VE/Scalar/brind.ll index 7238da0..f114282 100644 --- a/llvm/test/CodeGen/VE/Scalar/brind.ll +++ b/llvm/test/CodeGen/VE/Scalar/brind.ll @@ -4,8 +4,7 @@ define signext i32 @brind(i32 signext %0) { ; CHECK-LABEL: brind: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 1, (0)1 -; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: cmpu.w %s1, %s0, (63)0 ; CHECK-NEXT: lea %s2, .Ltmp0@lo ; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: lea.sl %s2, .Ltmp0@hi(, %s2) @@ -13,8 +12,6 @@ define signext i32 @brind(i32 signext %0) { ; CHECK-NEXT: and %s3, %s3, (32)0 ; CHECK-NEXT: lea.sl %s3, .Ltmp1@hi(, %s3) ; CHECK-NEXT: cmov.w.eq %s2, %s3, %s1 -; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: lea %s1, .Ltmp2@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .Ltmp2@hi(, %s1) diff --git a/llvm/test/CodeGen/VE/Scalar/cast.ll b/llvm/test/CodeGen/VE/Scalar/cast.ll index eadd8cf..44782b3 100644 --- a/llvm/test/CodeGen/VE/Scalar/cast.ll +++ b/llvm/test/CodeGen/VE/Scalar/cast.ll @@ -553,16 +553,15 @@ define i64 @ull2ull(i64 returned %0) { define float @ull2f(i64 %x) { ; CHECK-LABEL: ull2f: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.s.d %s1, %s1 -; CHECK-NEXT: srl %s3, %s0, 1 -; CHECK-NEXT: and %s0, 1, %s0 -; CHECK-NEXT: or %s0, %s0, %s3 -; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: fadd.s %s0, %s0, %s0 -; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 +; CHECK-NEXT: srl %s2, %s0, 1 +; CHECK-NEXT: and %s3, 1, %s0 +; CHECK-NEXT: or %s2, %s3, %s2 +; CHECK-NEXT: cvt.d.l %s2, %s2 +; CHECK-NEXT: cvt.s.d %s2, %s2 +; CHECK-NEXT: fadd.s %s2, %s2, %s2 +; CHECK-NEXT: cmov.l.lt %s1, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %r = uitofp i64 %x to float diff --git a/llvm/test/CodeGen/VE/Scalar/ctlz.ll b/llvm/test/CodeGen/VE/Scalar/ctlz.ll index 08c13c6..57d1a35 100644 --- a/llvm/test/CodeGen/VE/Scalar/ctlz.ll +++ b/llvm/test/CodeGen/VE/Scalar/ctlz.ll @@ -9,11 +9,10 @@ declare i8 @llvm.ctlz.i8(i8, i1) define i128 @func128(i128 %p){ ; CHECK-LABEL: func128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s2, %s1, (0)1 -; CHECK-NEXT: ldz %s1, %s1 +; CHECK-NEXT: ldz %s2, %s1 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, 64(, %s0) -; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 +; CHECK-NEXT: cmov.l.ne %s0, %s2, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true) @@ -178,11 +177,10 @@ define zeroext i8 @func8iz() { define i128 @func128x(i128 %p){ ; CHECK-LABEL: func128x: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s2, %s1, (0)1 -; CHECK-NEXT: ldz %s1, %s1 +; CHECK-NEXT: ldz %s2, %s1 ; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: lea %s0, 64(, %s0) -; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 +; CHECK-NEXT: cmov.l.ne %s0, %s2, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false) diff --git a/llvm/test/CodeGen/VE/Scalar/cttz.ll b/llvm/test/CodeGen/VE/Scalar/cttz.ll index 85ee135..9badb44 100644 --- a/llvm/test/CodeGen/VE/Scalar/cttz.ll +++ b/llvm/test/CodeGen/VE/Scalar/cttz.ll @@ -9,16 +9,16 @@ declare i8 @llvm.cttz.i8(i8, i1) define i128 @func128(i128 %p) { ; CHECK-LABEL: func128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s2, %s0, (0)1 -; CHECK-NEXT: lea %s3, -1(, %s0) -; CHECK-NEXT: nnd %s0, %s0, %s3 -; CHECK-NEXT: pcnt %s3, %s0 -; CHECK-NEXT: lea %s0, -1(, %s1) -; CHECK-NEXT: nnd %s0, %s1, %s0 -; CHECK-NEXT: pcnt %s0, %s0 -; CHECK-NEXT: lea %s0, 64(, %s0) -; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2 +; CHECK-NEXT: lea %s2, -1(, %s0) +; CHECK-NEXT: nnd %s2, %s0, %s2 +; CHECK-NEXT: pcnt %s3, %s2 +; CHECK-NEXT: lea %s2, -1(, %s1) +; CHECK-NEXT: nnd %s1, %s1, %s2 +; CHECK-NEXT: pcnt %s1, %s1 +; CHECK-NEXT: lea %s2, 64(, %s1) +; CHECK-NEXT: cmov.l.ne %s2, %s3, %s0 ; CHECK-NEXT: or %s1, 0, (0)1 +; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) %r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true) ret i128 %r diff --git a/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll b/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll index 5d70e03..eaa001f 100644 --- a/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll +++ b/llvm/test/CodeGen/VE/Scalar/int_to_fp.ll @@ -84,16 +84,15 @@ entry: define float @ul2f(i64 %a) { ; CHECK-LABEL: ul2f: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.s.d %s1, %s1 -; CHECK-NEXT: srl %s3, %s0, 1 -; CHECK-NEXT: and %s0, 1, %s0 -; CHECK-NEXT: or %s0, %s0, %s3 -; CHECK-NEXT: cvt.d.l %s0, %s0 -; CHECK-NEXT: cvt.s.d %s0, %s0 -; CHECK-NEXT: fadd.s %s0, %s0, %s0 -; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 +; CHECK-NEXT: srl %s2, %s0, 1 +; CHECK-NEXT: and %s3, 1, %s0 +; CHECK-NEXT: or %s2, %s3, %s2 +; CHECK-NEXT: cvt.d.l %s2, %s2 +; CHECK-NEXT: cvt.s.d %s2, %s2 +; CHECK-NEXT: fadd.s %s2, %s2, %s2 +; CHECK-NEXT: cmov.l.lt %s1, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: b.l.t (, %s10) entry: diff --git a/llvm/test/CodeGen/VE/Scalar/select_cc.ll b/llvm/test/CodeGen/VE/Scalar/select_cc.ll index d8ea7f1..bad8df3 100644 --- a/llvm/test/CodeGen/VE/Scalar/select_cc.ll +++ b/llvm/test/CodeGen/VE/Scalar/select_cc.ll @@ -22,7 +22,7 @@ define zeroext i1 @select_cc_i1_i1(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2, define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i8_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -35,7 +35,7 @@ define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u8_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -48,7 +48,7 @@ define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i16_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -61,7 +61,7 @@ define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext % define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u16_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -74,7 +74,7 @@ define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext % define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i32_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -87,7 +87,7 @@ define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext % define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u32_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -100,7 +100,7 @@ define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext % define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_i64_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -113,7 +113,7 @@ define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3 define zeroext i1 @select_cc_u64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { ; CHECK-LABEL: select_cc_u64_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -129,7 +129,6 @@ define zeroext i1 @select_cc_i128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -145,7 +144,6 @@ define zeroext i1 @select_cc_u128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -210,7 +208,7 @@ define signext i8 @select_cc_i1_i8(i1 zeroext %0, i1 zeroext %1, i8 signext %2, define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i8_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -223,7 +221,7 @@ define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u8_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -236,7 +234,7 @@ define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i16_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -249,7 +247,7 @@ define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext % define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u16_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -262,7 +260,7 @@ define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext % define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i32_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -275,7 +273,7 @@ define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext % define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u32_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -288,7 +286,7 @@ define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext % define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_i64_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -301,7 +299,7 @@ define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3 define signext i8 @select_cc_u64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { ; CHECK-LABEL: select_cc_u64_i8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -317,7 +315,6 @@ define signext i8 @select_cc_i128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -333,7 +330,6 @@ define signext i8 @select_cc_u128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -398,7 +394,7 @@ define zeroext i8 @select_cc_i1_u8(i1 zeroext %0, i1 zeroext %1, i8 zeroext %2, define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -411,7 +407,7 @@ define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -424,7 +420,7 @@ define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -437,7 +433,7 @@ define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext % define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -450,7 +446,7 @@ define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext % define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -463,7 +459,7 @@ define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext % define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -476,7 +472,7 @@ define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext % define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -489,7 +485,7 @@ define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3 define zeroext i8 @select_cc_u64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u8: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -505,7 +501,6 @@ define zeroext i8 @select_cc_i128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -521,7 +516,6 @@ define zeroext i8 @select_cc_u128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -586,7 +580,7 @@ define signext i16 @select_cc_i1_i16(i1 zeroext %0, i1 zeroext %1, i16 signext % define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i8_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -599,7 +593,7 @@ define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext % define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u8_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -612,7 +606,7 @@ define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext % define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i16_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -625,7 +619,7 @@ define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signex define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u16_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -638,7 +632,7 @@ define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signex define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i32_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -651,7 +645,7 @@ define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signex define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u32_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -664,7 +658,7 @@ define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signex define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_i64_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -677,7 +671,7 @@ define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signex define signext i16 @select_cc_u64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { ; CHECK-LABEL: select_cc_u64_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -693,7 +687,6 @@ define signext i16 @select_cc_i128_i16(i128 %0, i128 %1, i16 signext %2, i16 sig ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -709,7 +702,6 @@ define signext i16 @select_cc_u128_i16(i128 %0, i128 %1, i16 signext %2, i16 sig ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -774,7 +766,7 @@ define zeroext i16 @select_cc_i1_u16(i1 zeroext %0, i1 zeroext %1, i16 zeroext % define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -787,7 +779,7 @@ define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext % define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -800,7 +792,7 @@ define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext % define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -813,7 +805,7 @@ define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroex define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -826,7 +818,7 @@ define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroex define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -839,7 +831,7 @@ define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroex define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -852,7 +844,7 @@ define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroex define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -865,7 +857,7 @@ define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroex define zeroext i16 @select_cc_u64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u16: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -881,7 +873,6 @@ define zeroext i16 @select_cc_i128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zer ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -897,7 +888,6 @@ define zeroext i16 @select_cc_u128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zer ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -962,7 +952,7 @@ define signext i32 @select_cc_i1_i32(i1 zeroext %0, i1 zeroext %1, i32 signext % define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i8_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -975,7 +965,7 @@ define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext % define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u8_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -988,7 +978,7 @@ define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext % define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i16_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1001,7 +991,7 @@ define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signex define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u16_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1014,7 +1004,7 @@ define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signex define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i32_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1027,7 +1017,7 @@ define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signex define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u32_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1040,7 +1030,7 @@ define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signex define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_i64_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1053,7 +1043,7 @@ define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signex define signext i32 @select_cc_u64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { ; CHECK-LABEL: select_cc_u64_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1069,7 +1059,6 @@ define signext i32 @select_cc_i128_i32(i128 %0, i128 %1, i32 signext %2, i32 sig ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1085,7 +1074,6 @@ define signext i32 @select_cc_u128_i32(i128 %0, i128 %1, i32 signext %2, i32 sig ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1150,7 +1138,7 @@ define zeroext i32 @select_cc_i1_u32(i1 zeroext %0, i1 zeroext %1, i32 zeroext % define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i8_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1163,7 +1151,7 @@ define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext % define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u8_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1176,7 +1164,7 @@ define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext % define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i16_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1189,7 +1177,7 @@ define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroex define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u16_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1202,7 +1190,7 @@ define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroex define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i32_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1215,7 +1203,7 @@ define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroex define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u32_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1228,7 +1216,7 @@ define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroex define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_i64_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1241,7 +1229,7 @@ define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroex define zeroext i32 @select_cc_u64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { ; CHECK-LABEL: select_cc_u64_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1257,7 +1245,6 @@ define zeroext i32 @select_cc_i128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zer ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1273,7 +1260,6 @@ define zeroext i32 @select_cc_u128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zer ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -1338,7 +1324,7 @@ define i64 @select_cc_i1_i64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i8_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1351,7 +1337,7 @@ define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u8_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1364,7 +1350,7 @@ define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i16_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1377,7 +1363,7 @@ define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u16_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1390,7 +1376,7 @@ define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i32_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1403,7 +1389,7 @@ define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u32_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1416,7 +1402,7 @@ define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i64_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1429,7 +1415,7 @@ define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_u64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u64_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1445,7 +1431,6 @@ define i64 @select_cc_i128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -1461,7 +1446,6 @@ define i64 @select_cc_u128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -1526,7 +1510,7 @@ define i64 @select_cc_i1_u64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i8_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1539,7 +1523,7 @@ define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u8_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1552,7 +1536,7 @@ define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i16_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1565,7 +1549,7 @@ define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u16_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1578,7 +1562,7 @@ define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i32_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1591,7 +1575,7 @@ define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u32_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1604,7 +1588,7 @@ define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_i64_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1617,7 +1601,7 @@ define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_u64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { ; CHECK-LABEL: select_cc_u64_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -1633,7 +1617,6 @@ define i64 @select_cc_i128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -1649,7 +1632,6 @@ define i64 @select_cc_u128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -1716,7 +1698,7 @@ define i128 @select_cc_i1_i128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i8_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1731,7 +1713,7 @@ define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u8_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1746,7 +1728,7 @@ define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i16_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1761,7 +1743,7 @@ define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3 define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u16_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1776,7 +1758,7 @@ define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3 define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i32_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1791,7 +1773,7 @@ define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3 define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u32_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1806,7 +1788,7 @@ define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3 define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i64_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1821,7 +1803,7 @@ define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_u64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u64_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1839,7 +1821,6 @@ define i128 @select_cc_i128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 @@ -1857,7 +1838,6 @@ define i128 @select_cc_u128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 @@ -1932,7 +1912,7 @@ define i128 @select_cc_i1_u128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i8_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1947,7 +1927,7 @@ define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u8_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1962,7 +1942,7 @@ define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i16_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1977,7 +1957,7 @@ define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3 define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u16_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -1992,7 +1972,7 @@ define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3 define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i32_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2007,7 +1987,7 @@ define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3 define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u32_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2022,7 +2002,7 @@ define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3 define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_i64_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2037,7 +2017,7 @@ define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_u64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { ; CHECK-LABEL: select_cc_u64_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2055,7 +2035,6 @@ define i128 @select_cc_i128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 @@ -2073,7 +2052,6 @@ define i128 @select_cc_u128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 @@ -2146,7 +2124,7 @@ define float @select_cc_i1_float(i1 zeroext %0, i1 zeroext %1, float %2, float % define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i8_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2159,7 +2137,7 @@ define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float % define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u8_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2172,7 +2150,7 @@ define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float % define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i16_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2185,7 +2163,7 @@ define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, floa define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u16_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2198,7 +2176,7 @@ define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, floa define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i32_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2211,7 +2189,7 @@ define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, floa define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u32_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2224,7 +2202,7 @@ define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, floa define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_i64_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2237,7 +2215,7 @@ define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) { define float @select_cc_u64_float(i64 %0, i64 %1, float %2, float %3) { ; CHECK-LABEL: select_cc_u64_float: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2253,7 +2231,6 @@ define float @select_cc_i128_float(i128 %0, i128 %1, float %2, float %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -2269,7 +2246,6 @@ define float @select_cc_u128_float(i128 %0, i128 %1, float %2, float %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -2334,7 +2310,7 @@ define double @select_cc_i1_double(i1 zeroext %0, i1 zeroext %1, double %2, doub define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i8_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2347,7 +2323,7 @@ define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, doub define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u8_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2360,7 +2336,7 @@ define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, doub define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i16_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2373,7 +2349,7 @@ define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, d define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u16_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2386,7 +2362,7 @@ define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, d define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i32_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2399,7 +2375,7 @@ define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, d define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u32_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2412,7 +2388,7 @@ define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, d define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_i64_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2425,7 +2401,7 @@ define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) { define double @select_cc_u64_double(i64 %0, i64 %1, double %2, double %3) { ; CHECK-LABEL: select_cc_u64_double: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -2441,7 +2417,6 @@ define double @select_cc_i128_double(i128 %0, i128 %1, double %2, double %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -2457,7 +2432,6 @@ define double @select_cc_u128_double(i128 %0, i128 %1, double %2, double %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) @@ -2524,7 +2498,7 @@ define fp128 @select_cc_i1_quad(i1 zeroext %0, i1 zeroext %1, fp128 %2, fp128 %3 define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i8_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2539,7 +2513,7 @@ define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3 define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u8_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2554,7 +2528,7 @@ define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3 define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i16_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2569,7 +2543,7 @@ define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u16_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2584,7 +2558,7 @@ define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i32_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2599,7 +2573,7 @@ define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u32_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2614,7 +2588,7 @@ define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_i64_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2629,7 +2603,7 @@ define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { ; CHECK-LABEL: select_cc_u64_quad: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: or %s0, 0, %s4 @@ -2647,7 +2621,6 @@ define fp128 @select_cc_i128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 @@ -2665,7 +2638,6 @@ define fp128 @select_cc_u128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { ; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s1 -; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: or %s0, 0, %s6 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll index 033f8f4..43b02a8 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf32c.ll @@ -7,7 +7,7 @@ define float @selectccsgti8(i8, i8, float, float) { ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -23,7 +23,7 @@ define float @selectccsgti16(i16, i16, float, float) { ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -35,7 +35,7 @@ define float @selectccsgti16(i16, i16, float, float) { define float @selectccsgti32(i32, i32, float, float) { ; CHECK-LABEL: selectccsgti32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -59,16 +59,15 @@ define float @selectccsgti64(i64, i64, float, float) { define float @selectccsgti128(i128, i128, float, float) { ; CHECK-LABEL: selectccsgti128: ; CHECK: # %bb.0: +; CHECK-NEXT: cmpu.l %s6, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: or %s6, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 +; CHECK-NEXT: or %s7, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2 -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 -; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 -; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll b/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll index f96d227..cf43f23 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf32i.ll @@ -23,8 +23,6 @@ define float @selectccat(float, float, float, float) { define float @selectccoeq(float, float, float, float) { ; CHECK-LABEL: selectccoeq: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -36,8 +34,6 @@ define float @selectccoeq(float, float, float, float) { define float @selectccone(float, float, float, float) { ; CHECK-LABEL: selectccone: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -49,8 +45,6 @@ define float @selectccone(float, float, float, float) { define float @selectccogt(float, float, float, float) { ; CHECK-LABEL: selectccogt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -62,8 +56,6 @@ define float @selectccogt(float, float, float, float) { define float @selectccoge(float, float, float, float) { ; CHECK-LABEL: selectccoge: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -75,8 +67,6 @@ define float @selectccoge(float, float, float, float) { define float @selectccolt(float, float, float, float) { ; CHECK-LABEL: selectccolt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -88,8 +78,6 @@ define float @selectccolt(float, float, float, float) { define float @selectccole(float, float, float, float) { ; CHECK-LABEL: selectccole: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -125,8 +113,6 @@ define float @selectccuno(float, float, float, float) { define float @selectccueq(float, float, float, float) { ; CHECK-LABEL: selectccueq: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -138,8 +124,6 @@ define float @selectccueq(float, float, float, float) { define float @selectccune(float, float, float, float) { ; CHECK-LABEL: selectccune: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -151,8 +135,6 @@ define float @selectccune(float, float, float, float) { define float @selectccugt(float, float, float, float) { ; CHECK-LABEL: selectccugt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -164,8 +146,6 @@ define float @selectccugt(float, float, float, float) { define float @selectccuge(float, float, float, float) { ; CHECK-LABEL: selectccuge: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -177,8 +157,6 @@ define float @selectccuge(float, float, float, float) { define float @selectccult(float, float, float, float) { ; CHECK-LABEL: selectccult: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -190,8 +168,6 @@ define float @selectccult(float, float, float, float) { define float @selectccule(float, float, float, float) { ; CHECK-LABEL: selectccule: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll index 8f1e9f5..fcc1d67 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf64c.ll @@ -7,7 +7,7 @@ define double @selectccsgti8(i8, i8, double, double) { ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -23,7 +23,7 @@ define double @selectccsgti16(i16, i16, double, double) { ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -35,7 +35,7 @@ define double @selectccsgti16(i16, i16, double, double) { define double @selectccsgti32(i32, i32, double, double) { ; CHECK-LABEL: selectccsgti32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -59,16 +59,15 @@ define double @selectccsgti64(i64, i64, double, double) { define double @selectccsgti128(i128, i128, double, double) { ; CHECK-LABEL: selectccsgti128: ; CHECK: # %bb.0: +; CHECK-NEXT: cmpu.l %s6, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: or %s6, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 +; CHECK-NEXT: or %s7, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2 -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 -; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 -; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 diff --git a/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll b/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll index 400ef43..3079499 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectccf64i.ll @@ -23,8 +23,6 @@ define double @selectccat(double, double, double, double) { define double @selectccoeq(double, double, double, double) { ; CHECK-LABEL: selectccoeq: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -36,8 +34,6 @@ define double @selectccoeq(double, double, double, double) { define double @selectccone(double, double, double, double) { ; CHECK-LABEL: selectccone: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -49,8 +45,6 @@ define double @selectccone(double, double, double, double) { define double @selectccogt(double, double, double, double) { ; CHECK-LABEL: selectccogt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -62,8 +56,6 @@ define double @selectccogt(double, double, double, double) { define double @selectccoge(double, double, double, double) { ; CHECK-LABEL: selectccoge: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -75,8 +67,6 @@ define double @selectccoge(double, double, double, double) { define double @selectccolt(double, double, double, double) { ; CHECK-LABEL: selectccolt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -88,8 +78,6 @@ define double @selectccolt(double, double, double, double) { define double @selectccole(double, double, double, double) { ; CHECK-LABEL: selectccole: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -125,8 +113,6 @@ define double @selectccuno(double, double, double, double) { define double @selectccueq(double, double, double, double) { ; CHECK-LABEL: selectccueq: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -138,8 +124,6 @@ define double @selectccueq(double, double, double, double) { define double @selectccune(double, double, double, double) { ; CHECK-LABEL: selectccune: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -151,8 +135,6 @@ define double @selectccune(double, double, double, double) { define double @selectccugt(double, double, double, double) { ; CHECK-LABEL: selectccugt: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -164,8 +146,6 @@ define double @selectccugt(double, double, double, double) { define double @selectccuge(double, double, double, double) { ; CHECK-LABEL: selectccuge: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -177,8 +157,6 @@ define double @selectccuge(double, double, double, double) { define double @selectccult(double, double, double, double) { ; CHECK-LABEL: selectccult: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -190,8 +168,6 @@ define double @selectccult(double, double, double, double) { define double @selectccule(double, double, double, double) { ; CHECK-LABEL: selectccule: ; CHECK: # %bb.0: -; CHECK-NEXT: lea.sl %s1, 0 -; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32.ll index 105ab5c..3ab1058 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci32.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32.ll @@ -3,7 +3,7 @@ define i32 @selectcceq(i32, i32, i32, i32) { ; CHECK-LABEL: selectcceq: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -15,7 +15,7 @@ define i32 @selectcceq(i32, i32, i32, i32) { define i32 @selectccne(i32, i32, i32, i32) { ; CHECK-LABEL: selectccne: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -27,7 +27,7 @@ define i32 @selectccne(i32, i32, i32, i32) { define i32 @selectccsgt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgt: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -39,7 +39,7 @@ define i32 @selectccsgt(i32, i32, i32, i32) { define i32 @selectccsge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsge: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -51,7 +51,7 @@ define i32 @selectccsge(i32, i32, i32, i32) { define i32 @selectccslt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccslt: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -63,7 +63,7 @@ define i32 @selectccslt(i32, i32, i32, i32) { define i32 @selectccsle(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsle: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll index ba05d0f..e91bc33 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32c.ll @@ -7,7 +7,7 @@ define i32 @selectccsgti8(i8, i8, i32, i32) { ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -23,7 +23,7 @@ define i32 @selectccsgti16(i16, i16, i32, i32) { ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -35,7 +35,7 @@ define i32 @selectccsgti16(i16, i16, i32, i32) { define i32 @selectccsgti32(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgti32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -59,16 +59,15 @@ define i32 @selectccsgti64(i64, i64, i32, i32) { define i32 @selectccsgti128(i128, i128, i32, i32) { ; CHECK-LABEL: selectccsgti128: ; CHECK: # %bb.0: +; CHECK-NEXT: cmpu.l %s6, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: or %s6, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 +; CHECK-NEXT: or %s7, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2 -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 -; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 -; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll b/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll index 8c74e70..69c247e 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci32i.ll @@ -3,8 +3,7 @@ define i32 @selectcceq(i32, i32, i32, i32) { ; CHECK-LABEL: selectcceq: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -16,8 +15,7 @@ define i32 @selectcceq(i32, i32, i32, i32) { define i32 @selectccne(i32, i32, i32, i32) { ; CHECK-LABEL: selectccne: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -29,9 +27,8 @@ define i32 @selectccne(i32, i32, i32, i32) { define i32 @selectccsgt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsgt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmps.w.zx %s0, 12, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i32 %0, 12 @@ -42,9 +39,8 @@ define i32 @selectccsgt(i32, i32, i32, i32) { define i32 @selectccsge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsge: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmps.w.zx %s0, 11, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i32 %0, 12 @@ -55,9 +51,8 @@ define i32 @selectccsge(i32, i32, i32, i32) { define i32 @selectccslt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccslt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmps.w.zx %s0, 12, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i32 %0, 12 @@ -68,9 +63,8 @@ define i32 @selectccslt(i32, i32, i32, i32) { define i32 @selectccsle(i32, i32, i32, i32) { ; CHECK-LABEL: selectccsle: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmps.w.zx %s0, 13, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i32 %0, 12 @@ -81,9 +75,8 @@ define i32 @selectccsle(i32, i32, i32, i32) { define i32 @selectccugt(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, 12 @@ -94,9 +87,8 @@ define i32 @selectccugt(i32, i32, i32, i32) { define i32 @selectccuge(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 11, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, 12 @@ -107,9 +99,8 @@ define i32 @selectccuge(i32, i32, i32, i32) { define i32 @selectccult(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, 12 @@ -120,9 +111,8 @@ define i32 @selectccult(i32, i32, i32, i32) { define i32 @selectccule(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 13, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, 12 @@ -133,9 +123,8 @@ define i32 @selectccule(i32, i32, i32, i32) { define i32 @selectccugt2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccugt2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i32 %0, 12 @@ -146,9 +135,8 @@ define i32 @selectccugt2(i32, i32, i32, i32) { define i32 @selectccuge2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccuge2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 11, %s0 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i32 %0, 12 @@ -159,9 +147,8 @@ define i32 @selectccuge2(i32, i32, i32, i32) { define i32 @selectccult2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccult2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 12, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i32 %0, 12 @@ -172,9 +159,8 @@ define i32 @selectccult2(i32, i32, i32, i32) { define i32 @selectccule2(i32, i32, i32, i32) { ; CHECK-LABEL: selectccule2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmpu.w %s0, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.w %s0, 13, %s0 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i32 %0, 12 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64.ll index 0ab4b11..62caa5c 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci64.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64.ll @@ -3,7 +3,7 @@ define i64 @selectcceq(i64, i64, i64, i64) { ; CHECK-LABEL: selectcceq: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -15,7 +15,7 @@ define i64 @selectcceq(i64, i64, i64, i64) { define i64 @selectccne(i64, i64, i64, i64) { ; CHECK-LABEL: selectccne: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll index 28e596c..49fdd4f 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64c.ll @@ -7,7 +7,7 @@ define i64 @selectccsgti8(i8, i8, i64, i64) { ; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -23,7 +23,7 @@ define i64 @selectccsgti16(i16, i16, i64, i64) { ; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48 -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -35,7 +35,7 @@ define i64 @selectccsgti16(i16, i16, i64, i64) { define i64 @selectccsgti32(i32, i32, i64, i64) { ; CHECK-LABEL: selectccsgti32: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -59,16 +59,15 @@ define i64 @selectccsgti64(i64, i64, i64, i64) { define i64 @selectccsgti128(i128, i128, i64, i64) { ; CHECK-LABEL: selectccsgti128: ; CHECK: # %bb.0: +; CHECK-NEXT: cmpu.l %s6, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: or %s3, 0, (0)1 -; CHECK-NEXT: or %s6, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 +; CHECK-NEXT: or %s7, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2 -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 -; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 -; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 -; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7 ; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i128 %0, %1 diff --git a/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll b/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll index 5fb4bbe..717d87c 100644 --- a/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll +++ b/llvm/test/CodeGen/VE/Scalar/selectcci64i.ll @@ -3,8 +3,7 @@ define i64 @selectcceq(i64, i64, i64, i64) { ; CHECK-LABEL: selectcceq: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -16,8 +15,7 @@ define i64 @selectcceq(i64, i64, i64, i64) { define i64 @selectccne(i64, i64, i64, i64) { ; CHECK-LABEL: selectccne: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) @@ -29,9 +27,8 @@ define i64 @selectccne(i64, i64, i64, i64) { define i64 @selectccsgt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsgt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmps.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sgt i64 %0, 12 @@ -42,9 +39,8 @@ define i64 @selectccsgt(i64, i64, i64, i64) { define i64 @selectccsge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsge: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmps.l %s0, 11, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sge i64 %0, 12 @@ -55,9 +51,8 @@ define i64 @selectccsge(i64, i64, i64, i64) { define i64 @selectccslt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccslt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmps.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp slt i64 %0, 12 @@ -68,9 +63,8 @@ define i64 @selectccslt(i64, i64, i64, i64) { define i64 @selectccsle(i64, i64, i64, i64) { ; CHECK-LABEL: selectccsle: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmps.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmps.l %s0, 13, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp sle i64 %0, 12 @@ -81,9 +75,8 @@ define i64 @selectccsle(i64, i64, i64, i64) { define i64 @selectccugt(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, 12 @@ -94,9 +87,8 @@ define i64 @selectccugt(i64, i64, i64, i64) { define i64 @selectccuge(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 11, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, 12 @@ -107,9 +99,8 @@ define i64 @selectccuge(i64, i64, i64, i64) { define i64 @selectccult(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, 12 @@ -120,9 +111,8 @@ define i64 @selectccult(i64, i64, i64, i64) { define i64 @selectccule(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 13, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, 12 @@ -133,9 +123,8 @@ define i64 @selectccule(i64, i64, i64, i64) { define i64 @selectccugt2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccugt2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ugt i64 %0, 12 @@ -146,9 +135,8 @@ define i64 @selectccugt2(i64, i64, i64, i64) { define i64 @selectccuge2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccuge2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 11, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 11, %s0 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp uge i64 %0, 12 @@ -159,9 +147,8 @@ define i64 @selectccuge2(i64, i64, i64, i64) { define i64 @selectccult2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccult2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 12, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 12, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ult i64 %0, 12 @@ -172,9 +159,8 @@ define i64 @selectccult2(i64, i64, i64, i64) { define i64 @selectccule2(i64, i64, i64, i64) { ; CHECK-LABEL: selectccule2: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s1, 13, (0)1 -; CHECK-NEXT: cmpu.l %s0, %s0, %s1 -; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: cmpu.l %s0, 13, %s0 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: b.l.t (, %s10) %5 = icmp ule i64 %0, 12 diff --git a/llvm/test/CodeGen/VE/Scalar/smax.ll b/llvm/test/CodeGen/VE/Scalar/smax.ll index f989e04..93637d4 100644 --- a/llvm/test/CodeGen/VE/Scalar/smax.ll +++ b/llvm/test/CodeGen/VE/Scalar/smax.ll @@ -73,9 +73,10 @@ define i128 @func_smax_var_i128(i128 noundef %0, i128 noundef %1) { ; CHECK-NEXT: cmps.l %s5, %s1, %s3 ; CHECK-NEXT: or %s4, 0, %s2 ; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 -; CHECK-NEXT: cmpu.l %s6, %s0, %s2 -; CHECK-NEXT: cmov.l.gt %s2, %s0, %s6 -; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5 +; CHECK-NEXT: cmpu.l %s5, %s0, %s2 +; CHECK-NEXT: cmov.l.gt %s2, %s0, %s5 +; CHECK-NEXT: cmpu.l %s0, %s1, %s3 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: maxs.l %s1, %s1, %s3 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: b.l.t (, %s10) @@ -130,10 +131,9 @@ define i64 @func_smax_fore_zero_i64(i64 noundef %0) { define i128 @func_smax_fore_zero_i128(i128 noundef %0) { ; CHECK-LABEL: func_smax_fore_zero_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3 -; CHECK-NEXT: cmov.l.eq %s2, %s0, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.le %s2, (0)1, %s1 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: maxs.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) @@ -188,10 +188,9 @@ define i64 @func_smax_back_zero_i64(i64 noundef %0) { define i128 @func_smax_back_zero_i128(i128 noundef %0) { ; CHECK-LABEL: func_smax_back_zero_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3 -; CHECK-NEXT: cmov.l.eq %s2, %s0, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.le %s2, (0)1, %s1 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: maxs.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) @@ -246,13 +245,11 @@ define i64 @func_smax_fore_const_i64(i64 noundef %0) { define i128 @func_smax_fore_const_i128(i128 noundef %0) { ; CHECK-LABEL: func_smax_fore_const_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.le %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: maxs.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) @@ -307,13 +304,11 @@ define i64 @func_smax_back_const_i64(i64 noundef %0) { define i128 @func_smax_back_const_i128(i128 noundef %0) { ; CHECK-LABEL: func_smax_back_const_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.le %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: maxs.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/smin.ll b/llvm/test/CodeGen/VE/Scalar/smin.ll index a46c4e1..a19e167 100644 --- a/llvm/test/CodeGen/VE/Scalar/smin.ll +++ b/llvm/test/CodeGen/VE/Scalar/smin.ll @@ -73,9 +73,10 @@ define i128 @func_smin_var_i128(i128 noundef %0, i128 noundef %1) { ; CHECK-NEXT: cmps.l %s5, %s1, %s3 ; CHECK-NEXT: or %s4, 0, %s2 ; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5 -; CHECK-NEXT: cmpu.l %s6, %s0, %s2 -; CHECK-NEXT: cmov.l.lt %s2, %s0, %s6 -; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5 +; CHECK-NEXT: cmpu.l %s5, %s0, %s2 +; CHECK-NEXT: cmov.l.lt %s2, %s0, %s5 +; CHECK-NEXT: cmpu.l %s0, %s1, %s3 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: mins.l %s1, %s1, %s3 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: b.l.t (, %s10) @@ -130,11 +131,9 @@ define i64 @func_smin_fore_zero_i64(i64 noundef %0) { define i128 @func_smin_fore_zero_i128(i128 noundef %0) { ; CHECK-LABEL: func_smin_fore_zero_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: sra.l %s4, %s1, 63 -; CHECK-NEXT: and %s0, %s4, %s0 -; CHECK-NEXT: cmov.l.eq %s0, %s2, %s3 +; CHECK-NEXT: sra.l %s2, %s1, 63 +; CHECK-NEXT: and %s0, %s2, %s0 +; CHECK-NEXT: cmov.l.eq %s0, (0)1, %s1 ; CHECK-NEXT: mins.l %s1, 0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0) @@ -188,11 +187,9 @@ define i64 @func_smin_back_zero_i64(i64 noundef %0) { define i128 @func_smin_back_zero_i128(i128 noundef %0) { ; CHECK-LABEL: func_smin_back_zero_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: or %s2, 0, (0)1 -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: sra.l %s4, %s1, 63 -; CHECK-NEXT: and %s0, %s4, %s0 -; CHECK-NEXT: cmov.l.eq %s0, %s2, %s3 +; CHECK-NEXT: sra.l %s2, %s1, 63 +; CHECK-NEXT: and %s0, %s2, %s0 +; CHECK-NEXT: cmov.l.eq %s0, (0)1, %s1 ; CHECK-NEXT: mins.l %s1, 0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0) @@ -246,13 +243,11 @@ define i64 @func_smin_fore_const_i64(i64 noundef %0) { define i128 @func_smin_fore_const_i128(i128 noundef %0) { ; CHECK-LABEL: func_smin_fore_const_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.lt %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.ge %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: mins.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) @@ -307,13 +302,11 @@ define i64 @func_smin_back_const_i64(i64 noundef %0) { define i128 @func_smin_back_const_i128(i128 noundef %0) { ; CHECK-LABEL: func_smin_back_const_i128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.lt %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.ge %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: mins.l %s1, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/umax.ll b/llvm/test/CodeGen/VE/Scalar/umax.ll index 3df721f..4eb3034 100644 --- a/llvm/test/CodeGen/VE/Scalar/umax.ll +++ b/llvm/test/CodeGen/VE/Scalar/umax.ll @@ -89,8 +89,7 @@ define i128 @func_umax_var_u128(i128 noundef %0, i128 noundef %1) { ; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 ; CHECK-NEXT: cmpu.l %s6, %s0, %s2 ; CHECK-NEXT: cmov.l.gt %s2, %s0, %s6 -; CHECK-NEXT: cmps.l %s0, %s1, %s3 -; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5 ; CHECK-NEXT: cmov.l.gt %s3, %s1, %s5 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s3 @@ -228,10 +227,9 @@ define zeroext i16 @func_umax_fore_const_u16(i16 noundef zeroext %0) { define zeroext i32 @func_umax_fore_const_u32(i32 noundef zeroext %0) { ; CHECK-LABEL: func_umax_fore_const_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.w %s2, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2 -; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, (56)0 +; CHECK-NEXT: cmov.w.le %s0, (56)0, %s1 +; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i32 @llvm.umax.i32(i32 %0, i32 255) ret i32 %2 @@ -241,10 +239,8 @@ define zeroext i32 @func_umax_fore_const_u32(i32 noundef zeroext %0) { define i64 @func_umax_fore_const_u64(i64 noundef %0) { ; CHECK-LABEL: func_umax_fore_const_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2 -; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: cmpu.l %s1, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i64 @llvm.umax.i64(i64 %0, i64 255) ret i64 %2 @@ -254,13 +250,11 @@ define i64 @func_umax_fore_const_u64(i64 noundef %0) { define i128 @func_umax_fore_const_u128(i128 noundef %0) { ; CHECK-LABEL: func_umax_fore_const_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.ne %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.eq %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.umax.i128(i128 %0, i128 255) @@ -300,10 +294,9 @@ define zeroext i16 @func_umax_back_const_u16(i16 noundef zeroext %0) { define zeroext i32 @func_umax_back_const_u32(i32 noundef zeroext %0) { ; CHECK-LABEL: func_umax_back_const_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.w %s2, %s0, %s1 -; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2 -; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, (56)0 +; CHECK-NEXT: cmov.w.le %s0, (56)0, %s1 +; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i32 @llvm.umax.i32(i32 %0, i32 255) ret i32 %2 @@ -313,10 +306,8 @@ define zeroext i32 @func_umax_back_const_u32(i32 noundef zeroext %0) { define i64 @func_umax_back_const_u64(i64 noundef %0) { ; CHECK-LABEL: func_umax_back_const_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2 -; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: cmpu.l %s1, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i64 @llvm.umax.i64(i64 %0, i64 255) ret i64 %2 @@ -326,13 +317,11 @@ define i64 @func_umax_back_const_u64(i64 noundef %0) { define i128 @func_umax_back_const_u128(i128 noundef %0) { ; CHECK-LABEL: func_umax_back_const_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: cmps.l %s3, %s1, (0)1 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmov.l.ne %s2, %s0, %s3 -; CHECK-NEXT: cmpu.l %s5, %s0, (56)0 -; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3 +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: cmov.l.eq %s2, (56)0, %s1 +; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 +; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3 +; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1 ; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.umax.i128(i128 %0, i128 255) diff --git a/llvm/test/CodeGen/VE/Scalar/umin.ll b/llvm/test/CodeGen/VE/Scalar/umin.ll index 937fa42..21cb2a6 100644 --- a/llvm/test/CodeGen/VE/Scalar/umin.ll +++ b/llvm/test/CodeGen/VE/Scalar/umin.ll @@ -89,8 +89,7 @@ define i128 @func_umin_var_u128(i128 noundef %0, i128 noundef %1) { ; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5 ; CHECK-NEXT: cmpu.l %s6, %s0, %s2 ; CHECK-NEXT: cmov.l.lt %s2, %s0, %s6 -; CHECK-NEXT: cmps.l %s0, %s1, %s3 -; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 +; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5 ; CHECK-NEXT: cmov.l.lt %s3, %s1, %s5 ; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s3 @@ -240,10 +239,9 @@ define zeroext i16 @func_umin_fore_const_u16(i16 noundef zeroext %0) { define zeroext i32 @func_umin_fore_const_u32(i32 noundef zeroext %0) { ; CHECK-LABEL: func_umin_fore_const_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.w %s2, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2 -; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, (56)0 +; CHECK-NEXT: cmov.w.ge %s0, (56)0, %s1 +; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i32 @llvm.umin.i32(i32 %0, i32 255) ret i32 %2 @@ -253,10 +251,8 @@ define zeroext i32 @func_umin_fore_const_u32(i32 noundef zeroext %0) { define i64 @func_umin_fore_const_u64(i64 noundef %0) { ; CHECK-LABEL: func_umin_fore_const_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 -; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 -; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: cmpu.l %s1, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i64 @llvm.umin.i64(i64 %0, i64 255) ret i64 %2 @@ -266,14 +262,10 @@ define i64 @func_umin_fore_const_u64(i64 noundef %0) { define i128 @func_umin_fore_const_u128(i128 noundef %0) { ; CHECK-LABEL: func_umin_fore_const_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: cmov.l.lt %s4, %s0, %s3 -; CHECK-NEXT: cmps.l %s0, %s1, (0)1 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s0 +; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s2 +; CHECK-NEXT: cmov.l.ne %s0, (56)0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.umin.i128(i128 %0, i128 255) ret i128 %2 @@ -310,10 +302,9 @@ define zeroext i16 @func_umin_back_const_u16(i16 noundef zeroext %0) { define zeroext i32 @func_umin_back_const_u32(i32 noundef zeroext %0) { ; CHECK-LABEL: func_umin_back_const_u32: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.w %s2, %s0, %s1 -; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2 -; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, (56)0 +; CHECK-NEXT: cmov.w.ge %s0, (56)0, %s1 +; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i32 @llvm.umin.i32(i32 %0, i32 255) ret i32 %2 @@ -323,10 +314,8 @@ define zeroext i32 @func_umin_back_const_u32(i32 noundef zeroext %0) { define i64 @func_umin_back_const_u64(i64 noundef %0) { ; CHECK-LABEL: func_umin_back_const_u64: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s1, 255 -; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 -; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 -; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: cmpu.l %s1, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s1 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i64 @llvm.umin.i64(i64 %0, i64 255) ret i64 %2 @@ -336,14 +325,10 @@ define i64 @func_umin_back_const_u64(i64 noundef %0) { define i128 @func_umin_back_const_u128(i128 noundef %0) { ; CHECK-LABEL: func_umin_back_const_u128: ; CHECK: # %bb.0: -; CHECK-NEXT: lea %s2, 255 -; CHECK-NEXT: cmpu.l %s3, %s0, (56)0 -; CHECK-NEXT: lea %s4, 255 -; CHECK-NEXT: cmov.l.lt %s4, %s0, %s3 -; CHECK-NEXT: cmps.l %s0, %s1, (0)1 -; CHECK-NEXT: cmov.l.eq %s2, %s4, %s0 +; CHECK-NEXT: cmpu.l %s2, %s0, (56)0 +; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s2 +; CHECK-NEXT: cmov.l.ne %s0, (56)0, %s1 ; CHECK-NEXT: or %s1, 0, (0)1 -; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: b.l.t (, %s10) %2 = tail call i128 @llvm.umin.i128(i128 %0, i128 255) ret i128 %2 -- 2.7.4