From 33dd23dee36d93e9ea2438e6fc1599d721ccd4e2 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Fri, 12 Aug 2011 22:43:35 +0100 Subject: [PATCH] TEST mfld pmu: add arch/x86/platform/mfld/pmu.h from UMG 2.6.35 tree: arch/x86/kernel/mid_pmu.h commit 1df781ef9bbc9b0fc453537da2a3b1861f363138 Author: Illyas Mansoor Date: Thu Jun 23 04:58:43 2011 +0530 mid_pmu: sparse warnings fixed BZ: 3856 Fixed the following sparse warnings. arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static? fixed make namespacecheck issues. Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495 Signed-off-by: Illyas Mansoor commit 5e73c57d106f8c766a5a06221e2817a7c9a5b393 Author: Rajesh Poornachandran Date: Thu Jun 16 16:59:39 2011 -0700 Revert "Revert "mid_pmu: Moving NC power management logic to OSPM"" BZ: 1957 Currently the PM for north complex was done independently by Gfx and ISP drivers. There was no synchronization between ISP and Gfx while sending the PM cmd. OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care of talking to P-unit and getting the corresponding power islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers. Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb Signed-off-by: Sujith Thomas Signed-off-by: Rajesh Poornachandran commit dd6db50f98b6c0d368b9315124b65ec3b1aae2a1 Author: Erwan Mahe Date: Thu Jun 23 18:29:21 2011 +0200 Revert "Revert "mid_pmu: pick correct D0ix states in choose_state"" BZ: 2102 This reverts commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c. Change-Id: I5aa5658cf28696a3c79a939ea8644a3b3c4d73f0 commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c Author: Marie-Celine Dubut Date: Wed Jun 22 12:44:06 2011 +0200 Revert "mid_pmu: pick correct D0ix states in choose_state" BZ 2102 This reverts commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d. Change-Id: I7e7aed5071adabc824c303628ba855031892e70a commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d Author: Illyas Mansoor Date: Wed Jun 1 13:19:54 2011 +0530 mid_pmu: pick correct D0ix states in choose_state BZ: 2102 currently pmu_pci_choose_state return PCI_D3hot for all devices. For some of devices, it may not be possible to support PCI_D3hot state. eg., HSU needs to be put in D0i1, chaabi needs to be put in D0i2. It is not appropriate to always choose D0i3 for all devices We choose the correct state that is appropriate for each device for the platform. This patch should be used only with a FW that is capable of supporting Chaabi D0i2. Change-Id: Ief7b64bc1ec37d4452ce3222454bdd6102d54c10 Signed-off-by: Illyas Mansoor commit c4e73f14acb7ffd39a5d965fc23b1f01673363b8 Author: Hari Kanigeri Date: Fri Jun 3 11:27:13 2011 -0600 mid_pmu: fix checkpatch violations and some cleanup in exit paths BZ: 3066 Fix the following: 1. Checkpatch violations and cosmetic changes. 2. fix correct cleanup in the exit paths of the function mid_pmu_probe Below log is related to checkpatch violations. 1. Checkpatch violations ========================= ERROR: space required before the open parenthesis '(' + if(pdev->device == 0x81c || pdev->device == 0x81b) WARNING: line over 80 characters + for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {} ERROR: trailing statements should be on next line + for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {} WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {} WARNING: line over 80 characters +static pci_power_t pmu_pci_get_weakest_state_for_lss(int lss_index, struct pci_dev *pdev, pci_power_t state) total: 122 errors, 14 warnings, 2340 lines checked Change-Id: I1cdbd6a8b70d303611f0cd426ce63235010d0a07 Signed-off-by: Hari Kanigeri Signed-off-by: Illyas Mansoor commit d332d4a59c01e1774cd4fdc28d97fe4d865989ee Author: Vishwesh M Rudramuni Date: Thu Feb 16 22:36:00 2006 +0530 pmu: adding atomisp as part of entry criterion for S0i3 BZ: 1339 In current build we dont look at the isp runtime status before we enter S0i3 state. In this patch we check for the camera status in addition to all other device states that we check today in S0i3. Change-Id: If3f024fa22d0d744160b961e637e2b1c25e5e1c9 Signed-off-by: Vishwesh M Rudramuni commit 53f93b022da79eadc22a2ac5c3adade98380cf84 Author: Illyas Mansoor Date: Mon May 16 00:26:13 2011 +0530 mid_pmu: demote c6 to c4 while s0ix is in progress BZ: 2120 While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of mwait and since the SCU is still waiting for Ack_C6 the S0ix ACK_C6 timeout error interrupt is not recieved, meanwhile a new C6 could be triggered from IA and this could trigger a Ack_C6 SCU can mistake this Ack_C6 as a ack for the previously aborted S0ix and continue S0ix flow. This is not correct. We check if the system is in S0ix progress state by checking scu_ready_sem if its already acquired that means S0ix is in progress and the subsequent C6 should be demoted to C4's Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712 Signed-off-by: Illyas Mansoor commit 654da78fa8f45bcf4d64d9c0ea115d589f4374c4 Author: Illyas Mansoor Date: Sun May 15 23:44:23 2011 +0530 mid_pmu: c6 offload msr bit cleanup BZ: 2116 We were using magic number for wmsr(0x120) for setting/clearing offload bit. Fixed this by creating #defines Change-Id: I5fe4ec0568e48d12fe30074f8eebbc2a6411b4d8 Signed-off-by: Illyas Mansoor commit 8118849a0329d0e73761562443ae25c8b1cd3bf9 Author: Fengwei Yin Date: Sun May 22 11:57:12 2011 +0800 Revert "mid_pmu: Moving NC power management logic to OSPM" BZ: 2470 This reverts commit 594c7f0327dd02985fbcde1e0bd83c98e684097f. commit 594c7f0327dd02985fbcde1e0bd83c98e684097f Author: Sujith Thomas Date: Thu May 12 10:51:38 2011 +0530 mid_pmu: Moving NC power management logic to OSPM BZ: 1957 Currently the PM for north complex was done independently by Gfx and ISP drivers. There was no synchronization between ISP and Gfx while sending the PM cmd. OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care of talking to P-unit and getting the corresponding power islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers. Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc Signed-off-by: Sujith Thomas commit cba613f2bde66236706b9c0ba7f1fe6b5ff14ad7 Author: Vishwesh M Rudramuni Date: Tue May 10 16:22:10 2011 +0530 pmu: renaming lss after new wkc implementation in scu BZ 1756 This patch we are re assigning some of the lss to new lss based on the WKC implementation in scu. Change-Id: Ic7a9adf37194182b424dcdcc0d61cb09bba4a7a5 Signed-off-by: Vishwesh M Rudramuni commit 821d3f9513a5126201531e804c98b3618456d637 Author: Jean-Pierre Stierlin Date: Thu May 5 18:19:43 2011 +0200 OSPM: Add HSI as wake source in s0i3 BZ: 1705 HSI wake event was disabled in SCU configuration Revert a hack to disable HSI wake event to the SCU due to spurious interrupts. Change-Id: I2e9173fdf79fa158394a4b0b5894f643d3a43b8f commit cfda66e44bc142f836c2e550211997759aa0d8e2 Author: Illyas Mansoor Date: Wed Mar 30 16:23:28 2011 +0530 mid_pmu: cleanup added explicit LSS ids for s0ix entry Currently the LSS that need to be checked for S0ix/LPMP3 entry is hardcoded making it difficult to read the sub system values. Added #defines for all the sub system LSS id's, using this defined the target config values to check against the SSS register values, that tells which subsystems need to in D0i3 to issue S0i1/3 or LPMP3 commands. Also added a way to keep always ON LSS to be in D0i0. Added check for Keyboard, UART0/1/2 LSS in S0i1/lpmp3/S0i3 SSS config registers. Removed LSS 40, 41 from ignore_lss list. Change-Id: Ifd28b58f11c66232dc2993b3946c672bbe9931a3 Signed-off-by: Illyas Mansoor commit 885ebc4f559cdaa19b3dddd02faa2dba246ae689 Author: Sundar Iyer Date: Tue Mar 22 15:03:51 2011 +0530 mid_pmu: correct D0ix states during S0i3 Enable the UART0/1/2 and the KBD modules to be put into D0i3 states during the S0i3. Change-Id: Idec4907699ba23506900a249a130cecaed85dc82 Signed-off-by: Sundar Iyer commit 56ab6e9474f2e04f50ddede8f2b6db9e1dc852c1 Author: Sundar Iyer Date: Wed Mar 9 13:19:29 2011 +0530 mid_pmu: correct USB Dx state during S0i3 entry Enable D0i3 state for the USB during S0i3 entry. Making this change realizes power figures for the USB rail from ~16mW to ~.4mW Signed-off-by: Sundar Iyer commit 0c2cb76662387a575c6f41b9f91a85cd76064f55 Author: Illyas Mansoor Date: Sat Feb 5 14:52:41 2011 +0100 mid_pmu: cleanup: fix sparse check warnings moved all #defines to mid_pmu.h fixed warnings after installing sparse tool Fixed the following warnings from sparse. with make C=2 >& sparse.log command. arch/x86/kernel/mid_pmu.c:46:3: warning: symbol 'pci_dev_index' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1175:70: warning: incorrect type in argument 2 (different address spaces) arch/x86/kernel/mid_pmu.c:1175:70: expected void volatile [noderef] *addr arch/x86/kernel/mid_pmu.c:1175:70: got unsigned int * arch/x86/kernel/mid_pmu.c:1180:76: warning: incorrect type in argument 2 (different address spaces) arch/x86/kernel/mid_pmu.c:1180:76: expected void volatile [noderef] *addr arch/x86/kernel/mid_pmu.c:1180:76: got unsigned int * arch/x86/kernel/mid_pmu.c:322:5: warning: symbol 'get_target_platform_state' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:691:6: warning: symbol 'mfld_s0i1_enter' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:717:5: warning: symbol 'mfld_s0i3_enter' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:844:5: warning: symbol 'is_msi_enabled' was not declared. Should it be static? arch/x86/kernel/mid_pmu.c:1191:59: got unsigned int * arch/x86/kernel/mid_pmu.c:1502:13: warning: incorrect type in assignment (different address spaces) arch/x86/kernel/mid_pmu.c:1502:13: expected struct mrst_pmu_reg *pmu arch/x86/kernel/mid_pmu.c:1502:13: got void [noderef] * arch/x86/kernel/mid_pmu.c:1567:27: expected void [noderef] * arch/x86/kernel/mid_pmu.c:1567:27: got struct mrst_pmu_reg *static [toplevel] * ... and similar warnings. Signed-off-by: Illyas Mansoor commit 33d19d30ff22685f18f184183b1e675d8fe94fea Author: Illyas Mansoor Date: Mon Jan 17 08:22:32 2011 +0100 mid_pmu: driver that controls pmus of intel_mid platforms Mobile Internet Devices based on the Intel "Medfield" platform have two Platform Management Units (PMU). The first PMU (pmu1) comprises of the Silverthorne CPU, Graphics, Video encode/decode and Display engines, The second PMU (pmu2) is the IO hub. The Platform Management Unit (PMU) driver is a Medfield-specific power management driver. Intel's MID provides fine tuned knobs for platform level. Intel's Medfield MID provides control for platform level power management and the OS Power Management solution guides the power states that the subsystems and CPU needs to be in depending on the current usage and power policy set by the user. The purpose of the Medfield Power Management architecture is to turn off subsystems without affecting the end user functionality/usability of the system. The Power Management scheme uses the concept of operating modes, which define the configuration of all the subsystems under each of the usage model that the user might put the system in. Based on current platform usage, OSPM decides the target power states for the sub systems, and the PMU driver implements the OS-HW interface. "Intel" Medfield PMU driver interfaces with two power management units (PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces with the pmu1 & pmu2 via a well defined register interface to drive the required power management flows. This patch contains: - key definitions for the PMU driver. - core logic of the PMU driver as it interfaces with pmu1 & pmu2 for different platform power management flows. Signed-off-by: Vishwesh M Rudramuni Signed-off-by: Rajeev D Muralidhar Signed-off-by: Illyas Mansoor Signed-off-by: Len Brown --- arch/x86/platform/mfld/pmu.h | 536 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 536 insertions(+) create mode 100644 arch/x86/platform/mfld/pmu.h diff --git a/arch/x86/platform/mfld/pmu.h b/arch/x86/platform/mfld/pmu.h new file mode 100644 index 0000000..e259c4c --- /dev/null +++ b/arch/x86/platform/mfld/pmu.h @@ -0,0 +1,536 @@ +/* + * mid_pmu.h + * Copyright (c) 2010, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _MID_PMU_H_ +#define _MID_PMU_H_ + +#include + +#define PCI_ID_ANY (~0) + +/* P Unit Memory Map */ + +/* PMU1 Register */ +#define PMU1_PMU_BASE_ADDR 0x940 +#define PMU2_PMU_BASE_ADDR 0xFF11D000 + +/* PMU register memory map */ + +/* PMU1/PMU2 PM Status Reg */ +#define PMU_PM_STS_REG 0x00 +/* PMU1/PMU2 PM Command Reg */ +#define PMU_PM_CMD_REG 0x04 +/* PMU1/PMU2 PM Interrupt Control and Status Reg */ +#define PMU_PM_ICS_REG 0x08 +/* PMU1/PMU2 PM subsystem configuration register */ +#define PMU_PM_SSC_REG0 0x20 +#define PMU_PM_SSC_REG1 0x24 +#define PMU_PM_SSC_REG2 0x28 +#define PMU_PM_SSC_REG3 0x2C +/* PMU1/PMU2 PM Subsystem status Reg */ +#define PMU_PM_SSS_REG0 0x30 +#define PMU_PM_SSS_REG1 0x34 +#define PMU_PM_SSS_REG2 0x38 +#define PMU_PM_SSS_REG3 0x3C +/* PMU2 PM Wake Control */ +#define PMU_PM_WKC_REG0 0x10 +#define PMU_PM_WKC_REG1 0x14 +/* PMU2 PM Wake Status Reg */ +#define PMU_PM_WKS_REG0 0x18 +#define PMU_PM_WKS_REG1 0x1C +/* PMU2 PM Wake Status Reg */ +#define PMU_PM_WSSC_REG0 0x40 +#define PMU_PM_WSSC_REG1 0x44 +#define PMU_PM_WSSC_REG2 0x48 +#define PMU_PM_WSSC_REG3 0x4C +/* PMU2 PM Subsystem status Reg */ +#define PMU_PM_C3C4_REG 0x50 +/* PMU2 PM Subsystem status Reg */ +#define PMU_PM_C5C6_REG 0x54 +/* PMU2 PM Subsystem status Reg */ +#define PMU_PM_MSIC_REG 0x58 + +#define ACK_C6_DMI_MSG 0xC2 +#define MODE_ID_MAGIC_NUM 1 +#define PMU1_END_ADDRESS 0x34 +#define PMU2_END_ADDRESS 0x3B8 + +#define PMU2_SS_CFG_MASK 0x00FFFFFF +#define PMU2_WAKE_CFG_MASK 0x00000FFF +#define WAKE_CTRL_DEFAULT 0x1C2 + +/* PM table definitions */ +#define PM_TABLE_BASE 0x1D000 +#define PM_TABLE_PMU1_OFFSET 0x0 +#define PM_TABLE_PMU2_OFFSET 0x0 +#define PM_TABLE_PMU2_LOG_TO_PHY_MAP 0x0 +#define PM_TABLE_MAX 0xF0 +#define PM_TABLE_THRESH_MASK 0xFFFF + +/* Inactivity register definitions */ +#define PMU_INA_INT_STS_REG 0x220 +#define PMU_INA_THRESH_BASE 0x240 +#define PMU_INA_CTR_BASE 0x340 +#define PMU_INA_STS_REG 0x210 +#define PMU_INA_INVALID_SRC 0xFF +#define PMU_INA_CTR_MAX 32 +#define SINGLE_BIT_MASK 0x1 + +/* External timers register definitions */ +#define PMU2_EXT_TIMERS_BASE 0xff11B800 +#define PMU2_EXT_TIMERS_BASE_MAX 0xB0 +#define PMU2_EXT_TIMERS_MAX 8 +#define PMU2_EXT_TIMERS_0_OFFSET 0x14 +#define PMU2_EXT_TIMERS_LOAD_COUNT_REG 0x0 +#define PMU2_EXT_TIMERS_CUR_VAL_REG 0x4 +#define PMU2_EXT_TIMERS_CTRL_REG 0x8 +#define PMU2_EXT_TIMERS_EOI_REG 0xC +#define PMU2_EXT_TIMERS_INT_STATUS_REG 0x10 +#define PMU2_EXT_TIMERS_GLB_INT_STATUS_REG 0xa0 +#define PMU2_EXT_TIMERS_GLB_EOI_REG 0xa4 +#define PMU2_EXT_TIMERS_RAW_INT_STATUS_REG 0xa8 +#define PMU2_EXT_TIMERS_COMP_VER 0xac +#define TIMER_COUNT_ALL_ONES 0xFFFFFFFF +#define TIMER_IS_MASKED 0x4 +#define TIMER_IS_NOT_MASKED 0x3 +#define TIMER_FREE_RUNNING_MODE 0x5 +#define TIMER_USER_DEFINED_MODE 0x2 +#define TIMER_EN_VAL 0x1 + +/* Definitions used for Enumeration */ +#define SFI_PCI_CFG_START 0x80000000 +#define SFI_PCI_CFG_SIZE 256 +#define PMU1_DEV_MASK 0x3FFF +#define PMU2_DEV_MASK 0x3FFFFFFF +#define PM_SUPPORT 0x21 +#define LOG_ID_MASK 0x7F +#define SUB_CLASS_MASK 0xFF00 + +/* Definitions for Message Bus Interface */ +#define MSG_CMD_REG 0xD0 +#define MSG_DATA_REG 0xD4 + +/* Definition for C6 Offload MSR Address */ +#define MSR_C6OFFLOAD_CTL_REG 0x120 + +#define MSR_C6OFFLOAD_SET_LOW 1 +#define MSR_C6OFFLOAD_SET_HIGH 0 + +#define MSR_C6OFFLOAD_CLEAR_LOW 0 +#define MSR_C6OFFLOAD_CLEAR_HIGH 0 + +#define C6OFFLOAD_BIT_MASK 0x2 +#define C6OFFLOAD_BIT 0x2 + +/* Need to be changed after PMU driver is added as PCI device */ +#define MID_PMU_MRST_DRV_DEV_ID 0x0810 +#define MID_PMU_MFLD_DRV_DEV_ID 0x0828 + +#define PMU_DRV_NAME "intel_pmu_driver" + +#define MID_PCI_INDEX_HASH_BITS 7 /*size 128*/ +#define MID_PCI_INDEX_HASH_SIZE (1< LNG PMU1 --> LNC */ +union pmu_pm_ss_cfg { + struct { + u32 ss_0:2; /* cDmi / L1 power domain */ + u32 ss_1:2; /* SD HC0 / Display */ + u32 ss_2:2; /* SD HC1 / GFX */ + u32 ss_3:2; /* Nand / Ved */ + u32 ss_4:2; /* ISP Imaging / Vec */ + u32 ss_5:2; /* Security / Mipi */ + u32 ss_6:2; /* Display / LVDS */ + u32 ss_7:2; /* USB Host */ + u32 ss_8:2; /* USB OTG */ + u32 ss_9:2; /* Audio */ + u32 ss_10:2; /* Gpio */ + u32 ss_11:2; /* Shared SRAM */ + u32 ss_12:2; /* rsvd */ + u32 ss_13:2; /* rsvd */ + u32 ss_14:2; /* rsvd */ + u32 ss_15:2; /* rsvd */ + } pmu_pm_ss_cfg_parts; + u32 pmu_pm_ss_cfg_value; +}; + +union pmu_pm_ss_status { + struct { + u32 ss_0:2; /* cDmi / L1 power domain */ + u32 ss_1:2; /* SD HC0 / Display */ + u32 ss_2:2; /* SD HC1 / GFX */ + u32 ss_3:2; /* Nand / Ved */ + u32 ss_4:2; /* ISP Imaging / Vec */ + u32 ss_5:2; /* Security / Mipi */ + u32 ss_6:2; /* Display / LVDS */ + u32 ss_7:2; /* USB Host */ + u32 ss_8:2; /* USB OTG */ + u32 ss_9:2; /* Audio */ + u32 ss_10:2; /* Gpio */ + u32 ss_11:2; /* Shared SRAM */ + u32 ss_12:2; /* rsvd */ + u32 ss_13:2; /* rsvd */ + u32 ss_14:2; /* rsvd */ + u32 ss_15:2; /* rsvd */ + } pmu_pm_ss_status_parts; + u32 pmu_pm_ss_status_value; +}; + +union pmu_pm_status { + struct { + u32 pmu_rev:8; + u32 pmu_busy:1; + u32 mode_id:4; + u32 Reserved:19; + } pmu_status_parts; + u32 pmu_status_value; +}; + +union pmu_pm_cmd { + struct { + u32 cmd:8; + u32 ioc:1; + u32 pmu_cmd_param:23; + } pmu_pm_cmd_parts; + u32 pmu_pm_cmd_value; +}; + +struct cfg_mode_params { + u32 cfg_mode; + u32 cfg_trigger; + u32 cfg_trig_val; + u32 cfg_delay; + u32 cfg_cmbi; +}; + +/* pmu 1 pm set config parameters */ +struct pmu1_pm_set_cfg_cmd_parts { + u32 cmd:8; + u32 ioc:1; + u32 cfg_mode:4; + u32 cfg_delay:4; + u32 cfg_trigger:4; + u32 mode_id:4; + u32 rsvd:7; +}; + +/* pmu 2 pm set config parameters */ +struct cfg_delay_param_t { + u32 cmd:8; + u32 ioc:1; + u32 cfg_mode:4; + u32 mode_id:3; + u32 sys_state:3; + u32 cfg_delay:8; + u32 rsvd:5; +}; + + +struct cfg_trig_param_t { + u32 cmd:8; + u32 ioc:1; + u32 cfg_mode:4; + u32 mode_id:3; + u32 sys_state:3; + u32 cfg_trig_type:3; + u32 cfg_trig_val:8; + u32 cmbi:1; + u32 rsvd1:1; +}; + +union pmu_pm_set_cfg_cmd_t { + struct pmu1_pm_set_cfg_cmd_parts pmu1_params; + union { + struct cfg_delay_param_t d_param; + struct cfg_trig_param_t t_param; + } pmu2_params; + u32 pmu_pm_set_cfg_cmd_value; +}; + +union pmu_pm_ics { + struct { + u32 int_status:8; + u32 int_enable:1; + u32 int_pend:1; + u32 reserved:22; + } pmu_pm_ics_parts; + u32 pmu_pm_ics_value; +}; + +struct pmu_ospm_reg { + union pmu_pm_status *pm_status; + union pmu_pm_cmd *pm_cmd; + union pmu_pm_ics *pm_ics; + u32 pm_wkc; + u32 rsvd1; + u32 pm_wks; + u32 rsvd2; + union pmu_pm_ss_cfg *pm_ss_cfg; + u32 rsvd3[3]; + union pmu_pm_ss_status *pm_ss_status; + u32 rsvd4[3]; + u32 pm_wssc; + u32 rsvd5[3]; + u32 pm_c3c4_ctr; + u32 pm_c5c6_ctr; + u32 pm_msic; +}; + +struct intel_mid_base_addr { + u32 *pmu1_base; + void __iomem *pmu2_base; + u32 *pm_table_base; + u32 __iomem *offload_reg; +}; + +/*APIs to get the APM base address */ +static inline u32 MDFLD_MSG_READ32(uint port, uint offset) +{ + int mcr = (0x10<<24) | (port << 16) | (offset << 8); + uint32_t ret_val = 0; + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD0, mcr); + pci_read_config_dword(pci_root, 0xD4, &ret_val); + pci_dev_put(pci_root); + return ret_val; +} +static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value) +{ + int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD4, value); + pci_write_config_dword(pci_root, 0xD0, mcr); + pci_dev_put(pci_root); +} + +/* API used to change the platform mode */ +extern int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); +extern pci_power_t pmu_pci_choose_state(struct pci_dev *pdev); +extern bool pmu_pci_power_manageable(struct pci_dev *pdev); +extern bool pmu_pci_can_wakeup(struct pci_dev *pdev); +extern int pmu_pci_sleep_wake(struct pci_dev *pdev, bool enable); +#endif -- 2.7.4