From 335a1cc976ffbb58491a9b6dc58955349e3f0388 Mon Sep 17 00:00:00 2001 From: Andrew Vasquez Date: Tue, 8 Nov 2005 14:37:48 -0800 Subject: [PATCH] [SCSI] qla2xxx: Correct ISP24xx soft-reset handling. A driver must wait 100us before attempting an MMIO operation to the RISC after a soft-reset has been initiated. A similar delay was needed with earlier ISPs. Note: a PCI config-space read is used to flush the MMIO write to the ISP, since the ISP's state machines are unable to respond to any MMIO read during the reset process. Signed-off-by: Andrew Vasquez Signed-off-by: James Bottomley --- drivers/scsi/qla2xxx/qla_dbg.c | 8 ++++---- drivers/scsi/qla2xxx/qla_init.c | 7 ++++--- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 89793c1..5c5d231 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -970,7 +970,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) int rval; uint32_t cnt, timer; uint32_t risc_address; - uint16_t mb[4]; + uint16_t mb[4], wd; uint32_t stat; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; @@ -1514,10 +1514,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); - RD_REG_DWORD(®->ctrl_status); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + udelay(100); /* Wait for firmware to complete NVRAM accesses. */ - udelay(5); mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); for (cnt = 10000 ; cnt && mb[0]; cnt--) { udelay(5); @@ -1525,7 +1525,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) barrier(); } - udelay(20); + /* Wait for soft-reset to complete. */ for (cnt = 0; cnt < 30000; cnt++) { if ((RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET) == 0) diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 8fb084b..2d72012 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c @@ -567,6 +567,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) unsigned long flags = 0; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; uint32_t cnt, d2; + uint16_t wd; spin_lock_irqsave(&ha->hardware_lock, flags); @@ -581,10 +582,10 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); - RD_REG_DWORD(®->ctrl_status); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + udelay(100); /* Wait for firmware to complete NVRAM accesses. */ - udelay(5); d2 = (uint32_t) RD_REG_WORD(®->mailbox0); for (cnt = 10000 ; cnt && d2; cnt--) { udelay(5); @@ -592,7 +593,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) barrier(); } - udelay(20); + /* Wait for soft-reset to complete. */ d2 = RD_REG_DWORD(®->ctrl_status); for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { udelay(5); -- 2.7.4