From 3352a58ddc6e2806d1a4a9bffebc01083c5b94b1 Mon Sep 17 00:00:00 2001 From: Tilmann Scheller Date: Wed, 23 Jul 2014 12:38:17 +0000 Subject: [PATCH] [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions. The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior. llvm-svn: 213745 --- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 13 +++++++++++++ llvm/test/MC/ARM/diagnostics.s | 17 +++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index b62706c..5e074c4 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5728,6 +5728,19 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, "source operands must be sequential"); return false; } + case ARM::STR_PRE_IMM: + case ARM::STR_PRE_REG: + case ARM::STR_POST_IMM: + case ARM::STR_POST_REG: { + // Rt must be different from Rn. + const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + + if (Rt == Rn) + return Error(Operands[3]->getStartLoc(), + "source register and base register can't be identical"); + return false; + } case ARM::SBFX: case ARM::UBFX: { // Width must be in range [1, 32-lsb]. diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s index 88c5fb5..e26566d 100644 --- a/llvm/test/MC/ARM/diagnostics.s +++ b/llvm/test/MC/ARM/diagnostics.s @@ -491,3 +491,20 @@ foo2: @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: ^ + + str r0, [r0, #4]! + str r0, [r0, r1]! + str r0, [r0], #4 + str r0, [r0], r1 +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, #4]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], #4 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], r1 +@ CHECK-ERRORS: ^ -- 2.7.4