From 332ff009ffcbdad2402f089060623c0a86fa253c Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Thu, 19 Mar 2015 11:27:21 +0100 Subject: [PATCH] i965: Use 64-byte offset alignment for shader storage buffers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This should be a cacheline (64 bytes) so that we can safely have the CPU and GPU writing the same SSBO on non-cachecoherent systems (our Atom CPUs). With UBOs, the GPU never writes, so there's no problem. For an SSBO, the GPU and the CPU can be updating disjoint regions of the buffer simultaneously and that will break if the regions overlap the same cacheline. v2: - Use cacheline size (64 bytes) instead of 16 bytes (Kristian). - Update commit log and add a comment in the code explaining why we use cacheline size (Ben). Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_context.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 7c1c133..0cfc843 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -567,6 +567,15 @@ brw_initialize_context_constants(struct brw_context *brw) * However, unaligned accesses are slower, so enforce buffer alignment. */ ctx->Const.UniformBufferOffsetAlignment = 16; + + /* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so + * that we can safely have the CPU and GPU writing the same SSBO on + * non-cachecoherent systems (our Atom CPUs). With UBOs, the GPU never + * writes, so there's no problem. For an SSBO, the GPU and the CPU can + * be updating disjoint regions of the buffer simultaneously and that will + * break if the regions overlap the same cacheline. + */ + ctx->Const.ShaderStorageBufferOffsetAlignment = 64; ctx->Const.TextureBufferOffsetAlignment = 16; ctx->Const.MaxTextureBufferSize = 128 * 1024 * 1024; -- 2.7.4