From 32f6b6bff5cd6b64adf48070812f4ae7a92480e3 Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Tue, 18 Apr 2023 15:26:09 +0100 Subject: [PATCH] [AMDGPU][AsmParser] Refine parsing SDWA operands. Removes the need for the custom code in parseCustomOperand(). Reviewed By: foad Differential Revision: https://reviews.llvm.org/D147241 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 52 +++++++++------------- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 19 ++++++-- 2 files changed, 37 insertions(+), 34 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index f56c263..7a0910f 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -126,10 +126,10 @@ public: ImmTyD16, ImmTyClampSI, ImmTyOModSI, - ImmTySdwaDstSel, - ImmTySdwaSrc0Sel, - ImmTySdwaSrc1Sel, - ImmTySdwaDstUnused, + ImmTySDWADstSel, + ImmTySDWASrc0Sel, + ImmTySDWASrc1Sel, + ImmTySDWADstUnused, ImmTyDMask, ImmTyDim, ImmTyUNorm, @@ -386,10 +386,10 @@ public: bool isRowMask() const { return isImmTy(ImmTyDppRowMask); } bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } bool isFI() const { return isImmTy(ImmTyDppFi); } - bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); } - bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); } - bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); } - bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); } + bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); } + bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); } + bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); } + bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); } bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); } bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); } bool isAttrChan() const { return isImmTy(ImmTyAttrChan); } @@ -1049,10 +1049,10 @@ public: case ImmTyDppBankMask: OS << "DppBankMask"; break; case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break; case ImmTyDppFi: OS << "FI"; break; - case ImmTySdwaDstSel: OS << "SdwaDstSel"; break; - case ImmTySdwaSrc0Sel: OS << "SdwaSrc0Sel"; break; - case ImmTySdwaSrc1Sel: OS << "SdwaSrc1Sel"; break; - case ImmTySdwaDstUnused: OS << "SdwaDstUnused"; break; + case ImmTySDWADstSel: OS << "SDWADstSel"; break; + case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break; + case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break; + case ImmTySDWADstUnused: OS << "SDWADstUnused"; break; case ImmTyDMask: OS << "DMask"; break; case ImmTyDim: OS << "Dim"; break; case ImmTyUNorm: OS << "UNorm"; break; @@ -8939,7 +8939,7 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { return MatchOperand_ParseFail; } - Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused)); + Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused)); return MatchOperand_Success; } @@ -9026,14 +9026,14 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel)) addOptionalImmOperand(Inst, Operands, OptionalIdx, - AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD); + AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD); if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused)) addOptionalImmOperand(Inst, Operands, OptionalIdx, - AMDGPUOperand::ImmTySdwaDstUnused, + AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD); break; case SIInstrFlags::VOP2: @@ -9042,17 +9042,17 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod)) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD); break; case SIInstrFlags::VOPC: if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp)) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD); break; default: @@ -9155,14 +9155,6 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) { case MCK_ImmRowMask: return parseIntWithPrefix("row_mask", Operands, AMDGPUOperand::ImmTyDppRowMask); - case MCK_ImmSDWADstSel: - return parseSDWASel(Operands, "dst_sel", AMDGPUOperand::ImmTySdwaDstSel); - case MCK_ImmSDWADstUnused: - return parseSDWADstUnused(Operands); - case MCK_ImmSDWASrc0Sel: - return parseSDWASel(Operands, "src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel); - case MCK_ImmSDWASrc1Sel: - return parseSDWASel(Operands, "src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel); case MCK_tfe: return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index c0a1646..4a4ca6c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1207,6 +1207,17 @@ class NamedOperandU32Default1 : let ParserMatchClass = MatchClass; } +class SDWAOperandClass + : CustomOperandClass { + string ImmTy = "AMDGPUOperand::ImmTy"#Name; + let ParserMethod = + "[this](OperandVector &Operands) -> OperandMatchResultTy { "# + "return parseSDWASel(Operands, \""#Id#"\", "#ImmTy#"); }"; +} + +class SDWAOperand + : CustomOperand>; + let OperandType = "OPERAND_IMMEDIATE" in { def flat_offset : CustomOperand; @@ -1247,10 +1258,10 @@ def FORMAT : CustomOperand; def DMask : NamedIntOperand; def Dim : CustomOperand; -def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>; -def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>; -def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>; -def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>; +def dst_sel : SDWAOperand<"dst_sel", "SDWADstSel">; +def src0_sel : SDWAOperand<"src0_sel", "SDWASrc0Sel">; +def src1_sel : SDWAOperand<"src1_sel", "SDWASrc1Sel">; +def dst_unused : CustomOperand; def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>; def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>; -- 2.7.4