From 32af90d96f7f3c0983546a837e32da4d6029c816 Mon Sep 17 00:00:00 2001
From: Connor Abbott <cwabbott0@gmail.com>
Date: Thu, 7 Apr 2022 19:10:40 +0200
Subject: [PATCH] freedreno/a6xx: Fix SP_DS_CTRL_REG0 definition

Bit 20 isn't actually MERGEDREGS, the mode for the entire geometry
pipeline is controlled by SP_VS_CTRL_REG0::MERGEDREGS and it appears to
be something preamble-related instead since writing any register in the
preamble hangs if it's set. This fixes those hangs on freedreno and
turnip since we no longer set it.

Fixes: fccc35c2def ("ir3: Add preamble optimization pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15801>
---
 src/freedreno/registers/adreno/a6xx.xml          | 11 ++++++++---
 src/freedreno/vulkan/tu_pipeline.c               |  1 -
 src/gallium/drivers/freedreno/a6xx/fd6_program.c |  1 -
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 006bd71..fc4f60b 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2882,6 +2882,10 @@ to upconvert to 32b float internally?
 	</bitset>
 
 	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
+		<!--
+		This field actually controls all geometry stages. TCS, TES, and
+		GS must have the same mergedregs setting as VS.
+		-->
 		<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
 		<!-- ??? (blob has it set) -->
 		<bitfield name="UNK21" pos="21" type="boolean"/>
@@ -2998,7 +3002,7 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
 		<!--
-		There is no mergedregs bit, that comes from the previous stage (VS).
+		There is no mergedregs bit, that comes from the VS.
 		No idea what this bit does here.
 		-->
 		<bitfield name="UNK20" pos="20" type="boolean"/>
@@ -3024,7 +3028,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
 
 	<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
-		<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
+		<!-- There is no mergedregs bit, that comes from the VS. -->
+		<bitfield name="UNK20" pos="20" type="boolean"/> <!-- something preamble-related -->
 	</reg32>
 	<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
 
@@ -3060,7 +3065,7 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
 		<!--
-		There is no mergedregs bit, that comes from the previous stage (VS/DS).
+		There is no mergedregs bit, that comes from the VS.
 		No idea what this bit does here.
 		-->
 		<bitfield name="UNK20" pos="20" type="boolean"/>
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 428cebb..b027623 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -494,7 +494,6 @@ tu6_emit_xs(struct tu_cs *cs,
                .fullregfootprint = xs->info.max_reg + 1,
                .halfregfootprint = xs->info.max_half_reg + 1,
                .branchstack = ir3_shader_branchstack_hw(xs),
-               .mergedregs = xs->mergedregs,
       ));
       break;
    case MESA_SHADER_GEOMETRY:
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 5a0e8dd..983970f 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -713,7 +713,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
          ring,
          A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
             A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
-            COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
             A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(ds)));
 
       fd6_emit_shader(ctx, ring, ds);
-- 
2.7.4