From 328b693a199a67ce3a17d258f34d7bfd26790871 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Sat, 12 Nov 2011 02:21:44 -0800 Subject: [PATCH] i965/vs: Add support for texel offsets. The visit() half computes the values to put in the header based on the IR and simply stuffs that in the vec4_instruction; the emit() half uses this to set up the message header. This works out well since emit() can use brw_reg directly and access individual DWords without kludgery. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 18 +++++++++++++++++- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 6 +++++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index d3505c3..28da8c0 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -271,6 +271,7 @@ public: int conditional_mod; /**< BRW_CONDITIONAL_* */ int sampler; + uint32_t texture_offset; /**< Texture Offset bitfield */ int target; /**< MRT target. */ bool shadow_compare; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index c131343..b2427da 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -418,7 +418,23 @@ vec4_visitor::generate_tex(vec4_instruction *inst, assert(msg_type != -1); - if (inst->header_present) { + /* Load the message header if present. If there's a texture offset, we need + * to set it up explicitly and load the offset bitfield. Otherwise, we can + * use an implied move from g0 to the first message register. + */ + if (inst->texture_offset) { + /* Explicitly set up the message header by copying g0 to the MRF. */ + brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD), + retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + + /* Then set the offset bits in DWord 2. */ + brw_set_access_mode(p, BRW_ALIGN_1); + brw_MOV(p, + retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2), + BRW_REGISTER_TYPE_UD), + brw_imm_uw(inst->texture_offset)); + brw_set_access_mode(p, BRW_ALIGN_16); + } else if (inst->header_present) { /* Set up an implied move from g0 to the MRF. */ src = brw_vec8_grf(0, 0); } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index b49cf9c..b424a0f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1781,13 +1781,17 @@ vec4_visitor::visit(ir_texture *ir) assert(!"TXB is not valid for vertex shaders."); } - inst->header_present = intel->gen < 5; + /* Texel offsets go in the message header; Gen4 also requires headers. */ + inst->header_present = ir->offset || intel->gen < 5; inst->base_mrf = 2; inst->mlen = inst->header_present + 1; /* always at least one */ inst->sampler = sampler; inst->dst = dst_reg(this, glsl_type::get_instance(ir->type->base_type,4,1)); inst->shadow_compare = ir->shadow_comparitor != NULL; + if (ir->offset != NULL) + inst->texture_offset = brw_texture_offset(ir->offset->as_constant()); + /* MRF for the first parameter */ int param_base = inst->base_mrf + inst->header_present; -- 2.7.4