From 326594bc920bd15b19a713ef5dde404970c79b45 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 22 Apr 2018 21:37:08 +0000 Subject: [PATCH] [X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides. llvm-svn: 330558 --- llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index e0e8967..1a2fcc4 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -532,12 +532,6 @@ def : InstRW<[WriteALULd], (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; -// ANDN. -// r,r. -def : InstRW<[WriteALU], (instregex "ANDN(32|64)rr")>; -// r,m. -def : InstRW<[WriteALULd, ReadAfterLd], (instregex "ANDN(32|64)rm")>; - // Define ALU latency variants def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { let Latency = 2; -- 2.7.4