From 323b18d54b960d3ef64f60ad20838ef958334dc0 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 7 May 2021 10:37:52 +0200 Subject: [PATCH] i386: Fix up 8-byte vcond* with -mxop [PR100445] ix86_expand_sse_movcc has special TARGET_XOP handling and the recent addition of support of v*cond* patterns for MMXMODEI modes results in ICEs because the expected pattern doesn't exist. We can handle it using 128-bit vpcmov (if we ignore the upper 64 bits like we ignore in other TARGET_MMX_WITH_SSE support). 2021-05-07 Jakub Jelinek PR target/100445 * config/i386/mmx.md (*xop_pcmov_): New define_insn. * gcc.target/i386/pr100445.c: New test. --- gcc/config/i386/mmx.md | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr100445.c | 12 ++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr100445.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 347295a..295501d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1700,6 +1700,17 @@ DONE; }) +;; XOP parallel XMM conditional moves +(define_insn "*xop_pcmov_" + [(set (match_operand:MMXMODEI 0 "register_operand" "=x") + (if_then_else:MMXMODEI + (match_operand:MMXMODEI 3 "register_operand" "x") + (match_operand:MMXMODEI 1 "register_operand" "x") + (match_operand:MMXMODEI 2 "register_operand" "x")))] + "TARGET_XOP && TARGET_MMX_WITH_SSE" + "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse4arg")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral logical operations diff --git a/gcc/testsuite/gcc.target/i386/pr100445.c b/gcc/testsuite/gcc.target/i386/pr100445.c new file mode 100644 index 0000000..2f54fec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr100445.c @@ -0,0 +1,12 @@ +/* PR target/100445 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mxop" } */ + +int a, b[3]; + +void +foo (void) +{ + for (; a < 3; a++) + b[a] = (a - 1) / 2; +} -- 2.7.4