From 3229319e446cafe51e8d3060bdf39203b95a5c98 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 16 Dec 2022 02:38:00 +0200 Subject: [PATCH] drm/i915/dsb: Align DSB register writes to 8 bytes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Every DSB instruction has to be 8byte aligned. Make sure that is the case for the non-indexed register writes as well. The way this could end up unaligned is we emitted an odd number of indexed register writes beforehand. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20221216003810.13338-4-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_dsb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 90a22af..6abfd0f 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -172,6 +172,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, return; } + /* Every instruction should be 8 byte aligned. */ + dsb->free_pos = ALIGN(dsb->free_pos, 2); + dsb->ins_start_offset = dsb->free_pos; buf[dsb->free_pos++] = val; buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | -- 2.7.4