From 31dc03e21e74a5ad6d81602c8548aafb566c20e7 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 23 Aug 2022 10:05:36 +0200 Subject: [PATCH] radv: link primitive ID/clip distance shader info from the new helper MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit No functional changes. Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_pipeline.c | 29 ++++++++++------------------- src/amd/vulkan/radv_private.h | 3 ++- src/amd/vulkan/radv_shader_info.c | 38 ++++++++++++++++++++++++++++++++------ 3 files changed, 44 insertions(+), 26 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c500d6d..5f96f0c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3357,21 +3357,6 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_pass(device, stages[MESA_SHADER_FRAGMENT].nir, pipeline_layout, pipeline_key, &stages[MESA_SHADER_FRAGMENT].info); - assert(last_vgt_api_stage != MESA_SHADER_NONE); - struct radv_shader_info *pre_ps_info = &stages[last_vgt_api_stage].info; - struct radv_vs_output_info *outinfo = &pre_ps_info->outinfo; - - /* Add PS input requirements to the output of the pre-PS stage. */ - bool ps_prim_id_in = stages[MESA_SHADER_FRAGMENT].info.ps.prim_id_input; - bool ps_clip_dists_in = !!stages[MESA_SHADER_FRAGMENT].info.ps.num_input_clips_culls; - - assert(outinfo); - outinfo->export_clip_dists |= ps_clip_dists_in; - if (last_vgt_api_stage == MESA_SHADER_VERTEX || - last_vgt_api_stage == MESA_SHADER_TESS_EVAL) { - outinfo->export_prim_id |= ps_prim_id_in; - } - filled_stages |= (1 << MESA_SHADER_FRAGMENT); } @@ -3441,7 +3426,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, &stages[i].info); } - radv_nir_shader_info_link(device, pipeline_key, stages); + radv_nir_shader_info_link(device, pipeline_key, stages, last_vgt_api_stage); if (stages[MESA_SHADER_COMPUTE].nir) { unsigned subgroup_size = pipeline_key->cs.compute_subgroup_size; @@ -4177,15 +4162,21 @@ radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline, struct radv_device *device = pipeline->device; struct radv_shader_info info = {0}; - if (stages[MESA_SHADER_GEOMETRY].info.outinfo.export_clip_dists) - info.outinfo.export_clip_dists = true; - radv_nir_shader_info_pass(device, stages[MESA_SHADER_GEOMETRY].nir, pipeline_layout, pipeline_key, &info); info.wave_size = 64; /* Wave32 not supported. */ info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */ info.ballot_bit_size = 64; + if (stages[MESA_SHADER_GEOMETRY].info.outinfo.export_clip_dists) { + if (stages[MESA_SHADER_GEOMETRY].nir->info.outputs_written & VARYING_BIT_CLIP_DIST0) + info.outinfo.vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = info.outinfo.param_exports++; + if (stages[MESA_SHADER_GEOMETRY].nir->info.outputs_written & VARYING_BIT_CLIP_DIST1) + info.outinfo.vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = info.outinfo.param_exports++; + + info.outinfo.export_clip_dists = true; + } + struct radv_shader_args gs_copy_args = {0}; gs_copy_args.is_gs_copy_shader = true; gs_copy_args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 3108e00..dc5c673 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2821,7 +2821,8 @@ void radv_nir_shader_info_init(struct radv_shader_info *info); void radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key, - struct radv_pipeline_stage *stages); + struct radv_pipeline_stage *stages, + gl_shader_stage last_vgt_api_stage); bool radv_thread_trace_init(struct radv_device *device); void radv_thread_trace_finish(struct radv_device *device); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 6fb82d2..ab02a91 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -414,9 +414,7 @@ assign_outinfo_params(struct radv_vs_output_info *outinfo, uint64_t mask, { u_foreach_bit64(idx, mask) { if (idx >= VARYING_SLOT_VAR0 || idx == VARYING_SLOT_LAYER || - idx == VARYING_SLOT_PRIMITIVE_ID || idx == VARYING_SLOT_VIEWPORT || - ((idx == VARYING_SLOT_CLIP_DIST0 || idx == VARYING_SLOT_CLIP_DIST1) && - outinfo->export_clip_dists)) + idx == VARYING_SLOT_PRIMITIVE_ID || idx == VARYING_SLOT_VIEWPORT) assign_outinfo_param(outinfo, idx, total_param_exports); } } @@ -537,8 +535,6 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n /* Per-vertex outputs */ assign_outinfo_params(outinfo, per_vtx_mask, &total_param_exports); - if (outinfo->export_prim_id) - assign_outinfo_param(outinfo, VARYING_SLOT_PRIMITIVE_ID, &total_param_exports); outinfo->param_exports = total_param_exports; @@ -688,8 +684,38 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n void radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key, - struct radv_pipeline_stage *stages) + struct radv_pipeline_stage *stages, gl_shader_stage last_vgt_api_stage) { + if (stages[MESA_SHADER_FRAGMENT].nir) { + assert(last_vgt_api_stage != MESA_SHADER_NONE); + struct radv_shader_info *pre_ps_info = &stages[last_vgt_api_stage].info; + struct radv_vs_output_info *outinfo = &pre_ps_info->outinfo; + + /* Add PS input requirements to the output of the pre-PS stage. */ + bool ps_prim_id_in = stages[MESA_SHADER_FRAGMENT].info.ps.prim_id_input; + bool ps_clip_dists_in = !!stages[MESA_SHADER_FRAGMENT].info.ps.num_input_clips_culls; + + assert(outinfo); + + if (ps_prim_id_in && + (last_vgt_api_stage == MESA_SHADER_VERTEX || last_vgt_api_stage == MESA_SHADER_TESS_EVAL)) { + /* Mark the primitive ID as output when it's implicitly exported by VS or TES with NGG. */ + if (outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] == AC_EXP_PARAM_UNDEFINED) + outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = outinfo->param_exports++; + + outinfo->export_prim_id = true; + } + + if (ps_clip_dists_in) { + if (stages[last_vgt_api_stage].nir->info.outputs_written & VARYING_BIT_CLIP_DIST0) + outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = outinfo->param_exports++; + if (stages[last_vgt_api_stage].nir->info.outputs_written & VARYING_BIT_CLIP_DIST1) + outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = outinfo->param_exports++; + + outinfo->export_clip_dists = true; + } + } + if (stages[MESA_SHADER_TESS_CTRL].nir) { stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_reads_tess_factors = !!(stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read & -- 2.7.4