From 31bfad83ecff8e76e6b6c0801833c55aa157079f Mon Sep 17 00:00:00 2001
From: Qiang Yu <yuq825@gmail.com>
Date: Fri, 14 Apr 2023 15:47:10 +0800
Subject: [PATCH] aco: support 32bit address in nir_load_smem_amd

radeonsi uses 32bit address.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
---
 src/amd/compiler/aco_instruction_selection.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 7b685c3..0f09500 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -7179,6 +7179,12 @@ visit_load_smem(isel_context* ctx, nir_intrinsic_instr* instr)
    Temp base = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
    Temp offset = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
 
+   /* If base address is 32bit, convert to 64bit with the high 32bit part. */
+   if (base.bytes() == 4) {
+      base = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
+                        base, Operand::c32(ctx->options->address32_hi));
+   }
+
    aco_opcode opcode = aco_opcode::s_load_dword;
    unsigned size = 1;
 
-- 
2.7.4