From 31abe337268c5f0fe8a901c6c2d10a75718d0b81 Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Wed, 26 Nov 2014 18:55:59 +0000
Subject: [PATCH] [Hexagon] Adding and64, or64, and xor64 instructions.

llvm-svn: 222846
---
 llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 13 +++++++++++++
 llvm/test/MC/Hexagon/inst_and64.ll          | 10 ++++++++++
 llvm/test/MC/Hexagon/inst_or64.ll           | 10 ++++++++++
 llvm/test/MC/Hexagon/inst_xor64.ll          | 10 ++++++++++
 4 files changed, 43 insertions(+)
 create mode 100644 llvm/test/MC/Hexagon/inst_and64.ll
 create mode 100644 llvm/test/MC/Hexagon/inst_or64.ll
 create mode 100644 llvm/test/MC/Hexagon/inst_xor64.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 925adc5..5dfb13c 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -701,6 +701,19 @@ def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
 
+class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
+                      bit IsNeg>
+  : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
+               !if(IsNeg,"~","")>;
+
+def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
+def A2_orp  : T_ALU64_logical<"or",  0b010, 0, 1, 0>;
+def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
+
+def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
+def: Pat<(i64 (or  I64:$Rs, I64:$Rt)), (A2_orp  I64:$Rs, I64:$Rt)>;
+def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
+
 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
 // that reverse the order of the operands.
 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
diff --git a/llvm/test/MC/Hexagon/inst_and64.ll b/llvm/test/MC/Hexagon/inst_and64.ll
new file mode 100644
index 0000000..0b83074
--- /dev/null
+++ b/llvm/test/MC/Hexagon/inst_and64.ll
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = and i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 0042e0d3 00c09f52
diff --git a/llvm/test/MC/Hexagon/inst_or64.ll b/llvm/test/MC/Hexagon/inst_or64.ll
new file mode 100644
index 0000000..ea10430
--- /dev/null
+++ b/llvm/test/MC/Hexagon/inst_or64.ll
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = or i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 4042e0d3 00c09f52
diff --git a/llvm/test/MC/Hexagon/inst_xor64.ll b/llvm/test/MC/Hexagon/inst_xor64.ll
new file mode 100644
index 0000000..7f77c46
--- /dev/null
+++ b/llvm/test/MC/Hexagon/inst_xor64.ll
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = xor i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 8042e0d3 00c09f52
-- 
2.7.4