From 31a3f2aabaf832bca14ecfe6c409ca0618681ffc Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Sun, 7 Oct 2018 15:05:39 +0000 Subject: [PATCH] [x86] add tests for FP logic folding for vectors with undefs; NFC llvm-svn: 343938 --- llvm/test/CodeGen/X86/fp-logic.ll | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/llvm/test/CodeGen/X86/fp-logic.ll b/llvm/test/CodeGen/X86/fp-logic.ll index 6636271..59dbe7a 100644 --- a/llvm/test/CodeGen/X86/fp-logic.ll +++ b/llvm/test/CodeGen/X86/fp-logic.ll @@ -320,6 +320,19 @@ define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ret <4 x float> %fadd } +define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 +; CHECK-NEXT: addps %xmm1, %xmm0 +; CHECK-NEXT: retq + %bc1 = bitcast <4 x float> %y to <4 x i32> + %xor = xor <4 x i32> %bc1, + %bc2 = bitcast <4 x i32> %xor to <4 x float> + %fadd = fadd <4 x float> %x, %bc2 + ret <4 x float> %fadd +} + define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: fsub_bitcast_fneg_vec: ; CHECK: # %bb.0: @@ -332,6 +345,19 @@ define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ret <4 x float> %fsub } +define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: fsub_bitcast_fneg_vec_elts: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 +; CHECK-NEXT: subps %xmm1, %xmm0 +; CHECK-NEXT: retq + %bc1 = bitcast <4 x float> %y to <4 x i32> + %xor = xor <4 x i32> %bc1, + %bc2 = bitcast <4 x i32> %xor to <4 x float> + %fsub = fsub <4 x float> %x, %bc2 + ret <4 x float> %fsub +} + define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: fadd_bitcast_fneg_vec_width: ; CHECK: # %bb.0: -- 2.7.4