From 318b02b6b9286f7b45f2c3bef4d0630820cc742b Mon Sep 17 00:00:00 2001 From: Ken Raeburn Date: Mon, 5 Sep 1994 10:53:00 +0000 Subject: [PATCH] ARM Acorn/RISCiX target and host patches from Richard Earnshaw --- ChangeLog | 9 ++ bfd/ChangeLog | 9 ++ bfd/configure.in | 30 +++---- configure.in | 3 + gas/ChangeLog | 5 ++ gas/configure | 90 +++++++++++++------- gas/configure.in | 25 ++++-- gas/testsuite/ChangeLog | 12 +++ gas/testsuite/gas/arm/arm6.s | 13 +++ gas/testsuite/gas/arm/copro.s | 24 ++++++ gas/testsuite/gas/arm/float.s | 150 +++++++++++++++++++++++++++++++++ gas/testsuite/gas/arm/gas.exp | 14 ++++ gas/testsuite/gas/arm/inst.s | 189 ++++++++++++++++++++++++++++++++++++++++++ ld/ChangeLog | 6 ++ ld/config/riscix.mt | 1 + ld/emulparams/riscix.sh | 5 ++ ld/scripttempl/riscix.sc | 35 ++++++++ opcodes/ChangeLog | 13 ++- opcodes/arm-opc.h | 140 +++++++++++++++++++++++++++++++ 19 files changed, 722 insertions(+), 51 deletions(-) create mode 100644 gas/testsuite/gas/arm/arm6.s create mode 100644 gas/testsuite/gas/arm/copro.s create mode 100644 gas/testsuite/gas/arm/float.s create mode 100644 gas/testsuite/gas/arm/gas.exp create mode 100644 gas/testsuite/gas/arm/inst.s create mode 100644 ld/config/riscix.mt create mode 100644 ld/emulparams/riscix.sh create mode 100644 ld/scripttempl/riscix.sc create mode 100644 opcodes/arm-opc.h diff --git a/ChangeLog b/ChangeLog index 0d24de8..4623118 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,12 @@ +Mon Sep 5 05:01:30 1994 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * configure.in (arm-*-*): Don't configure ld for this target. + +Thu Sep 1 09:35:00 1994 J.T. Conklin (jtc@phishhead.cygnus.com) + + * configure.in (*-*-netware): don't configure libg++, libio, + librx, or newlib. + Wed Aug 31 13:52:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) * configure.in (alpha-dec-osf*): Use osf*, not osf1*. Don't diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 02a0860..30df05d 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,12 @@ +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * aoutx.h (NAME(aout,machine_type)): Recognize the ARM processor. + * archures.c, config.bfd, configure.host, libaout.h, reloc.c, + targets.c: Add support for the ARM. + * cpu-arm.c, riscix.c, config/riscix.mh, config/riscix.mt: New files. + + * aoutx.h (add_to_stringtabl): Check that str isn't a NULL pointer. + Fri Sep 2 14:10:30 1994 Ken Raeburn (raeburn@cujo.cygnus.com) * reloc.c (enum bfd_reloc_code_real): Rewrote definition to use diff --git a/bfd/configure.in b/bfd/configure.in index 4d911b8..4418f6a 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -32,8 +32,8 @@ fi # per-target: # Canonicalize the secondary target names. -if [ -n "$with_targets" ]; then - for targ in `echo $with_targets | sed 's/,/ /g'` +if [ -n "$enable_targets" ]; then + for targ in `echo $enable_targets | sed 's/,/ /g'` do result=`$configsub $targ 2>/dev/null` if [ -n "$result" ]; then @@ -76,11 +76,11 @@ done rm -f Makefile.tmp Makefile.2 mv Makefile Makefile.tmp -case ${with_64_bit_bfd} in +case ${enable_64_bit_bfd} in yes) want64=true ;; no | "") want64=false ;; *) - echo "*** bad value \"${with_64_bit_bfd}\" for 64-bit-bfd flag; ignored" 1>&2 + echo "*** bad value \"${enable_64_bit_bfd}\" for 64-bit-bfd flag; ignored" 1>&2 ;; esac @@ -144,12 +144,12 @@ do b_out_vec_big_host) tb="$tb bout.o aout32.o stab-syms.o" ;; b_out_vec_little_host) tb="$tb bout.o aout32.o stab-syms.o" ;; bfd_elf32_big_generic_vec) tb="$tb elf32-gen.o elf32.o elf.o" ;; - bfd_elf32_bigmips_vec) tb="$tb elf32-mips.o elf32.o elf.o" ;; + bfd_elf32_bigmips_vec) tb="$tb elf32-mips.o elf32.o elf.o ecoff.o ecofflink.o" ;; bfd_elf32_hppa_vec) tb="$tb elf32-hppa.o elf32.o elf.o" ;; bfd_elf32_i386_vec) tb="$tb elf32-i386.o elf32.o elf.o" ;; bfd_elf32_i860_vec) tb="$tb elf32-i860.o elf32.o elf.o" ;; bfd_elf32_little_generic_vec) tb="$tb elf32-gen.o elf32.o elf.o" ;; - bfd_elf32_littlemips_vec) tb="$tb elf32-mips.o elf32.o elf.o" ;; + bfd_elf32_littlemips_vec) tb="$tb elf32-mips.o elf32.o elf.o ecoff.o ecofflink.o" ;; bfd_elf32_m68k_vec) tb="$tb elf32-m68k.o elf32.o elf.o" ;; bfd_elf32_m88k_vec) tb="$tb elf32-m88k.o elf32.o elf.o" ;; bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.o elf32.o elf.o" ;; @@ -163,20 +163,18 @@ do cisco_core_vec) tb="$tb cisco-core.o" ;; demo_64_vec) tb="$tb demo64.o aout64.o stab-syms.o" target64=true ;; - ecoff_big_vec) tb="$tb coff-mips.o" ;; - ecoff_little_vec) tb="$tb coff-mips.o" ;; - ecoffalpha_little_vec) tb="$tb coff-alpha.o" + ecoff_big_vec) tb="$tb coff-mips.o ecoff.o ecofflink.o" ;; + ecoff_little_vec) tb="$tb coff-mips.o ecoff.o ecofflink.o" ;; + ecoffalpha_little_vec) tb="$tb coff-alpha.o ecoff.o ecofflink.o" target64=true ;; h8300coff_vec) tb="$tb coff-h8300.o reloc16.o" ;; h8500coff_vec) tb="$tb coff-h8500.o reloc16.o" ;; host_aout_vec) tb="$tb host-aout.o aout32.o stab-syms.o" ;; hp300bsd_vec) tb="$tb hp300bsd.o aout32.o stab-syms.o" ;; hp300hpux_vec) tb="$tb hp300hpux.o aout32.o stab-syms.o" ;; - som_vec) tb="$tb som.o" ;; i386aout_vec) tb="$tb i386aout.o aout32.o stab-syms.o" ;; i386bsd_vec) tb="$tb i386bsd.o aout32.o stab-syms.o" ;; i386dynix_vec) tb="$tb i386dynix.o aout32.o stab-syms.o" ;; - netbsd386_vec) tb="$tb netbsd386.o aout32.o stab-syms.o" ;; i386coff_vec) tb="$tb coff-i386.o" ;; i386linux_vec) tb="$tb i386linux.o aout32.o stab-syms.o" ;; i386lynx_aout_vec) tb="$tb i386lynx.o lynx-core.o aout32.o stab-syms.o" ;; @@ -191,25 +189,29 @@ do m68klynx_aout_vec) tb="$tb m68klynx.o lynx-core.o aout32.o stab-syms.o" ;; m68klynx_coff_vec) tb="$tb cf-m68klynx.o coff-m68k.o lynx-core.o stab-syms.o" ;; m88kbcs_vec) tb="$tb coff-m88k.o" ;; + netbsd386_vec) tb="$tb netbsd386.o aout32.o stab-syms.o" ;; + netbsd532_vec) tb="$tb netbsd532.o aout-ns32k.o stab-syms.o" ;; newsos3_vec) tb="$tb newsos3.o aout32.o stab-syms.o" ;; nlm32_i386_vec) tb="$tb nlm32-i386.o nlm32.o nlm.o" ;; nlm32_sparc_vec) tb="$tb nlm32-sparc.o nlm32.o nlm.o" ;; nlm32_alpha_vec) tb="$tb nlm32-alpha.o nlm32.o nlm.o" target64=true ;; + riscix_vec) tb="$tb aout32.o riscix.o stab-syms.o" ;; nlm32_powerpc_vec) tb="$tb nlm32-ppc.o nlm32.o nlm.o" ;; + pc532machaout_vec) tb="$tb pc532-mach.o aout-ns32k.o stab-syms.o" ;; rs6000coff_vec) tb="$tb coff-rs6000.o" ;; shcoff_vec) tb="$tb coff-sh.o reloc16.o" ;; + som_vec) tb="$tb som.o" ;; sparclynx_aout_vec) tb="$tb sparclynx.o lynx-core.o aout32.o stab-syms.o" ;; sparclynx_coff_vec) tb="$tb cf-sparclynx.o lynx-core.o stab-syms.o" ;; sparccoff_vec) tb="$tb coff-sparc.o" ;; + srec_vec) tb="$tb srec.o" ;; sunos_big_vec) tb="$tb sunos.o aout32.o stab-syms.o" ;; + symbolsrec_vec) tb="$tb srec.o" ;; tekhex_vec) tb="$tb tekhex.o" ;; we32kcoff_vec) tb="$tb coff-we32k.o" ;; z8kcoff_vec) tb="$tb coff-z8k.o reloc16.o" ;; - srec_vec) tb="$tb srec.o" ;; - symbolsrec_vec) tb="$tb srec.o" ;; - "") ;; *) echo "*** unknown target vector $vec" 1>&2; exit 1 ;; esac diff --git a/configure.in b/configure.in index 6948bc1..1d13162 100644 --- a/configure.in +++ b/configure.in @@ -314,6 +314,9 @@ case "${target}" in # newlib is not 64 bit ready noconfigdirs="$noconfigdirs newlib" ;; + arm-*-*) + noconfigdirs="$noconfigdirs ld" + ;; h8300*-*-* | \ h8500-*-*) noconfigdirs="$noconfigdirs libg++ libio librx" diff --git a/gas/ChangeLog b/gas/ChangeLog index 22c0503..0e5159b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * config/ho-riscix.h, config/tc-arm.c, config/tc-arm.h: New files + * configure.in: Recognize the arm. + Fri Sep 2 16:05:50 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) * ecoff.c (add_file): Don't try to generate line numbers if the diff --git a/gas/configure b/gas/configure index 36f69bc..56ccb53 100755 --- a/gas/configure +++ b/gas/configure @@ -171,11 +171,14 @@ EOF -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) prefix="$ac_optarg" ;; + # The program_*_given variables are so we can distinguish between + # unspecified and empty-string-valued options. -program-prefix | --program-prefix | --program-prefi | --program-pref \ | --program-pre | --program-pr | --program-p) ac_prev=program_prefix ;; -program-prefix=* | --program-prefix=* | --program-prefi=* \ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) + program_prefix_given=yes program_prefix="$ac_optarg" ;; -program-suffix | --program-suffix | --program-suffi | --program-suff \ @@ -183,6 +186,7 @@ EOF ac_prev=program_suffix ;; -program-suffix=* | --program-suffix=* | --program-suffi=* \ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) + program_suffix_given=yes program_suffix="$ac_optarg" ;; -program-transform-name | --program-transform-name \ @@ -200,7 +204,10 @@ EOF | --program-transfo=* | --program-transf=* \ | --program-trans=* | --program-tran=* \ | --progr-tra=* | --program-tr=* | --program-t=*) - program_transform_name="$ac_optarg" ;; + # Double any backslashes or dollar signs in the argument + program_transform_name_given=yes + program_transform_name="${program_transform_name} -e `echo ${ac_optarg} | sed -e 's/\\\\/\\\\\\\\/g' -e 's/\\\$/$$/g'`" + ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil) @@ -393,12 +400,13 @@ ac_compile='${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS conftest.${ac_ext} -o conftest $ bfd_gas=no +user_bfd_gas= # Check whether --enable-bfd-assembler or --disable-bfd-assembler was given. enableval="$enable_bfd_assembler" if test -n "$enableval"; then case "${enableval}" in - yes) need_bfd=yes bfd_gas=yes ;; - no) ;; + yes) need_bfd=yes user_bfd_gas=yes ;; + no) user_bfd_gas=no ;; *) { echo "configure: bad value ${enableval} given for bfd-assembler option" 1>&2; exit 1; } ;; esac fi @@ -510,6 +518,22 @@ esac echo "$ac_t""$build" 1>&4 +if [ "${host_alias}" != "${target_alias}" ] ; then + if [ "${program_prefix_given}${program_suffix_given}${program_transform_name_given}" = "" ] ; then + program_prefix=${target_alias}- ; + fi +fi + +# Merge program_prefix and program_suffix onto program_transform_name +# Use a double $ so that make ignores it +if [ "${program_suffix}" != "" ] ; then + program_transform_name="-e s,\$\$,${program_suffix}, ${program_transform_name}" +fi + +if [ "${program_prefix}" != "" ] ; then + program_transform_name="-e s,^,${program_prefix}, ${program_transform_name}" +fi + emulation=generic @@ -557,6 +581,8 @@ case ${generic_target} in alpha-*-netware*) obj_format=ecoff ;; alpha-*-osf*) obj_format=ecoff ;; + arm-*-riscix*) obj_format=aout bfd_gas=yes ;; + hppa-*-*elf*) obj_format=elf emulation=hppa ;; hppa-*-osf*) obj_format=som emulation=hppa ;; hppa-*-hpux*) obj_format=som emulation=hppa ;; @@ -573,7 +599,7 @@ case ${generic_target} in i386-*-linux*elf*) obj_format=elf emulation=linux ;; i386-*-linux*coff*) obj_format=coff emulation=linux gas_target=i386coff ;; - i386-*-linux*) obj_format=aout emulation=linux ;; + i386-*-linux*) obj_format=aout emulation=linux bfd_gas=preferred ;; i386-*-lynxos*) obj_format=coff gas_target=i386coff emulation=lynx ;; i386-*-sysv4* | i386-*-solaris* | i386-*-elf) @@ -694,20 +720,16 @@ fi target_frag=${srcdir}/config/${gas_target}.mt -case ${bfd_gas}-${obj_format} in - yes-coff) need_bfd=yes ;; - no-coff) need_bfd=yes - cat >> confdefs.h <<\EOF -#define MANY_SEGMENTS 1 -EOF - ;; +case ${cpu_type}-${obj_format} in +# not yet +# i386-aout) bfd_gas=preferred ;; *-elf) bfd_gas=yes ;; *-ecoff) bfd_gas=yes ;; *-som) bfd_gas=yes ;; *) ;; esac -case ${with_bfd_assembler}-${bfd_gas} in +case ${user_bfd_gas}-${bfd_gas} in yes-yes | no-no) # We didn't override user's choice. ;; @@ -725,6 +747,15 @@ case ${with_bfd_assembler}-${bfd_gas} in ;; esac +case ${bfd_gas}-${cpu_type}-${obj_format} in + yes-*-coff) need_bfd=yes ;; + no-*-coff) need_bfd=yes + cat >> confdefs.h <<\EOF +#define MANY_SEGMENTS 1 +EOF + ;; +esac + reject_dev_configs=yes case ${reject_dev_configs}-${dev} in @@ -881,7 +912,7 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.${ac_ext} < Syntax Error @@ -894,7 +925,7 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.${ac_ext} < Syntax Error @@ -924,7 +955,7 @@ if eval "test \"`echo '${'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&4 else cat > conftest.${ac_ext} < EOF @@ -961,7 +992,7 @@ else { echo "configure: can not run test program while cross compiling" 1>&2; exit 1; } else cat > conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} < int main() { return 0; } @@ -1015,7 +1046,7 @@ if eval "test \"`echo '${'ac_cv_func_alloca'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&4 else cat > conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} < /* Arbitrary system header to define __stub macros. */ int main() { return 0; } @@ -1141,7 +1172,7 @@ if eval "test \"`echo '${'ac_cv_func_GETB67'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&4 else cat > conftest.${ac_ext} < /* Arbitrary system header to define __stub macros. */ int main() { return 0; } @@ -1182,7 +1213,7 @@ if eval "test \"`echo '${'ac_cv_func_getb67'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&4 else cat > conftest.${ac_ext} < /* Arbitrary system header to define __stub macros. */ int main() { return 0; } @@ -1236,7 +1267,7 @@ ac_cv_c_stack_direction=0 else cat > conftest.${ac_ext} < conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} < #include @@ -1356,7 +1387,7 @@ if eval "test \"`echo '${'gas_cv_malloc_decl_needed'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&4 else cat > conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} <&4 else cat > conftest.${ac_ext} <d print the bitfield in decimal + %x print the bitfield in hex + %r print as an ARM register + %f print a floating point constant if >7 else an fp register + %c print condition code (always bits 28-31) + %P print floating point precision in arithmetic insn + %Q print floating point precision in ldf/stf insn + %R print floating point rounding mode + %'c print specified char iff bit is one + %`c print specified char iff bit is zero + %?ab print a if bit is one else print b + %p print 'p' iff bits 12-15 are 15 + %t print 't' iff bit 21 set and bit 24 clear + %o print operand2 (immediate or register + shift) + %a print address for ldr/str instruction + %b print branch destination + %A print address for ldc/stc/ldf/stf instruction + %m print register mask for ldm/stm instruction + %C print the PSR sub type. + %F print the COUNT field of a LFM/SFM instruction. +*/ + +static struct arm_opcode arm_opcodes[] = { + /* ARM instructions */ + {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, + {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, + {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, + {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, + {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, + {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, + {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, + {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, + {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, + {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, + {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"}, + {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"}, + {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, + {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, + {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, + {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, + {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, + {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, + {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, + {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, + {0x04000000, 0x0c100000, "str%c%22'b%t\t%12-15r, %a"}, + {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, + {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"}, + {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"}, + {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, + + /* Floating point coprocessor instructions */ + {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, + {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, + {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, + {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, + {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, + {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, + {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, + {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, + {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, + {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, + {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, + {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, + {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, + {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, + {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, + {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, + {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, + {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, + {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, + {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, + {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, + {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, + {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, + {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, + {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, + {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, + {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, + {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, + {0x0d000200, 0x0f900fff, "sfm%cfd\t%12-14f, %F, [%16-19r]%21'!"}, + {0x0c900200, 0x0f900fff, "lfm%cfd\t%12-14f, %F, [%16-19r]%21'!"}, + {0x0c800200, 0x0f900fff, "sfm%cea\t%12-14f, %F, [%16-19r]%21'!"}, + {0x0d100200, 0x0f900fff, "lfm%cea\t%12-14f, %F, [%16-19r]%21'!"}, + {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, + {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + + /* Generic coprocessor instructions */ + {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0c000000, 0x0e100000, "stc%c%22`l\t%8-11d, cr%12-15d, %A"}, + {0x0c100000, 0x0e100000, "ldc%c%22`l\t%8-11d, cr%12-15d, %A"}, + /* the rest */ + {0x00000000, 0x00000000, "undefined instruction %0-31x"}, + {0x00000000, 0x00000000, 0} +}; + +#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) -- 2.7.4