From 30e0b25bc7c286c9711d54a0a17e6b9e38fefdb6 Mon Sep 17 00:00:00 2001 From: Dietmar Eggemann Date: Wed, 30 Aug 2017 15:41:19 +0100 Subject: [PATCH] ARM: dts: exynos: add exynos5422 cpu capacity-dmips-mhz information MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platforms are affected once cpu-invariant accounting support is re-connected to the task scheduler: odroidxu3, odroidxu3-lite, odroidxu4 Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Dietmar Eggemann Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index c8afdf8..1ef8464 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -33,6 +33,7 @@ cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu1: cpu@101 { @@ -43,6 +44,7 @@ cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu2: cpu@102 { @@ -53,6 +55,7 @@ cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu3: cpu@103 { @@ -63,6 +66,7 @@ cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu4: cpu@0 { @@ -74,6 +78,7 @@ cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu5: cpu@1 { @@ -84,6 +89,7 @@ cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu6: cpu@2 { @@ -94,6 +100,7 @@ cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu7: cpu@3 { @@ -104,6 +111,7 @@ cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; }; }; -- 2.7.4