From 309206667d881ddfeaa2961f330043352ea92b04 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Fri, 16 Aug 2013 12:52:08 +0000 Subject: [PATCH] When initializing the PIC global base register on ARM/ELF add pc to fix the address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551 --- llvm/lib/Target/ARM/ARMInstrInfo.cpp | 4 ++++ llvm/test/CodeGen/ARM/fast-isel-pic.ll | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index 8cdb8536..868dd47 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -130,6 +130,10 @@ namespace { MIB.addImm(0); AddDefaultPred(MIB); + // Fix the GOT address by adding pc. + BuildMI(FirstMBB, MBBI, DL, TII.get(ARM::tPICADD), GlobalBaseReg) + .addReg(GlobalBaseReg).addImm(ARMPCLabelIndex); + return true; } diff --git a/llvm/test/CodeGen/ARM/fast-isel-pic.ll b/llvm/test/CodeGen/ARM/fast-isel-pic.ll index ad0f159..e3e5972 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-pic.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-pic.ll @@ -25,6 +25,8 @@ entry: ; ARMv7: add [[reg2]], pc, [[reg2]] ; ARMv7-ELF: LoadGV ; ARMv7-ELF: ldr r[[reg2:[0-9]+]], +; ARMv7-ELF: .LPC +; ARMv7-ELF-NEXT: add r[[reg2]], pc ; ARMv7-ELF: ldr r[[reg3:[0-9]+]], ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] %tmp = load i32* @g @@ -54,6 +56,8 @@ entry: ; ARMv7: ldr r[[reg5]], [r[[reg5]]] ; ARMv7-ELF: LoadIndirectSymbol ; ARMv7-ELF: ldr r[[reg5:[0-9]+]], +; ARMv7-ELF: .LPC +; ARMv7-ELF-NEXT: add r[[reg5]], pc ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] %tmp = load i32* @i -- 2.7.4