From 3084eb0011b38cceaafb9312ad90fe20d343daa7 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 12 Mar 2018 18:25:15 +0800 Subject: [PATCH] drm/amdgpu/soc15: initialize reg base for vega12 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Initialize the IP offsets for vega12. Acked-by: Christian König Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index e308c3c..51cf8a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -508,6 +508,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) /* Set IP register base before any HW register access */ switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_VEGA12: case CHIP_RAVEN: vega10_reg_base_init(adev); break; -- 2.7.4