From 30371df85f3e6fc2352647566f92c9079f77b2c7 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 21 Jul 2020 06:49:04 +0100 Subject: [PATCH] [ARM] More unpredictable VCVT instructions. These extra vcvt instructions were missed from 74ca67c109 because they live in a different Domain, but should be treated in the same way. Differential Revision: https://reviews.llvm.org/D83204 --- llvm/lib/Target/ARM/ARMInstrVFP.td | 2 ++ llvm/test/CodeGen/Thumb2/mve-vcvt.ll | 4 ++-- llvm/unittests/Target/ARM/MachineInstrTest.cpp | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 8a652c1..aea137a 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -1551,6 +1551,8 @@ class AVConv1InsS_Encode opcod1, bits<2> opcod2, bits<4> opcod3, let Inst{5} = Sm{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; + + let hasSideEffects = 0; } class AVConv1IsH_Encode opcod1, bits<2> opcod2, bits<4> opcod3, diff --git a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll index ddc36f3..831ca04 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll @@ -45,8 +45,8 @@ define arm_aapcs_vfpcc <4 x i32> @foo_int32_float(<4 x float> %src) { ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1 -; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s2 +; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov.32 q0[0], r0 ; CHECK-MVE-NEXT: vmov r0, s6 @@ -71,8 +71,8 @@ define arm_aapcs_vfpcc <4 x i32> @foo_uint32_float(<4 x float> %src) { ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1 -; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s2 +; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 ; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov.32 q0[0], r0 ; CHECK-MVE-NEXT: vmov r0, s6 diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp index 3e5403f..792a15d 100644 --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -1103,8 +1103,8 @@ TEST(MachineInstr, HasSideEffects) { for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) { const MCInstrDesc &Desc = TII->get(Op); - if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE && - (Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainVFP) + if ((Desc.TSFlags & + (ARMII::DomainMVE | ARMII::DomainVFP | ARMII::DomainNEONA8)) == 0) continue; if (UnpredictableOpcodes.count(Op)) continue; -- 2.7.4