From 3033f80af5dbc0858907df3c41ccf7b9de8a01a4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 25 Apr 2014 11:36:38 -0700 Subject: [PATCH] i965: Move intel_region_get_aligned_offset() to be a miptree function. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit All the consumers are doing it on a miptree. v2: fix a silly duplicated dereference (review by Ken) Reviewed-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg (v1) Reviewed-by: Chad Versace (v1) --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 7 ++-- src/mesa/drivers/dri/i965/brw_misc_state.c | 17 +++++----- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 18 +++++----- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 49 ++++++++++++++++++++++++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 +++ src/mesa/drivers/dri/i965/intel_regions.c | 42 ----------------------- src/mesa/drivers/dri/i965/intel_regions.h | 4 --- 7 files changed, 69 insertions(+), 72 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 121fe15..b800403 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -139,7 +139,6 @@ uint32_t brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const { - struct intel_region *region = mt->region; uint32_t mask_x, mask_y; intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled); @@ -147,9 +146,9 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, *tile_x = x_offset & mask_x; *tile_y = y_offset & mask_y; - return intel_region_get_aligned_offset(region, x_offset & ~mask_x, - y_offset & ~mask_y, - map_stencil_as_y_tiled); + return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x, + y_offset & ~mask_y, + map_stencil_as_y_tiled); } diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index aafb3fe..8756428 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -446,17 +446,16 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, depth_mt = depth_irb->mt; brw->depthstencil.depth_mt = depth_mt; brw->depthstencil.depth_offset = - intel_region_get_aligned_offset(depth_mt->region, - depth_irb->draw_x & ~tile_mask_x, - depth_irb->draw_y & ~tile_mask_y, - false); + intel_miptree_get_aligned_offset(depth_mt, + depth_irb->draw_x & ~tile_mask_x, + depth_irb->draw_y & ~tile_mask_y, + false); if (intel_renderbuffer_has_hiz(depth_irb)) { brw->depthstencil.hiz_offset = - intel_region_get_aligned_offset(depth_mt->region, - depth_irb->draw_x & ~tile_mask_x, - (depth_irb->draw_y & ~tile_mask_y) / - 2, - false); + intel_miptree_get_aligned_offset(depth_mt, + depth_irb->draw_x & ~tile_mask_x, + (depth_irb->draw_y & ~tile_mask_y) / 2, + false); } } if (stencil_irb) { diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 4222fa8..903cb78 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -804,9 +804,9 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t tile_x = draw_x & tile_mask_x; uint32_t tile_y = draw_y & tile_mask_y; uint32_t offset = - intel_region_get_aligned_offset(params->depth.mt->region, - draw_x & ~tile_mask_x, - draw_y & ~tile_mask_y, false); + intel_miptree_get_aligned_offset(params->depth.mt, + draw_x & ~tile_mask_x, + draw_y & ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth @@ -856,16 +856,16 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, /* 3DSTATE_HIER_DEPTH_BUFFER */ { - struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; + struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt; uint32_t hiz_offset = - intel_region_get_aligned_offset(hiz_region, - draw_x & ~tile_mask_x, - (draw_y & ~tile_mask_y) / 2, false); + intel_miptree_get_aligned_offset(hiz_mt, + draw_x & ~tile_mask_x, + (draw_y & ~tile_mask_y) / 2, false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_region->pitch - 1); - OUT_RELOC(hiz_region->bo, + OUT_BATCH(hiz_mt->region->pitch - 1); + OUT_RELOC(hiz_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, hiz_offset); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 2802043..63b80bd 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -977,7 +977,7 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, /** * This function computes masks that may be used to select the bits of the X - * and Y coordinates that indicate the offset within a tile. If the region is + * and Y coordinates that indicate the offset within a tile. If the BO is * untiled, the masks are set to 0. */ void @@ -1009,6 +1009,49 @@ intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt, } /** + * Compute the offset (in bytes) from the start of the BO to the given x + * and y coordinate. For tiled BOs, caller must ensure that x and y are + * multiples of the tile size. + */ +uint32_t +intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, + uint32_t x, uint32_t y, + bool map_stencil_as_y_tiled) +{ + int cpp = mt->region->cpp; + uint32_t pitch = mt->region->pitch; + uint32_t tiling = mt->region->tiling; + + if (map_stencil_as_y_tiled) { + tiling = I915_TILING_Y; + + /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile + * gets transformed into a 32-high Y-tile. Accordingly, the pitch of + * the resulting surface is twice the pitch of the original miptree, + * since each row in the Y-tiled view corresponds to two rows in the + * actual W-tiled surface. So we need to correct the pitch before + * computing the offsets. + */ + pitch *= 2; + } + + switch (tiling) { + default: + assert(false); + case I915_TILING_NONE: + return y * pitch + x * cpp; + case I915_TILING_X: + assert((x % (512 / cpp)) == 0); + assert((y % 8) == 0); + return y * pitch + x / (512 / cpp) * 4096; + case I915_TILING_Y: + assert((x % (128 / cpp)) == 0); + assert((y % 32) == 0); + return y * pitch + x / (128 / cpp) * 4096; + } +} + +/** * Rendering with tiled buffers requires that the base address of the buffer * be aligned to a page boundary. For renderbuffers, and sometimes with * textures, we may want the surface to point at a texture image level that @@ -1024,7 +1067,6 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t *tile_x, uint32_t *tile_y) { - const struct intel_region *region = mt->region; uint32_t x, y; uint32_t mask_x, mask_y; @@ -1034,8 +1076,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, *tile_x = x & mask_x; *tile_y = y & mask_y; - return intel_region_get_aligned_offset(region, x & ~mask_x, y & ~mask_y, - false); + return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, false); } static void diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index d09d09b..d76c0cd 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -546,6 +546,10 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, GLuint level, GLuint slice, uint32_t *tile_x, uint32_t *tile_y); +uint32_t +intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, + uint32_t x, uint32_t y, + bool map_stencil_as_y_tiled); void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, GLuint level, diff --git a/src/mesa/drivers/dri/i965/intel_regions.c b/src/mesa/drivers/dri/i965/intel_regions.c index a8d16cd..2fc57ed 100644 --- a/src/mesa/drivers/dri/i965/intel_regions.c +++ b/src/mesa/drivers/dri/i965/intel_regions.c @@ -276,45 +276,3 @@ intel_region_release(struct intel_region **region_handle) } *region_handle = NULL; } - -/** - * Compute the offset (in bytes) from the start of the region to the given x - * and y coordinate. For tiled regions, caller must ensure that x and y are - * multiples of the tile size. - */ -uint32_t -intel_region_get_aligned_offset(const struct intel_region *region, uint32_t x, - uint32_t y, bool map_stencil_as_y_tiled) -{ - int cpp = region->cpp; - uint32_t pitch = region->pitch; - uint32_t tiling = region->tiling; - - if (map_stencil_as_y_tiled) { - tiling = I915_TILING_Y; - - /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile - * gets transformed into a 32-high Y-tile. Accordingly, the pitch of - * the resulting region is twice the pitch of the original region, since - * each row in the Y-tiled view corresponds to two rows in the actual - * W-tiled surface. So we need to correct the pitch before computing - * the offsets. - */ - pitch *= 2; - } - - switch (tiling) { - default: - assert(false); - case I915_TILING_NONE: - return y * pitch + x * cpp; - case I915_TILING_X: - assert((x % (512 / cpp)) == 0); - assert((y % 8) == 0); - return y * pitch + x / (512 / cpp) * 4096; - case I915_TILING_Y: - assert((x % (128 / cpp)) == 0); - assert((y % 32) == 0); - return y * pitch + x / (128 / cpp) * 4096; - } -} diff --git a/src/mesa/drivers/dri/i965/intel_regions.h b/src/mesa/drivers/dri/i965/intel_regions.h index ff7a5f0..c4dd243 100644 --- a/src/mesa/drivers/dri/i965/intel_regions.h +++ b/src/mesa/drivers/dri/i965/intel_regions.h @@ -103,10 +103,6 @@ void intel_region_reference(struct intel_region **dst, void intel_region_release(struct intel_region **ib); -uint32_t -intel_region_get_aligned_offset(const struct intel_region *region, uint32_t x, - uint32_t y, bool map_stencil_as_y_tiled); - /** * Used with images created with image_from_names * to help support planar images. -- 2.7.4