From 30211d5f13d7d32c1d271b887ff4e6a6381c75db Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 21 Jun 2023 14:59:01 +0900 Subject: [PATCH] drm/verisilicon: hdmi: Add feature to check cea mode There is a problem with output for modes that are not supported, and due to this, the hdmi sound is not played. Add feature to check cea mode. Change-Id: I55e3daa4e6e98f6df26bf91de84c099077e7f339 Signed-off-by: Hoegeun Kwon --- drivers/gpu/drm/verisilicon/starfive_hdmi.c | 46 ++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/verisilicon/starfive_hdmi.c b/drivers/gpu/drm/verisilicon/starfive_hdmi.c index ccd307b..907831b 100644 --- a/drivers/gpu/drm/verisilicon/starfive_hdmi.c +++ b/drivers/gpu/drm/verisilicon/starfive_hdmi.c @@ -388,6 +388,34 @@ static int starfive_hdmi_config_video_timing(struct starfive_hdmi *hdmi, return 0; } +static void starfive_hdmi_improve_eye_diagram(struct starfive_hdmi *hdmi) +{ + switch (hdmi->hdmi_data.vic) { + case 95: + case 94: + case 93: + hdmi_writeb(hdmi, 0x100, 0x00); + hdmi_writeb(hdmi, 0x1bb, 0x40); + hdmi_writeb(hdmi, 0x1bc, 0x40); + hdmi_writeb(hdmi, 0x1bd, 0x40); + hdmi_writeb(hdmi, 0x1bf, 0x02); + hdmi_writeb(hdmi, 0x1c0, 0x22); + break; + case 16: + case 31: + hdmi_writeb(hdmi, 0x1bf, 0x02); + hdmi_writeb(hdmi, 0x1c0, 0x22); + break; + case 4: + case 3: + case 1: + hdmi_writeb(hdmi, 0x1bf, 0x00); + hdmi_writeb(hdmi, 0x1c0, 0x00); + break; + + } +} + static int starfive_hdmi_setup(struct starfive_hdmi *hdmi, struct drm_display_mode *mode) { @@ -408,6 +436,8 @@ static int starfive_hdmi_setup(struct starfive_hdmi *hdmi, /*turn on serializer*/ hdmi_writeb(hdmi, STARFIVE_SERIALIER_CONTROL, STARFIVE_SERIALIER_ENABLE); + starfive_hdmi_improve_eye_diagram(hdmi); + starfive_hdmi_tx_phy_power_down(hdmi); starfive_hdmi_config_video_timing(hdmi, mode); starfive_hdmi_tx_phy_power_on(hdmi); @@ -511,21 +541,29 @@ starfive_hdmi_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { const struct pre_pll_config *cfg = pre_pll_cfg_table; + u32 vic = drm_match_cea_mode(mode); int pclk = mode->clock * 1000; bool valid = false; int i; + + if (pclk > 297000000) + return MODE_BAD; + for (i = 0; cfg[i].pixclock != (~0UL); i++) { if (pclk == cfg[i].pixclock) { - if (pclk > 297000000) - continue; - valid = true; break; } } - return (valid) ? MODE_OK : MODE_BAD; + if (!valid) + return MODE_BAD; + + if (vic >= 1) + return MODE_OK; + else + return MODE_BAD; } static int -- 2.7.4