From 2f772dd67b353ecd9de7c6c7cbd7e94025b34428 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 17 Jul 2012 14:18:54 +0800 Subject: [PATCH] s/flag_reg_nr/flag_subreg_nr for an instruction s/flagreg/flag_subreg_nr for a condition They are flag subregister number indeed Signed-off-by: Xiang, Haihao --- assembler/src/brw_structs.h | 8 ++++---- assembler/src/disasm.c | 4 ++-- assembler/src/gen4asm.h | 2 +- assembler/src/gram.y | 22 +++++++++++----------- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h index 25e7eb4..543150a 100644 --- a/assembler/src/brw_structs.h +++ b/assembler/src/brw_structs.h @@ -1134,7 +1134,7 @@ struct brw_instruction GLuint src0_horiz_stride:2; /* 0x00030000 */ GLuint src0_width:3; /* 0x001c0000 */ GLuint src0_vert_stride:4; /* 0x01e00000 */ - GLuint flag_reg_nr:1; /* 0x02000000 */ + GLuint flag_subreg_nr:1; /* 0x02000000 */ GLuint pad:6; /* 0xfc000000 */ } da1; @@ -1148,7 +1148,7 @@ struct brw_instruction GLuint src0_horiz_stride:2; GLuint src0_width:3; GLuint src0_vert_stride:4; - GLuint flag_reg_nr:1; + GLuint flag_subreg_nr:1; GLuint pad:6; } ia1; @@ -1165,7 +1165,7 @@ struct brw_instruction GLuint src0_swz_w:2; GLuint pad0:1; GLuint src0_vert_stride:4; - GLuint flag_reg_nr:1; + GLuint flag_subreg_nr:1; GLuint pad1:6; } da16; @@ -1182,7 +1182,7 @@ struct brw_instruction GLuint src0_swz_w:2; GLuint pad0:1; GLuint src0_vert_stride:4; - GLuint flag_reg_nr:1; + GLuint flag_subreg_nr:1; GLuint pad1:6; } ia16; diff --git a/assembler/src/disasm.c b/assembler/src/disasm.c index efba364..9d9dfac 100644 --- a/assembler/src/disasm.c +++ b/assembler/src/disasm.c @@ -780,8 +780,8 @@ int disasm (FILE *file, struct brw_instruction *inst) string (file, "("); err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); string (file, "f0"); - if (inst->bits2.da1.flag_reg_nr) - format (file, ".%d", inst->bits2.da1.flag_reg_nr); + if (inst->bits2.da1.flag_subreg_nr) + format (file, ".%d", inst->bits2.da1.flag_subreg_nr); if (inst->header.access_mode == BRW_ALIGN_1) err |= control (file, "predicate control align1", pred_ctrl_align1, inst->header.predicate_control, NULL); diff --git a/assembler/src/gen4asm.h b/assembler/src/gen4asm.h index 620d433..5dccaba 100644 --- a/assembler/src/gen4asm.h +++ b/assembler/src/gen4asm.h @@ -49,7 +49,7 @@ struct direct_reg { struct condition { int cond; - int flagreg; + int flag_subreg_nr; }; struct region { diff --git a/assembler/src/gram.y b/assembler/src/gram.y index 0845777..022fca1 100644 --- a/assembler/src/gram.y +++ b/assembler/src/gram.y @@ -389,8 +389,8 @@ unaryinstruction: if (set_instruction_src0(&$$, &$7) != 0) YYERROR; - if ($3.flagreg != -1) - $$.bits2.da1.flag_reg_nr = $3.flagreg; + if ($3.flag_subreg_nr != -1) + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; if (gen_level < 6 && get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) @@ -419,8 +419,8 @@ binaryinstruction: if (set_instruction_src1(&$$, &$8) != 0) YYERROR; - if ($3.flagreg != -1) - $$.bits2.da1.flag_reg_nr = $3.flagreg; + if ($3.flag_subreg_nr != -1) + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; if (gen_level < 6 && get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) @@ -449,8 +449,8 @@ binaryaccinstruction: if (set_instruction_src1(&$$, &$8) != 0) YYERROR; - if ($3.flagreg != -1) - $$.bits2.da1.flag_reg_nr = $3.flagreg; + if ($3.flag_subreg_nr != -1) + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; if (gen_level < 6 && get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) @@ -2291,7 +2291,7 @@ imm32: exp { $$.r = imm32_d; $$.u.d = $1; } predicate: /* empty */ { $$.header.predicate_control = BRW_PREDICATE_NONE; - $$.bits2.da1.flag_reg_nr = 0; + $$.bits2.da1.flag_subreg_nr = 0; $$.header.predicate_inverse = 0; } | LPAREN predstate flagreg predctrl RPAREN @@ -2301,7 +2301,7 @@ predicate: /* empty */ * set a predicate for one flag register and conditional * modification on the other flag register. */ - $$.bits2.da1.flag_reg_nr = $3.subreg_nr; + $$.bits2.da1.flag_subreg_nr = $3.subreg_nr; $$.header.predicate_inverse = $2; } ; @@ -2360,12 +2360,12 @@ saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; } conditionalmodifier: condition { $$.cond = $1; - $$.flagreg = -1; + $$.flag_subreg_nr = -1; } | condition DOT flagreg { $$.cond = $1; - $$.flagreg = $3.subreg_nr; + $$.flag_subreg_nr = $3.subreg_nr; } condition: /* empty */ { $$ = BRW_CONDITIONAL_NONE; } @@ -2848,7 +2848,7 @@ void set_instruction_predicate(struct brw_instruction *instr, { instr->header.predicate_control = predicate->header.predicate_control; instr->header.predicate_inverse = predicate->header.predicate_inverse; - instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr; + instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr; } void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, -- 2.7.4