From 2ed9b74e98c6db928900ec8b50c0545e14ef89f8 Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Thu, 27 Sep 2018 14:13:06 +0800 Subject: [PATCH] lcd: add tl1 support [1/1] PD#172587 Problem: not support tl1 Solution: add tl1 support Verify: test pass on PTM Change-Id: I5a9073fc08a98ae95d4961297a7427864d92279b Signed-off-by: Evoke Zhang --- MAINTAINERS | 7 + arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi | 92 + arch/arm/boot/dts/amlogic/tl1_pxp.dts | 6 + drivers/amlogic/media/vout/lcd/Makefile | 4 +- drivers/amlogic/media/vout/lcd/lcd_clk_config.c | 3137 +- drivers/amlogic/media/vout/lcd/lcd_clk_config.h | 381 +- drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h | 417 + drivers/amlogic/media/vout/lcd/lcd_common.c | 43 +- drivers/amlogic/media/vout/lcd/lcd_common.h | 38 +- drivers/amlogic/media/vout/lcd/lcd_debug.c | 1702 +- drivers/amlogic/media/vout/lcd/lcd_debug.h | 187 + drivers/amlogic/media/vout/lcd/lcd_reg.c | 140 +- drivers/amlogic/media/vout/lcd/lcd_reg.h | 159 +- .../amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c | 10 + .../amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c | 8 +- .../media/vout/lcd/lcd_tablet/mipi_dsi_util.c | 5 +- drivers/amlogic/media/vout/lcd/lcd_tcon.c | 623 + drivers/amlogic/media/vout/lcd/lcd_tcon.h | 63 + drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h | 40993 +++++++++++++++++++ drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c | 275 + drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c | 8 +- drivers/amlogic/media/vout/lcd/lcd_unifykey.c | 72 + drivers/amlogic/media/vout/lcd/lcd_vout.c | 32 +- .../linux/amlogic/media/vout/lcd/lcd_unifykey.h | 3 + include/linux/amlogic/media/vout/lcd/lcd_vout.h | 72 +- 25 files changed, 46020 insertions(+), 2457 deletions(-) create mode 100644 arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi create mode 100644 drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h create mode 100644 drivers/amlogic/media/vout/lcd/lcd_debug.h create mode 100644 drivers/amlogic/media/vout/lcd/lcd_tcon.c create mode 100644 drivers/amlogic/media/vout/lcd/lcd_tcon.h create mode 100644 drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h diff --git a/MAINTAINERS b/MAINTAINERS index 168cddd..8235b82 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14653,3 +14653,10 @@ AMLOGIC DTS M: Luan Yuan F: arch/arm/boot/dts/amlogic/partition_mbox_p241_P.dtsi +AMLOGIC LCD DRIVERS +M: Evoke Zhang +F: arch\arm\boot\dts\amlogic\mesontl1_pxp-panel.dtsi +F: drivers\amlogic\media\vout\lcd\lcd_clk_ctrl.h +F: drivers\amlogic\media\vout\lcd\lcd_debug.h +F: drivers\amlogic\media\vout\lcd\lcd_tcon.c +F: drivers\amlogic\media\vout\lcd\lcd_tcon.h diff --git a/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi b/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi new file mode 100644 index 0000000..765211c --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi @@ -0,0 +1,92 @@ +/* + * arch/arm64/boot/dts/amlogic/mesontl1_pxp-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd { + compatible = "amlogic, lcd-tl1"; + status = "okay"; + mode = "tv"; + fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */ + key_valid = <0>; + clocks = <&clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_TCON + &clkc CLKID_FCLK_DIV5 + &clkc CLKID_TCON_PLL_COMP>; + clock-names = "encl_top_gate", + "encl_int_gate", + "tcon_gate", + "fclk_div5", + "clk_tcon"; + reg = <0xff660000 0x8100 + 0xff634400 0x100>; + interrupts = <0 3 1 + 0 78 1 + 0 88 1>; + interrupt-names = "vsync","vbyone","tcon"; + pinctrl_version = <2>; /* for uboot */ + + /* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */ + /* power index:(gpios_index, or extern_index, 0xff=invalid) */ + /* power value:(0=output low, 1=output high, 2=input) */ + /* power delay:(unit in ms) */ + + lvds_0{ + model_name = "1080p-vfreq"; + interface = "lvds"; /*lcd_interface(lvds, vbyone)*/ + basic_setting = < + 1920 1080 /*h_active, v_active*/ + 2200 1125 /*h_period, v_period*/ + 8 /*lcd_bits */ + 16 9>; /*screen_widht, screen_height*/ + range_setting = < + 2060 2650 /*h_period_min,max*/ + 1100 1480 /*v_period_min,max*/ + 120000000 160000000>; /*pclk_min,max*/ + lcd_timing = < + 44 148 0 /*hs_width, hs_bp, hs_pol*/ + 5 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = < + 2 /*fr_adj_type + *(0=clk, 1=htotal, 2=vtotal, 3=auto_range, + * 4=hdmi_mode) + */ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 0>; /*pixel_clk(unit in Hz)*/ + lvds_attr = < + 1 /*lvds_repack*/ + 1 /*dual_port*/ + 0 /*pn_swap*/ + 0 /*port_swap*/ + 0>; /*lane_reverse*/ + phy_attr=< + 3 0 /*vswing_level, preem_level*/ + 0 0>; /*clk vswing_level, preem_level*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 2 0 0 0 /*signal enable*/ + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 10 /*signal disable*/ + 0xff 0 0 0>; /*ending*/ + backlight_index = <0xff>; + }; + }; /* end of lcd */ + +}; /* end of / */ diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts index b56c2de..cd11ca0 100644 --- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts +++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts @@ -50,6 +50,12 @@ alloc-ranges = <0x05000000 0x400000>; }; }; + + vout { + compatible = "amlogic, vout"; + status = "okay"; + fr_auto_policy = <0>; + }; }; &sd_emmc_b { status = "okay"; diff --git a/drivers/amlogic/media/vout/lcd/Makefile b/drivers/amlogic/media/vout/lcd/Makefile index 8018bfd..c5dab01 100644 --- a/drivers/amlogic/media/vout/lcd/Makefile +++ b/drivers/amlogic/media/vout/lcd/Makefile @@ -1,4 +1,6 @@ -obj-$(CONFIG_AMLOGIC_LCD) += lcd_vout.o lcd_reg.o lcd_common.o lcd_notify.o lcd_debug.o lcd_clk_config.o lcd_unifykey.o +obj-$(CONFIG_AMLOGIC_LCD) += lcd_vout.o lcd_reg.o lcd_common.o lcd_notify.o \ + lcd_debug.o lcd_clk_config.o lcd_unifykey.o \ + lcd_tcon.o obj-$(CONFIG_AMLOGIC_LCD_TV) += lcd_tv/ obj-$(CONFIG_AMLOGIC_LCD_TABLET) += lcd_tablet/ obj-$(CONFIG_AMLOGIC_LCD_EXTERN) += lcd_extern/ diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c index 2eea34c..98e6933 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c @@ -24,70 +24,16 @@ #include #include #include -#include "lcd_reg.h" -#include "lcd_clk_config.h" #include #ifdef CONFIG_AMLOGIC_VPU #include #endif - +#include "lcd_reg.h" +#include "lcd_clk_config.h" +#include "lcd_clk_ctrl.h" static spinlock_t lcd_clk_lock; -static const unsigned int od_fb_table[2] = {1, 2}; - -static const unsigned int od_table[6] = { - 1, 2, 4, 8, 16, 32 -}; - -static const unsigned int div_pre_table[6] = { - 1, 2, 3, 4, 5, 6 -}; - -static char *lcd_clk_div_sel_table[] = { - "1", - "2", - "3", - "3.5", - "3.75", - "4", - "5", - "6", - "6.25", - "7", - "7.5", - "12", - "14", - "15", - "2.5", - "invalid", -}; - -static char *lcd_pll_ss_table_gxtvbb[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.5%", - "3, +/-0.9%", - "4, +/-1.2%", -}; - -static char *lcd_pll_ss_table_txl[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.4%", - "3, +/-0.9%", - "4, +/-1.2%", -}; - -static char *lcd_pll_ss_table_txlx[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.5%", - "3, +/-1.0%", - "4, +/-1.6%", - "5, +/-3.0%", -}; - static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ /* IN-OUT parameters */ .fin = FIN_FREQ, @@ -95,12 +41,13 @@ static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ /* pll parameters */ .pll_mode = 0, /* txl */ - .od_fb = 0, + .pll_od_fb = 0, .pll_m = 0, .pll_n = 0, .pll_od1_sel = 0, .pll_od2_sel = 0, .pll_od3_sel = 0, + .pll_pi_div_sel = 0, /* for tcon */ .pll_level = 0, .ss_level = 0, .div_sel = 0, @@ -108,391 +55,37 @@ static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ .pll_fout = 0, /* clk path node parameters */ - .pll_m_max = 0, - .pll_m_min = 0, - .pll_n_max = 0, - .pll_n_min = 0, - .pll_frac_range = 0, - .pll_od_sel_max = 0, - .ss_level_max = 0, .div_sel_max = 0, .xd_max = 0, - .pll_ref_fmax = 0, - .pll_ref_fmin = 0, - .pll_vco_fmax = 0, - .pll_vco_fmin = 0, - .pll_out_fmax = 0, - .pll_out_fmin = 0, - .div_in_fmax = 0, - .div_out_fmax = 0, - .xd_out_fmax = 0, -}; - -struct lcd_clk_config_s *get_lcd_clk_config(void) -{ - return &clk_conf; -} - -static void lcd_clk_config_init_print(void) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - LCDPR("lcd clk config init:\n" - "pll_m_max: %d\n" - "pll_m_min: %d\n" - "pll_n_max: %d\n" - "pll_n_min: %d\n" - "pll_frac_range: %d\n" - "pll_od_sel_max: %d\n" - "ss_level_max: %d\n" - "pll_ref_fmax: %d\n" - "pll_ref_fmin: %d\n" - "pll_vco_fmax: %d\n" - "pll_vco_fmin: %d\n" - "pll_out_fmax: %d\n" - "pll_out_fmin: %d\n" - "xd_out_fmax: %d\n\n", - clk_conf.pll_m_max, clk_conf.pll_m_min, - clk_conf.pll_n_max, clk_conf.pll_n_min, - clk_conf.pll_frac_range, - clk_conf.pll_od_sel_max, clk_conf.ss_level_max, - clk_conf.pll_ref_fmax, clk_conf.pll_ref_fmin, - clk_conf.pll_vco_fmax, clk_conf.pll_vco_fmin, - clk_conf.pll_out_fmax, clk_conf.pll_out_fmin, - clk_conf.xd_out_fmax); - break; - default: - LCDPR("lcd clk config:\n" - "pll_m_max: %d\n" - "pll_m_min: %d\n" - "pll_n_max: %d\n" - "pll_n_min: %d\n" - "pll_frac_range: %d\n" - "pll_od_sel_max: %d\n" - "ss_level_max: %d\n" - "pll_ref_fmax: %d\n" - "pll_ref_fmin: %d\n" - "pll_vco_fmax: %d\n" - "pll_vco_fmin: %d\n" - "pll_out_fmax: %d\n" - "pll_out_fmin: %d\n" - "div_in_fmax: %d\n" - "div_out_fmax: %d\n" - "xd_out_fmax: %d\n\n", - clk_conf.pll_m_max, clk_conf.pll_m_min, - clk_conf.pll_n_max, clk_conf.pll_n_min, - clk_conf.pll_frac_range, - clk_conf.pll_od_sel_max, clk_conf.ss_level_max, - clk_conf.pll_ref_fmax, clk_conf.pll_ref_fmin, - clk_conf.pll_vco_fmax, clk_conf.pll_vco_fmin, - clk_conf.pll_out_fmax, clk_conf.pll_out_fmin, - clk_conf.div_in_fmax, clk_conf.div_out_fmax, - clk_conf.xd_out_fmax); - break; - } -} - -int lcd_clk_config_print(char *buf, int offset) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int n, len = 0; - n = lcd_debug_info_len(len + offset); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - len += snprintf((buf+len), n, - "lcd clk config:\n" - "clk_path %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od: %d\n" - "pll_out: %dkHz\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - lcd_drv->lcd_clk_path, - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_fout, - clk_conf.xd, clk_conf.fout, clk_conf.ss_level); - } else { - len += snprintf((buf+len), n, - "lcd clk config:\n" - "clk_path %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od1: %d\n" - "pll_od2: %d\n" - "pll_od3: %d\n" - "pll_out: %dkHz\n" - "div_sel: %s(index %d)\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - lcd_drv->lcd_clk_path, - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, - clk_conf.pll_od3_sel, clk_conf.pll_fout, - lcd_clk_div_sel_table[clk_conf.div_sel], - clk_conf.div_sel, clk_conf.xd, - clk_conf.fout, clk_conf.ss_level); - } - break; - case LCD_CHIP_AXG: - len += snprintf((buf+len), n, - "lcd clk config:\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od: %d\n" - "pll_out: %dkHz\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_fout, - clk_conf.xd, clk_conf.fout, clk_conf.ss_level); - break; - default: - len += snprintf((buf+len), n, - "lcd clk config:\n" - "pll_mode: %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od1: %d\n" - "pll_od2: %d\n" - "pll_od3: %d\n" - "pll_out: %dkHz\n" - "div_sel: %s(index %d)\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, - clk_conf.pll_od3_sel, clk_conf.pll_fout, - lcd_clk_div_sel_table[clk_conf.div_sel], - clk_conf.div_sel, clk_conf.xd, - clk_conf.fout, clk_conf.ss_level); - break; - } + .data = NULL, +}; - return len; -} +static struct lcd_clktree_s lcd_clktree = { + .clk_gate_state = 0, -static void lcd_clk_config_chip_init(void) -{ - struct lcd_clk_config_s *cConf; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + .encl_top_gate = NULL, + .encl_int_gate = NULL, - cConf = get_lcd_clk_config(); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - cConf->od_fb = PLL_FRAC_OD_FB_GXTVBB; - cConf->ss_level_max = SS_LEVEL_MAX_GXTVBB; - cConf->pll_m_max = PLL_M_MAX_GXTVBB; - cConf->pll_m_min = PLL_M_MIN_GXTVBB; - cConf->pll_n_max = PLL_N_MAX_GXTVBB; - cConf->pll_n_min = PLL_N_MIN_GXTVBB; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXTVBB; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXTVBB; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXTVBB; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXTVBB; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXTVBB; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXTVBB; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXTVBB; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXTVBB; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXTVBB; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXTVBB; - break; - case LCD_CHIP_GXL: - cConf->od_fb = PLL_FRAC_OD_FB_GXL; - cConf->ss_level_max = SS_LEVEL_MAX_GXL; - cConf->pll_m_max = PLL_M_MAX_GXL; - cConf->pll_m_min = PLL_M_MIN_GXL; - cConf->pll_n_max = PLL_N_MAX_GXL; - cConf->pll_n_min = PLL_N_MIN_GXL; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXL; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXL; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXL; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXL; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXL; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXL; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXL; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXL; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXL; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXL; - break; - case LCD_CHIP_GXM: - cConf->od_fb = PLL_FRAC_OD_FB_GXM; - cConf->ss_level_max = SS_LEVEL_MAX_GXM; - cConf->pll_m_max = PLL_M_MAX_GXM; - cConf->pll_m_min = PLL_M_MIN_GXM; - cConf->pll_n_max = PLL_N_MAX_GXM; - cConf->pll_n_min = PLL_N_MIN_GXM; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXM; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXM; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXM; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXM; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXM; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXM; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXM; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXM; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXM; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXM; - break; - case LCD_CHIP_TXL: - cConf->od_fb = PLL_FRAC_OD_FB_TXL; - cConf->ss_level_max = SS_LEVEL_MAX_TXL; - cConf->pll_m_max = PLL_M_MAX_TXL; - cConf->pll_m_min = PLL_M_MIN_TXL; - cConf->pll_n_max = PLL_N_MAX_TXL; - cConf->pll_n_min = PLL_N_MIN_TXL; - cConf->pll_frac_range = PLL_FRAC_RANGE_TXL; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_TXL; - cConf->pll_ref_fmax = PLL_FREF_MAX_TXL; - cConf->pll_ref_fmin = PLL_FREF_MIN_TXL; - cConf->pll_vco_fmax = PLL_VCO_MAX_TXL; - cConf->pll_vco_fmin = PLL_VCO_MIN_TXL; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_TXL; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_TXL; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_TXL; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_TXL; - break; - case LCD_CHIP_TXLX: - cConf->od_fb = PLL_FRAC_OD_FB_TXLX; - cConf->ss_level_max = SS_LEVEL_MAX_TXLX; - cConf->pll_m_max = PLL_M_MAX_TXLX; - cConf->pll_m_min = PLL_M_MIN_TXLX; - cConf->pll_n_max = PLL_N_MAX_TXLX; - cConf->pll_n_min = PLL_N_MIN_TXLX; - cConf->pll_frac_range = PLL_FRAC_RANGE_TXLX; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_TXLX; - cConf->pll_ref_fmax = PLL_FREF_MAX_TXLX; - cConf->pll_ref_fmin = PLL_FREF_MIN_TXLX; - cConf->pll_vco_fmax = PLL_VCO_MAX_TXLX; - cConf->pll_vco_fmin = PLL_VCO_MIN_TXLX; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_TXLX; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_TXLX; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_TXLX; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_TXLX; - break; - case LCD_CHIP_AXG: - cConf->od_fb = PLL_FRAC_OD_FB_AXG; - cConf->ss_level_max = SS_LEVEL_MAX_AXG; - cConf->pll_m_max = PLL_M_MAX_AXG; - cConf->pll_m_min = PLL_M_MIN_AXG; - cConf->pll_n_max = PLL_N_MAX_AXG; - cConf->pll_n_min = PLL_N_MIN_AXG; - cConf->pll_frac_range = PLL_FRAC_RANGE_AXG; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_AXG; - cConf->pll_ref_fmax = PLL_FREF_MAX_AXG; - cConf->pll_ref_fmin = PLL_FREF_MIN_AXG; - cConf->pll_vco_fmax = PLL_VCO_MAX_AXG; - cConf->pll_vco_fmin = PLL_VCO_MIN_AXG; - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_AXG; - cConf->pll_out_fmin = cConf->pll_vco_fmin / - od_table[cConf->pll_od_sel_max - 1]; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_AXG; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_AXG; - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_GP0_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_GP0_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_GP0_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_GP0_G12A; - } else { - cConf->od_fb = PLL_FRAC_OD_FB_HPLL_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_HPLL_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A; - } - cConf->pll_m_max = PLL_M_MAX_G12A; - cConf->pll_m_min = PLL_M_MIN_G12A; - cConf->pll_n_max = PLL_N_MAX_G12A; - cConf->pll_n_min = PLL_N_MIN_G12A; - cConf->pll_ref_fmax = PLL_FREF_MAX_G12A; - cConf->pll_ref_fmin = PLL_FREF_MIN_G12A; - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_G12A; - break; - default: - LCDPR("%s invalid chip type\n", __func__); - break; - } - if (lcd_debug_print_flag > 0) - lcd_clk_config_init_print(); -} + .dsi_host_gate = NULL, + .dsi_phy_gate = NULL, + .dsi_meas = NULL, + .mipi_enable_gate = NULL, + .mipi_bandgap_gate = NULL, + .gp0_pll = NULL, + .tcon_gate = NULL, + .tcon_clk = NULL, +}; -int lcd_clk_path_change(int sel) +struct lcd_clk_config_s *get_lcd_clk_config(void) { - struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int ret = 0; - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (sel) { - lcd_drv->lcd_clk_path = 1; - cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_GP0_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_GP0_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_GP0_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_GP0_G12A; - } else { - lcd_drv->lcd_clk_path = 0; - cConf->od_fb = PLL_FRAC_OD_FB_HPLL_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_HPLL_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A; - } - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - break; - default: - ret = -1; - LCDPR("%s: current chip not support\n", __func__); - break; - } - if (lcd_debug_print_flag > 0) - lcd_clk_config_init_print(); - - return ret; + return &clk_conf; } -/* lcd controller operation */ +/* **************************************************** + * lcd pll & clk operation + * **************************************************** + */ static int lcd_pll_wait_lock(unsigned int reg, unsigned int lock_bit) { unsigned int pll_lock; @@ -569,182 +162,24 @@ pll_lock_end_g12a: return ret; } -static void lcd_set_pll_ss_gxtvbb(struct lcd_clk_config_s *cConf) -{ - if ((cConf->pll_fvco >= 5500000) && (cConf->pll_fvco <= 6000000)) { - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb01da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 2: /* +/- 0.5% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xa85da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 3: /* +/- 0.9% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb09da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 4: /* +/- 1.2% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb0dda72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - default: /* disable */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5081); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - break; - } - } else { - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb01da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 2: /* +/- 0.5% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xa85da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 3: /* +/- 0.9% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb09da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 4: /* +/- 1.2% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb0dda72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - default: /* disable */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - break; - } - } - LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_gxtvbb[cConf->ss_level]); -} - -static void lcd_pll_reset_gxtvbb(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_GXTVBB, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_GXTVBB, 1); -} - -static void lcd_set_pll_gxtvbb(struct lcd_clk_config_s *cConf) -{ - unsigned int pll_ctrl, pll_ctrl2; - int ret; - - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - pll_ctrl = ((1 << LCD_PLL_EN_GXTVBB) | - (1 << 27) | /* DPLL_BGP_EN */ - (cConf->pll_n << LCD_PLL_N_GXTVBB) | - (cConf->pll_m << LCD_PLL_M_GXTVBB)); - - pll_ctrl2 = ((cConf->pll_od3_sel << LCD_PLL_OD3_GXTVBB) | - (cConf->pll_od2_sel << LCD_PLL_OD2_GXTVBB) | - (cConf->pll_od1_sel << LCD_PLL_OD1_GXTVBB)); - pll_ctrl2 |= ((1 << 14) | (cConf->pll_frac << 0)); - - lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl | (1 << LCD_PLL_RST_GXTVBB)); - lcd_hiu_write(HHI_HDMI_PLL_CNTL2, pll_ctrl2); - if ((cConf->pll_fvco >= 5500000) && (cConf->pll_fvco <= 6000000)) { - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5081); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - } else { - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - } - lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl); - - ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL, LCD_PLL_LOCK_GXTVBB); - if (ret) - LCDERR("hpll lock failed\n"); - - if (cConf->ss_level > 0) - lcd_set_pll_ss_gxtvbb(cConf); -} - -static void lcd_update_pll_frac_gxtvbb(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 12); -} - -static void lcd_set_pll_ss_txl(struct lcd_clk_config_s *cConf) +static void lcd_set_pll_ss_txl(unsigned int ss_level) { unsigned int pll_ctrl3, pll_ctrl4; pll_ctrl3 = lcd_hiu_read(HHI_HDMI_PLL_CNTL3); pll_ctrl4 = lcd_hiu_read(HHI_HDMI_PLL_CNTL4); + pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); + pll_ctrl4 &= ~(0x3 << 2); + + ss_level = (ss_level >= SS_LEVEL_MAX_TXL) ? 0 : ss_level; + pll_ctrl3 |= pll_ss_reg_txl[ss_level][0]; + pll_ctrl4 |= pll_ss_reg_txl[ss_level][1]; - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - break; - case 2: /* +/- 0.4% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x8 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - break; - case 3: /* +/- 0.9% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x2 << 2); - break; - case 4: /* +/- 1.2% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - break; - default: /* disable */ - pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); - pll_ctrl4 &= ~(0x3 << 2); - break; - } lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3); lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4); LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_txl[cConf->ss_level]); -} - -static void lcd_pll_reset_txl(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_TXL, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_TXL, 1); + lcd_pll_ss_table_txl[ss_level]); } static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) @@ -759,7 +194,7 @@ static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) (cConf->pll_m << LCD_PLL_M_TXL)); pll_ctrl2 = 0x800ca000; pll_ctrl2 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl3 = 0x860330c4 | (cConf->od_fb << 30); + pll_ctrl3 = 0x860330c4 | (cConf->pll_od_fb << 30); pll_ctrl3 |= ((cConf->pll_od3_sel << LCD_PLL_OD3_TXL) | (cConf->pll_od2_sel << LCD_PLL_OD2_TXL) | (cConf->pll_od1_sel << LCD_PLL_OD1_TXL)); @@ -781,75 +216,31 @@ static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) LCDERR("hpll lock failed\n"); if (cConf->ss_level > 0) - lcd_set_pll_ss_txl(cConf); -} - -static void lcd_update_pll_frac_txl(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 12); + lcd_set_pll_ss_txl(cConf->ss_level); } -static void lcd_set_pll_ss_txlx(struct lcd_clk_config_s *cConf) +static void lcd_set_pll_ss_txlx(unsigned int ss_level) { unsigned int pll_ctrl3, pll_ctrl4, pll_ctrl5; pll_ctrl3 = lcd_hiu_read(HHI_HDMI_PLL_CNTL3); pll_ctrl4 = lcd_hiu_read(HHI_HDMI_PLL_CNTL4); pll_ctrl5 = lcd_hiu_read(HHI_HDMI_PLL_CNTL5); + pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); + pll_ctrl4 &= ~(0x3 << 2); + pll_ctrl5 &= ~(0x3 << 30); + + ss_level = (ss_level >= SS_LEVEL_MAX_TXLX) ? 0 : ss_level; + pll_ctrl3 |= pll_ss_reg_txlx[ss_level][0]; + pll_ctrl4 |= pll_ss_reg_txlx[ss_level][1]; + pll_ctrl5 |= pll_ss_reg_txlx[ss_level][2]; - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x6 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 2: /* +/- 0.5% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 3: /* +/- 1.0% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 4: /* +/- 1.6% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x8 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - pll_ctrl5 |= (0x1 << 30); - break; - case 5: /* +/- 3.0% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - pll_ctrl5 |= (0x2 << 30); - break; - default: /* disable */ - pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - } lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3); lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4); lcd_hiu_write(HHI_HDMI_PLL_CNTL5, pll_ctrl5); LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_txlx[cConf->ss_level]); + lcd_pll_ss_table_txlx[ss_level]); } static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) @@ -864,7 +255,7 @@ static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) (cConf->pll_m << LCD_PLL_M_TXL)); pll_ctrl2 = 0x800ca000; pll_ctrl2 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl3 = 0x860030c4 | (cConf->od_fb << 30); + pll_ctrl3 = 0x860030c4 | (cConf->pll_od_fb << 30); pll_ctrl3 |= ((cConf->pll_od3_sel << LCD_PLL_OD3_TXL) | (cConf->pll_od2_sel << LCD_PLL_OD2_TXL) | (cConf->pll_od1_sel << LCD_PLL_OD1_TXL)); @@ -883,14 +274,7 @@ static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) LCDERR("hpll lock failed\n"); if (cConf->ss_level > 0) - lcd_set_pll_ss_txlx(cConf); -} - -static void lcd_pll_reset_axg(void) -{ - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 1, LCD_PLL_RST_AXG, 1); - udelay(10); - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 0, LCD_PLL_RST_AXG, 1); + lcd_set_pll_ss_txlx(cConf->ss_level); } static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) @@ -907,7 +291,7 @@ static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) (cConf->pll_od1_sel << LCD_PLL_OD_AXG)); pll_ctrl1 = 0xc084a000; pll_ctrl1 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl2 = 0xb75020be | (cConf->od_fb << 19); + pll_ctrl2 = 0xb75020be | (cConf->pll_od_fb << 19); lcd_hiu_write(HHI_GP0_PLL_CNTL_AXG, pll_ctrl); lcd_hiu_write(HHI_GP0_PLL_CNTL1_AXG, pll_ctrl1); @@ -924,22 +308,6 @@ static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL_AXG, LCD_PLL_LOCK_AXG); if (ret) LCDERR("gp0_pll lock failed\n"); - -} - -static void lcd_update_pll_frac_axg(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_GP0_PLL_CNTL1_AXG, cConf->pll_frac, 0, 12); -} - -static void lcd_gp0_pll_reset_g12a(void) -{ - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 1, LCD_PLL_RST_GP0_G12A, 1); - udelay(10); - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 0, LCD_PLL_RST_GP0_G12A, 1); } static void lcd_set_gp0_pll_g12a(struct lcd_clk_config_s *cConf) @@ -980,22 +348,6 @@ static void lcd_set_gp0_pll_g12a(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock_g12a(1); if (ret) LCDERR("gp0_pll lock failed\n"); - -} - -static void lcd_update_gp0_pll_frac_g12a(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_GP0_PLL_CNTL1_G12A, cConf->pll_frac, 0, 19); -} - -static void lcd_hpll_reset_g12a(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_HPLL_G12A, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_HPLL_G12A, 1); } static void lcd_set_hpll_g12a(struct lcd_clk_config_s *cConf) @@ -1039,15 +391,6 @@ static void lcd_set_hpll_g12a(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock_g12a(0); if (ret) LCDERR("hpll lock failed\n"); - -} - -static void lcd_update_hpll_frac_g12a(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 19); } static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf) @@ -1088,7 +431,6 @@ static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_LOCK_GP0_G12A); if (ret) LCDERR("gp0_pll lock failed\n"); - } static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf) @@ -1132,33 +474,54 @@ static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL, LCD_PLL_LOCK_HPLL_G12A); if (ret) LCDERR("hpll lock failed\n"); - } -static unsigned int lcd_clk_div_g9_gxtvbb[][3] = { - /* divider, shift_val, shift_sel */ - {CLK_DIV_SEL_1, 0xffff, 0,}, - {CLK_DIV_SEL_2, 0x0aaa, 0,}, - {CLK_DIV_SEL_3, 0x0db6, 0,}, - {CLK_DIV_SEL_3p5, 0x36cc, 1,}, - {CLK_DIV_SEL_3p75, 0x6666, 2,}, - {CLK_DIV_SEL_4, 0x0ccc, 0,}, - {CLK_DIV_SEL_5, 0x739c, 2,}, - {CLK_DIV_SEL_6, 0x0e38, 0,}, - {CLK_DIV_SEL_6p25, 0x0000, 3,}, - {CLK_DIV_SEL_7, 0x3c78, 1,}, - {CLK_DIV_SEL_7p5, 0x78f0, 2,}, - {CLK_DIV_SEL_12, 0x0fc0, 0,}, - {CLK_DIV_SEL_14, 0x3f80, 1,}, - {CLK_DIV_SEL_15, 0x7f80, 2,}, - {CLK_DIV_SEL_2p5, 0x5294, 2,}, - {CLK_DIV_SEL_MAX, 0xffff, 0,}, -}; - -static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) +static void lcd_set_pll_ss_tl1(unsigned int ss_level) { - unsigned int shift_val, shift_sel; - int i; + LCDPR("%s: todo\n", __func__); +} + +static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) +{ + unsigned int pll_ctrl, pll_ctrl1; + int ret; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + pll_ctrl = ((0x3 << 17) | /* gate ctrl */ + (1 << LCD_PLL_RST_TL1) | + (cConf->pll_n << LCD_PLL_N_TL1) | + (cConf->pll_m << LCD_PLL_M_TL1) | + (cConf->pll_od3_sel << LCD_PLL_OD3_TL1) | + (cConf->pll_od2_sel << LCD_PLL_OD2_TL1) | + (cConf->pll_od1_sel << LCD_PLL_OD1_TL1)); + pll_ctrl1 = (1 << 28) | (1 << 23) | + ((1 << 20) | (cConf->pll_frac << 0)); + + lcd_hiu_write(HHI_TCON_PLL_CNTL0, pll_ctrl); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_EN_TL1, 1); + lcd_hiu_write(HHI_TCON_PLL_CNTL1, pll_ctrl1); + lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108); + lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 1, 26, 1); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1); + lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x0b8300c0); + + ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1); + if (ret) + LCDERR("hpll lock failed\n"); + + if (cConf->ss_level > 0) + lcd_set_pll_ss_tl1(cConf->ss_level); +} + +static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) +{ + unsigned int shift_val, shift_sel; + int i; if (lcd_debug_print_flag == 2) LCDPR("%s\n", __func__); @@ -1171,15 +534,15 @@ static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1); i = 0; - while (lcd_clk_div_g9_gxtvbb[i][0] != CLK_DIV_SEL_MAX) { - if (cConf->div_sel == lcd_clk_div_g9_gxtvbb[i][0]) + while (lcd_clk_div_table[i][0] != CLK_DIV_SEL_MAX) { + if (cConf->div_sel == lcd_clk_div_table[i][0]) break; i++; } - if (lcd_clk_div_g9_gxtvbb[i][0] == CLK_DIV_SEL_MAX) + if (lcd_clk_div_table[i][0] == CLK_DIV_SEL_MAX) LCDERR("invalid clk divider\n"); - shift_val = lcd_clk_div_g9_gxtvbb[i][1]; - shift_sel = lcd_clk_div_g9_gxtvbb[i][2]; + shift_val = lcd_clk_div_table[i][1]; + shift_sel = lcd_clk_div_table[i][2]; if (shift_val == 0xffff) { /* if divide by 1 */ lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 18, 1); @@ -1200,7 +563,6 @@ static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag == 2) LCDPR("%s\n", __func__); @@ -1209,18 +571,8 @@ static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf) udelay(5); /* select vid_pll_clk */ - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_CLK_IN_SEL, 3); - else - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3); - break; - default: - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3); - break; - } + lcd_hiu_setb(HHI_VIID_CLK_CNTL, cConf->data->vclk_sel, + VCLK2_CLK_IN_SEL, 3); lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1); udelay(2); @@ -1250,6 +602,58 @@ static void lcd_set_dsi_phy_clk(int sel) lcd_hiu_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 0, 0, 7); } +static void lcd_set_tcon_clk(struct lcd_config_s *pconf) +{ +#if 0 + unsigned int val; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + + switch (pconf->lcd_basic.lcd_type) { + case LCD_LVDS: + lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x0); + lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x80000000); + lcd_hiu_write(HHI_DIF_TCON_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0); + break; + case LCD_MLVDS: + val = pconf->lcd_control.mlvds_config->pi_clk_sel; + /*val = (~val) & 0x3ff;*/ + lcd_hiu_write(HHI_DIF_TCON_CNTL0, (val << 12)); + lcd_hiu_write(HHI_DIF_TCON_CNTL0, ((1 << 31) | (val << 12))); + + val = pconf->lcd_control.mlvds_config->clk_phase & 0xfff; + lcd_hiu_write(HHI_DIF_TCON_CNTL1, val); + lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0); + + /* tcon_clk 50M */ + /*lcd_hiu_write(HHI_TCON_CLK_CNTL, + * (1 << 7) | (1 << 6) | (7 << 0)); + */ + if (!IS_ERR(lcd_clktree.tcon_clk)) { + clk_set_rate(lcd_clktree.tcon_clk, 50000000); + clk_prepare_enable(lcd_clktree.tcon_clk); + } + break; + default: + break; + } +#endif +} + +/* **************************************************** + * lcd clk parameters calculate + * **************************************************** + */ +static int error_abs(int a, int b) +{ + if (a >= b) + return (a - b); + else + return (b - a); +} + static unsigned int clk_vid_pll_div_calc(unsigned int clk, unsigned int div_sel, int dir) { @@ -1377,9 +781,11 @@ static unsigned int clk_vid_pll_div_get(unsigned int clk_div) return div_sel; } -static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, +static int check_pll_txl(struct lcd_clk_config_s *cConf, unsigned int pll_fout) { + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_clk_data_s *data = cConf->data; unsigned int m, n; unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; @@ -1387,11 +793,11 @@ static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, int done; done = 0; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { return done; } - for (od3_sel = cConf->pll_od_sel_max; od3_sel > 0; od3_sel--) { + for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) { od3 = od_table[od3_sel - 1]; pll_fod3_in = pll_fout * od3; for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { @@ -1400,8 +806,8 @@ static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { od1 = od_table[od1_sel - 1]; pll_fvco = pll_fod2_in * od1; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { continue; } cConf->pll_od1_sel = od1_sel - 1; @@ -1416,11 +822,19 @@ static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, } cConf->pll_fvco = pll_fvco; n = 1; - od_fb = cConf->od_fb; /* pll default */ - pll_fvco = pll_fvco / od_fb_table[od_fb + 1]; + if (lcd_drv->data->chip_type == LCD_CHIP_TXL) { + if (pll_fvco < 3700000) + od_fb = 0; + else + od_fb = 1; + cConf->pll_od_fb = od_fb; + } else { + od_fb = cConf->pll_od_fb; + } + pll_fvco = pll_fvco / od_fb_table[od_fb]; m = pll_fvco / cConf->fin; pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; + data->pll_frac_range / cConf->fin; cConf->pll_m = m; cConf->pll_n = n; cConf->pll_frac = pll_frac; @@ -1436,32 +850,118 @@ static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, return done; } -static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) +static int check_pll_tl1_mlvds(struct lcd_clk_config_s *cConf, + unsigned int pll_fvco) { - unsigned int pll_fout; + struct lcd_clk_data_s *data = cConf->data; + unsigned int m, n; + unsigned int od_fb = 0, pll_frac; + int done = 0; + + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { + if (lcd_debug_print_flag == 2) + LCDPR("pll_fvco %d is out of range\n", pll_fvco); + return done; + } + + cConf->pll_fvco = pll_fvco; + n = 1; + od_fb = cConf->pll_od_fb; + pll_fvco = pll_fvco / od_fb_table[od_fb]; + m = pll_fvco / cConf->fin; + pll_frac = (pll_fvco % cConf->fin) * data->pll_frac_range / cConf->fin; + cConf->pll_m = m; + cConf->pll_n = n; + cConf->pll_frac = pll_frac; + if (lcd_debug_print_flag == 2) { + LCDPR("m=%d, n=%d, frac=0x%x, pll_fvco=%d\n", + m, n, pll_frac, pll_fvco); + } + done = 1; + + return done; +} + +#define PLL_FVCO_ERR_MAX 2 /* kHz */ +static int check_pll_od_tl1_mlvds(struct lcd_clk_config_s *cConf, + unsigned int pll_fout) +{ + struct lcd_clk_data_s *data = cConf->data; + unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; + unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; + int done = 0; + + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { + return done; + } + for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) { + od3 = od_table[od3_sel - 1]; + pll_fod3_in = pll_fout * od3; + for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { + od2 = od_table[od2_sel - 1]; + pll_fod2_in = pll_fod3_in * od2; + for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { + od1 = od_table[od1_sel - 1]; + pll_fvco = pll_fod2_in * od1; + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { + continue; + } + if (error_abs(pll_fvco, cConf->pll_fvco) < + PLL_FVCO_ERR_MAX) { + cConf->pll_od1_sel = od1_sel - 1; + cConf->pll_od2_sel = od2_sel - 1; + cConf->pll_od3_sel = od3_sel - 1; + cConf->pll_fout = pll_fout; + + if (lcd_debug_print_flag == 2) { + LCDPR( + "od1=%d, od2=%d, od3=%d\n", + (od1_sel - 1), + (od2_sel - 1), + (od3_sel - 1)); + } + done = 1; + break; + } + } + } + } + return done; +} + +static void lcd_clk_generate_txl(struct lcd_config_s *pconf) +{ + unsigned int pll_fout, pll_fvco, bit_rate; unsigned int clk_div_in, clk_div_out; - unsigned int clk_div_sel, xd; - struct lcd_clk_config_s *cConf; + unsigned int clk_div_sel, xd, pi_div_sel; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int done; done = 0; - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); - goto generate_clk_done_gxtvbb; + goto generate_clk_done_txl; } + if (pconf->lcd_timing.clk_auto == 2) + cConf->pll_mode = 1; + else + cConf->pll_mode = 0; + switch (pconf->lcd_basic.lcd_type) { case LCD_TTL: clk_div_sel = CLK_DIV_SEL_1; cConf->xd_max = CRT_VID_DIV_MAX; for (xd = 1; xd <= cConf->xd_max; xd++) { clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) + if (clk_div_out > cConf->data->div_out_fmax) continue; if (lcd_debug_print_flag == 2) { LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", @@ -1469,7 +969,7 @@ static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) } clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) + if (clk_div_in > cConf->data->div_in_fmax) continue; cConf->xd = xd; cConf->div_sel = clk_div_sel; @@ -1479,25 +979,25 @@ static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) lcd_clk_div_sel_table[clk_div_sel], clk_div_sel, pll_fout); } - done = check_pll_gxtvbb(cConf, pll_fout); + done = check_pll_txl(cConf, pll_fout); if (done) - goto generate_clk_done_gxtvbb; + goto generate_clk_done_txl; } break; case LCD_LVDS: clk_div_sel = CLK_DIV_SEL_7; xd = 1; clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_gxtvbb; + if (clk_div_out > cConf->data->div_out_fmax) + goto generate_clk_done_txl; if (lcd_debug_print_flag == 2) { LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", cConf->fout, xd, clk_div_out); } clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_gxtvbb; + if (clk_div_in > cConf->data->div_in_fmax) + goto generate_clk_done_txl; cConf->xd = xd; cConf->div_sel = clk_div_sel; pll_fout = clk_div_in; @@ -1506,17 +1006,17 @@ static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) lcd_clk_div_sel_table[clk_div_sel], clk_div_sel, pll_fout); } - done = check_pll_gxtvbb(cConf, pll_fout); + done = check_pll_txl(cConf, pll_fout); if (done) - goto generate_clk_done_gxtvbb; + goto generate_clk_done_txl; break; case LCD_VBYONE: cConf->div_sel_max = CLK_DIV_SEL_MAX; cConf->xd_max = CRT_VID_DIV_MAX; pll_fout = pconf->lcd_control.vbyone_config->bit_rate / 1000; clk_div_in = pll_fout; - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_gxtvbb; + if (clk_div_in > cConf->data->div_in_fmax) + goto generate_clk_done_txl; if (lcd_debug_print_flag == 2) LCDPR("pll_fout=%d\n", pll_fout); if ((clk_div_in / cConf->fout) > 15) @@ -1529,8 +1029,8 @@ static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) clk_div_in, cConf->fout, clk_div_out, cConf->xd); } - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_gxtvbb; + if (clk_div_out > cConf->data->div_out_fmax) + goto generate_clk_done_txl; clk_div_sel = clk_vid_pll_div_get( clk_div_in * 100 / clk_div_out); cConf->div_sel = clk_div_sel; @@ -1539,13 +1039,60 @@ static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) lcd_clk_div_sel_table[clk_div_sel], cConf->div_sel); } - done = check_pll_gxtvbb(cConf, pll_fout); + done = check_pll_txl(cConf, pll_fout); + break; + case LCD_MLVDS: + bit_rate = pconf->lcd_control.mlvds_config->bit_rate / 1000; + for (pi_div_sel = 0; pi_div_sel < 2; pi_div_sel++) { + pll_fvco = bit_rate * pi_div_table[pi_div_sel] * 4; + done = check_pll_tl1_mlvds(cConf, pll_fvco); + if (done) { + clk_div_sel = CLK_DIV_SEL_1; + cConf->xd_max = CRT_VID_DIV_MAX; + for (xd = 1; xd <= cConf->xd_max; xd++) { + clk_div_out = cConf->fout * xd; + if (clk_div_out > + cConf->data->div_out_fmax) + continue; + if (lcd_debug_print_flag == 2) { + LCDPR("fout=%d, xd=%d\n", + cConf->fout, xd); + LCDPR("clk_div_out=%d\n", + clk_div_out); + } + clk_div_in = clk_vid_pll_div_calc( + clk_div_out, + clk_div_sel, CLK_DIV_O2I); + if (clk_div_in > + cConf->data->div_in_fmax) + continue; + cConf->xd = xd; + cConf->div_sel = clk_div_sel; + cConf->pll_pi_div_sel = pi_div_sel; + pll_fout = clk_div_in; + if (lcd_debug_print_flag == 2) { + LCDPR("clk_div_sel=%s(%d)\n", + lcd_clk_div_sel_table[ + clk_div_sel], + clk_div_sel); + LCDPR("pll_fout=%d\n", + pll_fout); + LCDPR("pi_clk_sel=%d\n", + pi_div_sel); + } + done = check_pll_od_tl1_mlvds( + cConf, pll_fout); + if (done) + goto generate_clk_done_txl; + } + } + } break; default: break; } -generate_clk_done_gxtvbb: +generate_clk_done_txl: if (done) { pconf->lcd_timing.pll_ctrl = (cConf->pll_od1_sel << PLL_CTRL_OD1) | @@ -1556,8 +1103,7 @@ generate_clk_done_gxtvbb: pconf->lcd_timing.div_ctrl = (cConf->div_sel << DIV_CTRL_DIV_SEL) | (cConf->xd << DIV_CTRL_XD); - pconf->lcd_timing.clk_ctrl = - (cConf->pll_frac << CLK_CTRL_FRAC); + pconf->lcd_timing.clk_ctrl = (cConf->pll_frac << CLK_CTRL_FRAC); } else { pconf->lcd_timing.pll_ctrl = (1 << PLL_CTRL_OD1) | @@ -1573,15 +1119,14 @@ generate_clk_done_gxtvbb: } } -static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) +static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) { unsigned int pll_fout; unsigned int clk_div_in, clk_div_out, clk_div_sel; unsigned int od1, od2, od3, pll_fvco; unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ clk_div_sel = cConf->div_sel; od1 = od_table[cConf->pll_od1_sel]; @@ -1589,6 +1134,7 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) od3 = od_table[cConf->pll_od3_sel]; m = cConf->pll_m; n = cConf->pll_n; + od_fb = cConf->pll_od_fb; if (lcd_debug_print_flag == 2) { LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n", @@ -1598,7 +1144,7 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) lcd_clk_div_sel_table[clk_div_sel], clk_div_sel, cConf->xd); } - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); return; @@ -1607,7 +1153,7 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) LCDPR("%s pclk=%d\n", __func__, cConf->fout); clk_div_out = cConf->fout * cConf->xd; - if (clk_div_out > cConf->div_out_fmax) { + if (clk_div_out > cConf->data->div_out_fmax) { LCDERR("%s: wrong clk_div_out value %dkHz\n", __func__, clk_div_out); return; @@ -1615,15 +1161,15 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) { + if (clk_div_in > cConf->data->div_in_fmax) { LCDERR("%s: wrong clk_div_in value %dkHz\n", __func__, clk_div_in); return; } pll_fout = clk_div_in; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > cConf->data->pll_out_fmax) || + (pll_fout < cConf->data->pll_out_fmin)) { LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); return; } @@ -1631,8 +1177,8 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) LCDPR("%s pll_fout=%d\n", __func__, pll_fout); pll_fvco = pll_fout * od1 * od2 * od3; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < cConf->data->pll_vco_fmin) || + (pll_fvco > cConf->data->pll_vco_fmax)) { LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); return; } @@ -1640,8 +1186,7 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco); cConf->pll_fvco = pll_fvco; - od_fb = cConf->od_fb; /* pll default */ - pll_fvco = pll_fvco / od_fb_table[od_fb + 1]; + pll_fvco = pll_fvco / od_fb_table[od_fb]; temp = cConf->fin * m / n; if (pll_fvco >= temp) { temp = pll_fvco - temp; @@ -1655,397 +1200,101 @@ static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) __func__, temp); return; } - frac = temp * cConf->pll_frac_range * n / cConf->fin; + frac = temp * cConf->data->pll_frac_range * n / cConf->fin; cConf->pll_frac = frac | (offset << 11); if (lcd_debug_print_flag) - LCDPR("lcd_pll_frac_generate frac=%d\n", frac); + LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac); } -static int check_pll_txl(struct lcd_clk_config_s *cConf, +static int check_pll_axg(struct lcd_clk_config_s *cConf, unsigned int pll_fout) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - unsigned int m, n; - unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; - unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; + struct lcd_clk_data_s *data = cConf->data; + unsigned int m, n, od_sel, od; + unsigned int pll_fvco; unsigned int od_fb = 0, pll_frac; - int done; + int done = 0; - done = 0; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { return done; } - for (od3_sel = cConf->pll_od_sel_max; od3_sel > 0; od3_sel--) { - od3 = od_table[od3_sel - 1]; - pll_fod3_in = pll_fout * od3; - for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { - od2 = od_table[od2_sel - 1]; - pll_fod2_in = pll_fod3_in * od2; - for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { - od1 = od_table[od1_sel - 1]; - pll_fvco = pll_fod2_in * od1; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { - continue; - } - cConf->pll_od1_sel = od1_sel - 1; - cConf->pll_od2_sel = od2_sel - 1; - cConf->pll_od3_sel = od3_sel - 1; - cConf->pll_fout = pll_fout; - if (lcd_debug_print_flag == 2) { - LCDPR("od1=%d, od2=%d, od3=%d\n", - (od1_sel - 1), (od2_sel - 1), - (od3_sel - 1)); - LCDPR("pll_fvco=%d\n", pll_fvco); - } - cConf->pll_fvco = pll_fvco; - n = 1; - if (lcd_drv->data->chip_type == LCD_CHIP_TXL) { - if (pll_fvco < 3700000) - od_fb = 0; - else - od_fb = 1; - cConf->od_fb = od_fb; - } else { - od_fb = cConf->od_fb; - } - pll_fvco = pll_fvco / od_fb_table[od_fb]; - m = pll_fvco / cConf->fin; - pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; - cConf->pll_m = m; - cConf->pll_n = n; - cConf->pll_frac = pll_frac; - if (lcd_debug_print_flag == 2) { - LCDPR("m=%d, n=%d, frac=0x%x\n", - m, n, pll_frac); - } - done = 1; - break; - } + for (od_sel = data->pll_od_sel_max; od_sel > 0; od_sel--) { + od = od_table[od_sel - 1]; + pll_fvco = pll_fout * od; + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { + continue; + } + cConf->pll_od1_sel = od_sel - 1; + cConf->pll_fout = pll_fout; + if (lcd_debug_print_flag == 2) { + LCDPR("od_sel=%d, pll_fvco=%d\n", + (od_sel - 1), pll_fvco); + } + + cConf->pll_fvco = pll_fvco; + n = 1; + od_fb = cConf->pll_od_fb; + pll_fvco = pll_fvco / od_fb_table[od_fb]; + m = pll_fvco / cConf->fin; + pll_frac = (pll_fvco % cConf->fin) * + data->pll_frac_range / cConf->fin; + cConf->pll_m = m; + cConf->pll_n = n; + cConf->pll_frac = pll_frac; + if (lcd_debug_print_flag == 2) { + LCDPR("pll_m=%d, pll_n=%d, pll_frac=0x%x\n", + m, n, pll_frac); } + done = 1; + break; } return done; } -static void lcd_clk_generate_txl(struct lcd_config_s *pconf) +static void lcd_clk_generate_axg(struct lcd_config_s *pconf) { unsigned int pll_fout; - unsigned int clk_div_in, clk_div_out; - unsigned int clk_div_sel, xd; - struct lcd_clk_config_s *cConf; + unsigned int xd; + unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0; + unsigned int tmp; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int done; done = 0; - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); - goto generate_clk_done_txl; + goto generate_clk_done_axg; } - if (pconf->lcd_timing.clk_auto == 2) - cConf->pll_mode = 1; - else - cConf->pll_mode = 0; - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - clk_div_sel = CLK_DIV_SEL_1; + case LCD_MIPI: cConf->xd_max = CRT_VID_DIV_MAX; + tmp = pconf->lcd_control.mipi_config->bit_rate_max; + dsi_bit_rate_max = tmp * 1000; /* change to kHz */ + dsi_bit_rate_min = dsi_bit_rate_max - cConf->fout; + for (xd = 1; xd <= cConf->xd_max; xd++) { - clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) + pll_fout = cConf->fout * xd; + if ((pll_fout > dsi_bit_rate_max) || + (pll_fout < dsi_bit_rate_min)) { continue; - if (lcd_debug_print_flag == 2) { - LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", - cConf->fout, xd, clk_div_out); } - clk_div_in = clk_vid_pll_div_calc(clk_div_out, - clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) - continue; + if (lcd_debug_print_flag == 2) + LCDPR("fout=%d, xd=%d\n", cConf->fout, xd); + + pconf->lcd_control.mipi_config->bit_rate = + pll_fout * 1000; + pconf->lcd_control.mipi_config->clk_factor = xd; cConf->xd = xd; - cConf->div_sel = clk_div_sel; - pll_fout = clk_div_in; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, pll_fout); - } - done = check_pll_txl(cConf, pll_fout); + done = check_pll_axg(cConf, pll_fout); if (done) - goto generate_clk_done_txl; - } - break; - case LCD_LVDS: - clk_div_sel = CLK_DIV_SEL_7; - xd = 1; - clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_txl; - if (lcd_debug_print_flag == 2) { - LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", - cConf->fout, xd, clk_div_out); - } - clk_div_in = clk_vid_pll_div_calc(clk_div_out, - clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_txl; - cConf->xd = xd; - cConf->div_sel = clk_div_sel; - pll_fout = clk_div_in; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, pll_fout); - } - done = check_pll_txl(cConf, pll_fout); - if (done) - goto generate_clk_done_txl; - break; - case LCD_VBYONE: - cConf->div_sel_max = CLK_DIV_SEL_MAX; - cConf->xd_max = CRT_VID_DIV_MAX; - pll_fout = pconf->lcd_control.vbyone_config->bit_rate / 1000; - clk_div_in = pll_fout; - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_txl; - if (lcd_debug_print_flag == 2) - LCDPR("pll_fout=%d\n", pll_fout); - if ((clk_div_in / cConf->fout) > 15) - cConf->xd = 4; - else - cConf->xd = 1; - clk_div_out = cConf->fout * cConf->xd; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_in=%d, fout=%d, xd=%d, clk_div_out=%d\n", - clk_div_in, cConf->fout, - clk_div_out, cConf->xd); - } - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_txl; - clk_div_sel = clk_vid_pll_div_get( - clk_div_in * 100 / clk_div_out); - cConf->div_sel = clk_div_sel; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d)\n", - lcd_clk_div_sel_table[clk_div_sel], - cConf->div_sel); - } - done = check_pll_txl(cConf, pll_fout); - break; - default: - break; - } - -generate_clk_done_txl: - if (done) { - pconf->lcd_timing.pll_ctrl = - (cConf->pll_od1_sel << PLL_CTRL_OD1) | - (cConf->pll_od2_sel << PLL_CTRL_OD2) | - (cConf->pll_od3_sel << PLL_CTRL_OD3) | - (cConf->pll_n << PLL_CTRL_N) | - (cConf->pll_m << PLL_CTRL_M); - pconf->lcd_timing.div_ctrl = - (cConf->div_sel << DIV_CTRL_DIV_SEL) | - (cConf->xd << DIV_CTRL_XD); - pconf->lcd_timing.clk_ctrl = (cConf->pll_frac << CLK_CTRL_FRAC); - } else { - pconf->lcd_timing.pll_ctrl = - (1 << PLL_CTRL_OD1) | - (1 << PLL_CTRL_OD2) | - (1 << PLL_CTRL_OD3) | - (1 << PLL_CTRL_N) | - (50 << PLL_CTRL_M); - pconf->lcd_timing.div_ctrl = - (CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) | - (7 << DIV_CTRL_XD); - pconf->lcd_timing.clk_ctrl = (0 << CLK_CTRL_FRAC); - LCDERR("Out of clock range, reset to default setting\n"); - } -} - -static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) -{ - unsigned int pll_fout; - unsigned int clk_div_in, clk_div_out, clk_div_sel; - unsigned int od1, od2, od3, pll_fvco; - unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; - - cConf = get_lcd_clk_config(); - cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ - clk_div_sel = cConf->div_sel; - od1 = od_table[cConf->pll_od1_sel]; - od2 = od_table[cConf->pll_od2_sel]; - od3 = od_table[cConf->pll_od3_sel]; - m = cConf->pll_m; - n = cConf->pll_n; - od_fb = cConf->od_fb; - - if (lcd_debug_print_flag == 2) { - LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n", - m, n, cConf->pll_od1_sel, cConf->pll_od2_sel, - cConf->pll_od3_sel); - LCDPR("clk_div_sel=%s(index %d), xd=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, cConf->xd); - } - if (cConf->fout > cConf->xd_out_fmax) { - LCDERR("%s: wrong lcd_clk value %dkHz\n", - __func__, cConf->fout); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pclk=%d\n", __func__, cConf->fout); - - clk_div_out = cConf->fout * cConf->xd; - if (clk_div_out > cConf->div_out_fmax) { - LCDERR("%s: wrong clk_div_out value %dkHz\n", - __func__, clk_div_out); - return; - } - - clk_div_in = - clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) { - LCDERR("%s: wrong clk_div_in value %dkHz\n", - __func__, clk_div_in); - return; - } - - pll_fout = clk_div_in; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { - LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pll_fout=%d\n", __func__, pll_fout); - - pll_fvco = pll_fout * od1 * od2 * od3; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { - LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco); - - cConf->pll_fvco = pll_fvco; - pll_fvco = pll_fvco / od_fb_table[od_fb]; - temp = cConf->fin * m / n; - if (pll_fvco >= temp) { - temp = pll_fvco - temp; - offset = 0; - } else { - temp = temp - pll_fvco; - offset = 1; - } - if (temp >= (2 * cConf->fin)) { - LCDERR("%s: pll changing %dkHz is too much\n", - __func__, temp); - return; - } - frac = temp * cConf->pll_frac_range * n / cConf->fin; - cConf->pll_frac = frac | (offset << 11); - if (lcd_debug_print_flag) - LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac); -} - -static int check_pll_axg(struct lcd_clk_config_s *cConf, - unsigned int pll_fout) -{ - unsigned int m, n, od_sel, od; - unsigned int pll_fvco; - unsigned int od_fb = 0, pll_frac; - int done = 0; - - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { - return done; - } - for (od_sel = cConf->pll_od_sel_max; od_sel > 0; od_sel--) { - od = od_table[od_sel - 1]; - pll_fvco = pll_fout * od; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { - continue; - } - cConf->pll_od1_sel = od_sel - 1; - cConf->pll_fout = pll_fout; - if (lcd_debug_print_flag == 2) { - LCDPR("od_sel=%d, pll_fvco=%d\n", - (od_sel - 1), pll_fvco); - } - - cConf->pll_fvco = pll_fvco; - n = 1; - od_fb = cConf->od_fb; - pll_fvco = pll_fvco / od_fb_table[od_fb]; - m = pll_fvco / cConf->fin; - pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; - cConf->pll_m = m; - cConf->pll_n = n; - cConf->pll_frac = pll_frac; - if (lcd_debug_print_flag == 2) { - LCDPR("pll_m=%d, pll_n=%d, pll_frac=0x%x\n", - m, n, pll_frac); - } - done = 1; - break; - } - return done; -} - -static void lcd_clk_generate_axg(struct lcd_config_s *pconf) -{ - unsigned int pll_fout; - unsigned int xd; - unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0; - unsigned int tmp; - struct lcd_clk_config_s *cConf; - int done; - - done = 0; - cConf = get_lcd_clk_config(); - cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ - cConf->err_fmin = MAX_ERROR; - - if (cConf->fout > cConf->xd_out_fmax) { - LCDERR("%s: wrong lcd_clk value %dkHz\n", - __func__, cConf->fout); - goto generate_clk_done_axg; - } - - switch (pconf->lcd_basic.lcd_type) { - case LCD_MIPI: - cConf->xd_max = CRT_VID_DIV_MAX; - tmp = pconf->lcd_control.mipi_config->bit_rate_max; - dsi_bit_rate_max = tmp * 1000; /* change to kHz */ - dsi_bit_rate_min = dsi_bit_rate_max - cConf->fout; - - for (xd = 1; xd <= cConf->xd_max; xd++) { - pll_fout = cConf->fout * xd; - if ((pll_fout > dsi_bit_rate_max) || - (pll_fout < dsi_bit_rate_min)) { - continue; - } - if (lcd_debug_print_flag == 2) - LCDPR("fout=%d, xd=%d\n", cConf->fout, xd); - - pconf->lcd_control.mipi_config->bit_rate = pll_fout * 1000; - pconf->lcd_control.mipi_config->clk_factor = xd; - cConf->xd = xd; - done = check_pll_axg(cConf, pll_fout); - if (done) - goto generate_clk_done_axg; + goto generate_clk_done_axg; } break; default: @@ -2080,19 +1329,19 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) unsigned int pll_fout; unsigned int od, pll_fvco; unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ od = od_table[cConf->pll_od1_sel]; m = cConf->pll_m; n = cConf->pll_n; + od_fb = cConf->pll_od_fb; if (lcd_debug_print_flag == 2) { LCDPR("m=%d, n=%d, od=%d, xd=%d\n", m, n, cConf->pll_od1_sel, cConf->xd); } - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); return; @@ -2101,8 +1350,8 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pclk=%d\n", __func__, cConf->fout); pll_fout = cConf->fout * cConf->xd; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > cConf->data->pll_out_fmax) || + (pll_fout < cConf->data->pll_out_fmin)) { LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); return; } @@ -2110,8 +1359,8 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pll_fout=%d\n", __func__, pll_fout); pll_fvco = pll_fout * od; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < cConf->data->pll_vco_fmin) || + (pll_fvco > cConf->data->pll_vco_fmax)) { LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); return; } @@ -2119,7 +1368,6 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco); cConf->pll_fvco = pll_fvco; - od_fb = cConf->od_fb; /* pll default */ pll_fvco = pll_fvco / od_fb_table[od_fb]; temp = cConf->fin * m / n; if (pll_fvco >= temp) { @@ -2134,7 +1382,7 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) __func__, temp); return; } - frac = temp * cConf->pll_frac_range * n / cConf->fin; + frac = temp * cConf->data->pll_frac_range * n / cConf->fin; cConf->pll_frac = frac | (offset << 11); if (lcd_debug_print_flag) LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac); @@ -2153,7 +1401,7 @@ static void lcd_clk_generate_hpll_g12a(struct lcd_config_s *pconf) cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); } @@ -2216,91 +1464,673 @@ generate_clk_done_g12a: } } -void lcd_clk_generate_parameter(struct lcd_config_s *pconf) +/* **************************************************** + * lcd clk match function + * **************************************************** + */ +void lcd_clk_set_txl(struct lcd_config_s *pconf) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + lcd_set_pll_txl(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_clk_generate_gxtvbb(pconf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_clk_generate_txl(pconf); - break; - case LCD_CHIP_AXG: - lcd_clk_generate_axg(pconf); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_clk_generate_axg(pconf); - else - lcd_clk_generate_hpll_g12a(pconf); - break; - default: - break; +static void lcd_clk_set_txlx(struct lcd_config_s *pconf) +{ + lcd_set_pll_txlx(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} + +static void lcd_clk_set_axg(struct lcd_config_s *pconf) +{ + lcd_set_pll_axg(&clk_conf); +} + +static void lcd_clk_set_g12a_path0(struct lcd_config_s *pconf) +{ + /* hpll */ + lcd_set_hpll_g12a(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); + lcd_set_dsi_phy_clk(0); +} + +static void lcd_clk_set_g12a_path1(struct lcd_config_s *pconf) +{ + /* gp0_pll */ + lcd_set_gp0_pll_g12a(&clk_conf); + lcd_set_dsi_phy_clk(1); +} + +static void lcd_clk_set_g12b_path0(struct lcd_config_s *pconf) +{ + /* hpll */ + lcd_set_hpll_g12b(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); + lcd_set_dsi_phy_clk(0); +} + +static void lcd_clk_set_g12b_path1(struct lcd_config_s *pconf) +{ + /* gp0_pll */ + lcd_set_gp0_pll_g12b(&clk_conf); + lcd_set_dsi_phy_clk(1); +} + +static void lcd_clk_set_tl1(struct lcd_config_s *pconf) +{ + lcd_set_tcon_clk(pconf); + lcd_set_pll_tl1(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} + +static void lcd_clk_gate_switch_dft(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + } else { + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gata\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); } } -static char lcd_ss_str[10] = { - 'u', 'n', 'k', 'n', 'o', 'w', 'n', '\0', -}; -char *lcd_get_spread_spectrum(void) +static void lcd_clk_gate_switch_axg(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: mipi_enable_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.mipi_enable_gate); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: mipi_bandgap_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.mipi_bandgap_gate); + } else { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: mipi_enable_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.mipi_enable_gate); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: mipi_bandgap_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.mipi_bandgap_gate); + } +} + +static void lcd_clk_gate_switch_g12a(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (clk_conf.data->vclk_sel) { + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: gp0_pll\n", __func__); + else + clk_prepare_enable(lcd_clktree.gp0_pll); + } + + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + } else { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); + + if (clk_conf.data->vclk_sel) { + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: gp0_pll\n", __func__); + else + clk_disable_unprepare(lcd_clktree.gp0_pll); + } + } +} + +static void lcd_clk_gate_switch_tl1(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: tcon_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.tcon_gate); + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: tcon_clk\n", __func__); + else + clk_prepare_enable(lcd_clktree.tcon_clk); + break; + default: + break; + } + } else { + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: tcon_clk\n", __func__); + else + clk_disable_unprepare(lcd_clktree.tcon_clk); + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: tcon_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.tcon_gate); + break; + default: + break; + } + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); + } +} + +static void lcd_clktree_probe_dft(void) { - char *ss_str; - unsigned int ss_level; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - ss_level = lcd_drv->lcd_config->lcd_timing.ss_level; - ss_level = (ss_level >= clk_conf.ss_level_max) ? 0 : ss_level; - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - ss_str = lcd_pll_ss_table_gxtvbb[ss_level]; - break; - case LCD_CHIP_TXL: - ss_str = lcd_pll_ss_table_txl[ss_level]; - break; - case LCD_CHIP_TXLX: - ss_str = lcd_pll_ss_table_txlx[ss_level]; + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: get encl_top_gate error\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: get encl_int_gate error\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_axg(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate"); + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: clk dsi_host_gate\n", __func__); + + lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate"); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: clk dsi_phy_gate\n", __func__); + + lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas"); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: clk dsi_meas\n", __func__); + + lcd_clktree.mipi_enable_gate = devm_clk_get(lcd_drv->dev, + "mipi_enable_gate"); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: clk mipi_enable_gate\n", __func__); + + lcd_clktree.mipi_bandgap_gate = devm_clk_get(lcd_drv->dev, + "mipi_bandgap_gate"); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: clk mipi_bandgap_gate\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_g12a(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate"); + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: clk dsi_host_gate\n", __func__); + + lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate"); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: clk dsi_phy_gate\n", __func__); + + lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas"); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: clk dsi_meas\n", __func__); + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: clk encl_top_gate\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: clk encl_int_gate\n", __func__); + + lcd_clktree.gp0_pll = devm_clk_get(lcd_drv->dev, "gp0_pll"); + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: clk gp0_pll\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_tl1(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct clk *temp_clk; + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: get encl_top_gate error\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: get encl_int_gate error\n", __func__); + + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + lcd_clktree.tcon_gate = devm_clk_get(lcd_drv->dev, "tcon_gate"); + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: get tcon_gate error\n", __func__); + + temp_clk = devm_clk_get(lcd_drv->dev, "fclk_div5"); + if (IS_ERR(temp_clk)) { + LCDERR("%s: clk fclk_div5\n", __func__); + return; + } + lcd_clktree.tcon_clk = devm_clk_get(lcd_drv->dev, "clk_tcon"); + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: clk clk_tcon\n", __func__); + else + clk_set_parent(lcd_clktree.tcon_clk, temp_clk); break; default: - ss_str = lcd_ss_str; break; } - return ss_str; + LCDPR("lcd_clktree_probe\n"); } -void lcd_set_spread_spectrum(void) +static void lcd_clktree_remove_dft(void) { - unsigned long flags = 0; - int ss_level; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - spin_lock_irqsave(&lcd_clk_lock, flags); + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); +} + +static void lcd_clktree_remove_axg(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.mipi_bandgap_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_bandgap_gate); + if (!IS_ERR(lcd_clktree.mipi_enable_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_enable_gate); + if (!IS_ERR(lcd_clktree.dsi_meas)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas); + if (!IS_ERR(lcd_clktree.dsi_phy_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate); + if (!IS_ERR(lcd_clktree.dsi_host_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate); + if (!IS_ERR(lcd_clktree.gp0_pll)) + devm_clk_put(lcd_drv->dev, lcd_clktree.gp0_pll); +} - ss_level = lcd_drv->lcd_config->lcd_timing.ss_level; - clk_conf.ss_level = (ss_level >= clk_conf.ss_level_max) ? 0 : ss_level; - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_set_pll_ss_gxtvbb(&clk_conf); - break; - case LCD_CHIP_TXL: - lcd_set_pll_ss_txl(&clk_conf); - break; - case LCD_CHIP_TXLX: - lcd_set_pll_ss_txlx(&clk_conf); +static void lcd_clktree_remove_g12a(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.dsi_host_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate); + if (!IS_ERR(lcd_clktree.dsi_phy_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate); + if (!IS_ERR(lcd_clktree.dsi_meas)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas); + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); +} + +static void lcd_clktree_remove_tl1(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); + + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (!IS_ERR(lcd_clktree.tcon_clk)) + devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_clk); + if (IS_ERR(lcd_clktree.tcon_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_gate); break; default: break; } +} + +static void lcd_clk_config_init_print_dft(void) +{ + struct lcd_clk_data_s *data = clk_conf.data; + + LCDPR("lcd clk config data init:\n" + "pll_m_max: %d\n" + "pll_m_min: %d\n" + "pll_n_max: %d\n" + "pll_n_min: %d\n" + "pll_od_fb: %d\n" + "pll_frac_range: %d\n" + "pll_od_sel_max: %d\n" + "pll_ref_fmax: %d\n" + "pll_ref_fmin: %d\n" + "pll_vco_fmax: %d\n" + "pll_vco_fmin: %d\n" + "pll_out_fmax: %d\n" + "pll_out_fmin: %d\n" + "div_in_fmax: %d\n" + "div_out_fmax: %d\n" + "xd_out_fmax: %d\n" + "ss_level_max: %d\n\n", + data->pll_m_max, data->pll_m_min, + data->pll_n_max, data->pll_n_min, + data->pll_od_fb, data->pll_frac_range, + data->pll_od_sel_max, + data->pll_ref_fmax, data->pll_ref_fmin, + data->pll_vco_fmax, data->pll_vco_fmin, + data->pll_out_fmax, data->pll_out_fmin, + data->div_in_fmax, data->div_out_fmax, + data->xd_out_fmax, data->ss_level_max); +} + +static void lcd_clk_config_init_print_axg(void) +{ + struct lcd_clk_data_s *data = clk_conf.data; + + LCDPR("lcd clk config data init:\n" + "vclk_sel: %d\n" + "pll_m_max: %d\n" + "pll_m_min: %d\n" + "pll_n_max: %d\n" + "pll_n_min: %d\n" + "pll_od_fb: %d\n" + "pll_frac_range: %d\n" + "pll_od_sel_max: %d\n" + "pll_ref_fmax: %d\n" + "pll_ref_fmin: %d\n" + "pll_vco_fmax: %d\n" + "pll_vco_fmin: %d\n" + "pll_out_fmax: %d\n" + "pll_out_fmin: %d\n" + "xd_out_fmax: %d\n" + "ss_level_max: %d\n\n", + data->vclk_sel, + data->pll_m_max, data->pll_m_min, + data->pll_n_max, data->pll_n_min, + data->pll_od_fb, data->pll_frac_range, + data->pll_od_sel_max, + data->pll_ref_fmax, data->pll_ref_fmin, + data->pll_vco_fmax, data->pll_vco_fmin, + data->pll_out_fmax, data->pll_out_fmin, + data->xd_out_fmax, data->ss_level_max); +} + +static int lcd_clk_config_print_dft(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lcd clk config:\n" + "pll_mode: %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od1: %d\n" + "pll_od2: %d\n" + "pll_od3: %d\n" + "pll_pi_div_sel: %d\n" + "pll_out: %dkHz\n" + "div_sel: %s(index %d)\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, + clk_conf.pll_od3_sel, clk_conf.pll_pi_div_sel, + clk_conf.pll_fout, + lcd_clk_div_sel_table[clk_conf.div_sel], + clk_conf.div_sel, clk_conf.xd, + clk_conf.fout, clk_conf.ss_level); + + return len; +} + +static int lcd_clk_config_print_axg(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lcd clk config:\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od: %d\n" + "pll_out: %dkHz\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_fout, + clk_conf.xd, clk_conf.fout, clk_conf.ss_level); + + return len; +} + +static int lcd_clk_config_print_g12a(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + if (clk_conf.data->vclk_sel) { + len += snprintf((buf+len), n, + "lcd clk config:\n" + "vclk_sel %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od: %d\n" + "pll_out: %dkHz\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.data->vclk_sel, + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_fout, + clk_conf.xd, clk_conf.fout, clk_conf.ss_level); + } else { + len += snprintf((buf+len), n, + "lcd clk config:\n" + "vclk_sel %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od1: %d\n" + "pll_od2: %d\n" + "pll_od3: %d\n" + "pll_out: %dkHz\n" + "div_sel: %s(index %d)\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.data->vclk_sel, + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, + clk_conf.pll_od3_sel, clk_conf.pll_fout, + lcd_clk_div_sel_table[clk_conf.div_sel], + clk_conf.div_sel, clk_conf.xd, + clk_conf.fout, clk_conf.ss_level); + } + + return len; +} + +/* **************************************************** + * lcd clk function api + * **************************************************** + */ +void lcd_clk_generate_parameter(struct lcd_config_s *pconf) +{ + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; + } + + if (clk_conf.data->clk_generate_parameter) + clk_conf.data->clk_generate_parameter(pconf); +} + +static char lcd_ss_invalid_str[10] = {'i', 'n', 'v', 'a', 'l', 'i', 'd', '\0',}; +char *lcd_get_spread_spectrum(void) +{ + char *ss_str = lcd_ss_invalid_str; + unsigned int level; + + level = clk_conf.ss_level; + if (clk_conf.data) { + level = (level >= clk_conf.data->ss_level_max) ? 0 : level; + if (clk_conf.data->pll_ss_table) + ss_str = clk_conf.data->pll_ss_table[level]; + } + + return ss_str; +} + +void lcd_set_spread_spectrum(unsigned int ss_level) +{ + unsigned long flags = 0; + + spin_lock_irqsave(&lcd_clk_lock, flags); + + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_set_spread_spectrum_end; + } + + clk_conf.ss_level = (ss_level >= clk_conf.data->ss_level_max) ? + 0 : ss_level; + if (clk_conf.data->set_spread_spectrum) + clk_conf.data->set_spread_spectrum(clk_conf.ss_level); + +lcd_set_spread_spectrum_end: spin_unlock_irqrestore(&lcd_clk_lock, flags); + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); } int lcd_encl_clk_msr(void) @@ -2316,144 +2146,99 @@ int lcd_encl_clk_msr(void) void lcd_pll_reset(void) { + struct lcd_clk_ctrl_s *table; + int i = 0; unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); spin_lock_irqsave(&lcd_clk_lock, flags); - LCDPR("%s\n", __func__); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_pll_reset_gxtvbb(); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_pll_reset_txl(); - break; - case LCD_CHIP_AXG: - lcd_pll_reset_axg(); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_gp0_pll_reset_g12a(); - else - lcd_hpll_reset_g12a(); - break; - default: - break; + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_pll_reset_end; } + if (clk_conf.data->pll_ctrl_table == NULL) + goto lcd_pll_reset_end; + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_RST) { + lcd_hiu_setb(table[i].reg, 1, + table[i].bit, table[i].len); + udelay(10); + lcd_hiu_setb(table[i].reg, 0, + table[i].bit, table[i].len); + } + i++; + } + +lcd_pll_reset_end: spin_unlock_irqrestore(&lcd_clk_lock, flags); + LCDPR("%s\n", __func__); } /* for frame rate change */ void lcd_clk_update(struct lcd_config_s *pconf) { + struct lcd_clk_ctrl_s *table; + int i = 0; unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); spin_lock_irqsave(&lcd_clk_lock, flags); - LCDPR("%s\n", __func__); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_pll_frac_generate_gxtvbb(pconf); - lcd_update_pll_frac_gxtvbb(&clk_conf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_pll_frac_generate_txl(pconf); - lcd_update_pll_frac_txl(&clk_conf); - break; - case LCD_CHIP_AXG: - lcd_pll_frac_generate_axg(pconf); - lcd_update_pll_frac_axg(&clk_conf); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - lcd_pll_frac_generate_axg(pconf); - lcd_update_gp0_pll_frac_g12a(&clk_conf); - } else { - lcd_pll_frac_generate_txl(pconf); - lcd_update_hpll_frac_g12a(&clk_conf); + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_clk_update_end; + } + + if (clk_conf.data->pll_frac_generate) + clk_conf.data->pll_frac_generate(pconf); + + if (clk_conf.data->pll_ctrl_table == NULL) + goto lcd_clk_update_end; + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_FRAC) { + lcd_hiu_setb(table[i].reg, clk_conf.pll_frac, + table[i].bit, table[i].len); } - break; - default: - break; + i++; } +lcd_clk_update_end: spin_unlock_irqrestore(&lcd_clk_lock, flags); + LCDPR("%s\n", __func__); } /* for timing change */ void lcd_clk_set(struct lcd_config_s *pconf) { unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - spin_lock_irqsave(&lcd_clk_lock, flags); + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; + } - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); + spin_lock_irqsave(&lcd_clk_lock, flags); + if (clk_conf.data->clk_set) + clk_conf.data->clk_set(pconf); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_set_pll_gxtvbb(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - lcd_set_pll_txl(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_TXLX: - lcd_set_pll_txlx(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_AXG: - lcd_set_pll_axg(&clk_conf); - break; - case LCD_CHIP_G12A: - if (lcd_drv->lcd_clk_path) { /* gp0_pll */ - lcd_set_gp0_pll_g12a(&clk_conf); - lcd_set_dsi_phy_clk(1); - } else { /* hpll */ - lcd_set_hpll_g12a(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - lcd_set_dsi_phy_clk(0); - } - break; - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { /* gp0_pll */ - lcd_set_gp0_pll_g12b(&clk_conf); - lcd_set_dsi_phy_clk(1); - } else { /* hpll */ - lcd_set_hpll_g12b(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - lcd_set_dsi_phy_clk(0); - } - break; - default: - break; - } lcd_set_vclk_crt(pconf->lcd_basic.lcd_type, &clk_conf); mdelay(10); spin_unlock_irqrestore(&lcd_clk_lock, flags); + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); } void lcd_clk_disable(void) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); + struct lcd_clk_ctrl_s *table; + int i = 0; lcd_hiu_setb(HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1); @@ -2461,38 +2246,23 @@ void lcd_clk_disable(void) lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, 0, 5); lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); - /* disable pll */ - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_EN_GXTVBB, 1); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL5, 0, 30, 1); /* bandgap */ - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_EN_TXL, 1); - break; - case LCD_CHIP_AXG: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 0, LCD_PLL_EN_AXG, 1); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, - 0, LCD_PLL_EN_GP0_G12A, 1); - } else { - /* disable hdmi_pll: 0x10c8[28] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, - 0, LCD_PLL_EN_HPLL_G12A, 1); + if (clk_conf.data == NULL) + return; + if (clk_conf.data->pll_ctrl_table == NULL) + return; + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_EN) { + lcd_hiu_setb(table[i].reg, 0, + table[i].bit, table[i].len); } - break; - default: - break; + i++; } + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); } void lcd_clk_gate_switch(int status) @@ -2500,298 +2270,479 @@ void lcd_clk_gate_switch(int status) struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (status) { - if (lcd_drv->clk_gate_state) { + if (lcd_clktree.clk_gate_state) { LCDPR("clk gate is already on\n"); return; } - #ifdef CONFIG_AMLOGIC_VPU switch_vpu_clk_gate_vmod(VPU_VENCL, VPU_CLK_GATE_ON); #endif - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: mipi_enable_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->mipi_enable_gate); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: mipi_bandgap_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->mipi_bandgap_gate); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: gp0_pll\n", __func__); - else - clk_prepare_enable(lcd_drv->gp0_pll); - } - - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_top_gate); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_int_gate); - break; - default: - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_top_gate); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_int_gate); - break; + if (clk_conf.data) { + if (clk_conf.data->clk_gate_switch) + clk_conf.data->clk_gate_switch(lcd_drv, 1); } - lcd_drv->clk_gate_state = 1; + lcd_clktree.clk_gate_state = 1; } else { - if (lcd_drv->clk_gate_state == 0) { + if (lcd_clktree.clk_gate_state == 0) { LCDPR("clk gate is already off\n"); return; } - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: mipi_enable_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->mipi_enable_gate); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: mipi_bandgap_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->mipi_bandgap_gate); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->encl_int_gate); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->encl_top_gate); - - if (lcd_drv->lcd_clk_path) { - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: gp0_pll\n", __func__); - else - clk_disable_unprepare(lcd_drv->gp0_pll); - } - break; - default: - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_disable_unprepare(lcd_drv->encl_int_gate); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gata\n", __func__); - else - clk_disable_unprepare(lcd_drv->encl_top_gate); - break; + if (clk_conf.data) { + if (clk_conf.data->clk_gate_switch) + clk_conf.data->clk_gate_switch(lcd_drv, 0); } #ifdef CONFIG_AMLOGIC_VPU switch_vpu_clk_gate_vmod(VPU_VENCL, VPU_CLK_GATE_OFF); #endif - lcd_drv->clk_gate_state = 0; + lcd_clktree.clk_gate_state = 0; } } -static void lcd_clktree_probe(void) +static void lcd_clk_config_init_print(void) +{ + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; + } + + if (clk_conf.data->clk_config_init_print) + clk_conf.data->clk_config_init_print(); +} + +int lcd_clk_config_print(char *buf, int offset) +{ + int n, len = 0; + + if (clk_conf.data == NULL) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "%s: clk config data is null\n", + __func__); + return len; + } + + if (clk_conf.data->clk_config_print) + len = clk_conf.data->clk_config_print(buf, offset); + + return len; +} + +/* **************************************************** + * lcd clk config + * **************************************************** + */ +static struct lcd_clk_data_s lcd_clk_data_gxl = { + .pll_od_fb = PLL_OD_FB_GXL, + .pll_m_max = PLL_M_MAX_GXL, + .pll_m_min = PLL_M_MIN_GXL, + .pll_n_max = PLL_N_MAX_GXL, + .pll_n_min = PLL_N_MIN_GXL, + .pll_frac_range = PLL_FRAC_RANGE_GXL, + .pll_od_sel_max = PLL_OD_SEL_MAX_GXL, + .pll_ref_fmax = PLL_FREF_MAX_GXL, + .pll_ref_fmin = PLL_FREF_MIN_GXL, + .pll_vco_fmax = PLL_VCO_MAX_GXL, + .pll_vco_fmin = PLL_VCO_MIN_GXL, + .pll_out_fmax = CLK_DIV_IN_MAX_GXL, + .pll_out_fmin = PLL_VCO_MIN_GXL / 16, + .div_in_fmax = CLK_DIV_IN_MAX_GXL, + .div_out_fmax = CRT_VID_CLK_IN_MAX_GXL, + .xd_out_fmax = ENCL_CLK_IN_MAX_GXL, + .ss_level_max = SS_LEVEL_MAX_GXL, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_txl, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_txl = { + .pll_od_fb = PLL_OD_FB_TXL, + .pll_m_max = PLL_M_MAX_TXL, + .pll_m_min = PLL_M_MIN_TXL, + .pll_n_max = PLL_N_MAX_TXL, + .pll_n_min = PLL_N_MIN_TXL, + .pll_frac_range = PLL_FRAC_RANGE_TXL, + .pll_od_sel_max = PLL_OD_SEL_MAX_TXL, + .pll_ref_fmax = PLL_FREF_MAX_TXL, + .pll_ref_fmin = PLL_FREF_MIN_TXL, + .pll_vco_fmax = PLL_VCO_MAX_TXL, + .pll_vco_fmin = PLL_VCO_MIN_TXL, + .pll_out_fmax = CLK_DIV_IN_MAX_TXL, + .pll_out_fmin = PLL_VCO_MIN_TXL / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TXL, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TXL, + .xd_out_fmax = ENCL_CLK_IN_MAX_TXL, + .ss_level_max = SS_LEVEL_MAX_TXL, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = lcd_pll_ss_table_txl, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = lcd_set_pll_ss_txl, + .clk_set = lcd_clk_set_txl, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_txlx = { + .pll_od_fb = PLL_OD_FB_TXLX, + .pll_m_max = PLL_M_MAX_TXLX, + .pll_m_min = PLL_M_MIN_TXLX, + .pll_n_max = PLL_N_MAX_TXLX, + .pll_n_min = PLL_N_MIN_TXLX, + .pll_frac_range = PLL_FRAC_RANGE_TXLX, + .pll_od_sel_max = PLL_OD_SEL_MAX_TXLX, + .pll_ref_fmax = PLL_FREF_MAX_TXLX, + .pll_ref_fmin = PLL_FREF_MIN_TXLX, + .pll_vco_fmax = PLL_VCO_MAX_TXLX, + .pll_vco_fmin = PLL_VCO_MIN_TXLX, + .pll_out_fmax = CLK_DIV_IN_MAX_TXLX, + .pll_out_fmin = PLL_VCO_MIN_TXLX / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TXLX, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TXLX, + .xd_out_fmax = ENCL_CLK_IN_MAX_TXLX, + .ss_level_max = SS_LEVEL_MAX_TXLX, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = lcd_pll_ss_table_txlx, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = lcd_set_pll_ss_txlx, + .clk_set = lcd_clk_set_txlx, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_axg = { + .pll_od_fb = PLL_OD_FB_AXG, + .pll_m_max = PLL_M_MAX_AXG, + .pll_m_min = PLL_M_MIN_AXG, + .pll_n_max = PLL_N_MAX_AXG, + .pll_n_min = PLL_N_MIN_AXG, + .pll_frac_range = PLL_FRAC_RANGE_AXG, + .pll_od_sel_max = PLL_OD_SEL_MAX_AXG, + .pll_ref_fmax = PLL_FREF_MAX_AXG, + .pll_ref_fmin = PLL_FREF_MIN_AXG, + .pll_vco_fmax = PLL_VCO_MAX_AXG, + .pll_vco_fmin = PLL_VCO_MIN_AXG, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_AXG, + .pll_out_fmin = PLL_VCO_MIN_AXG / 4, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_AXG, + .xd_out_fmax = ENCL_CLK_IN_MAX_AXG, + .ss_level_max = SS_LEVEL_MAX_AXG, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_axg, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_axg, + .clk_gate_switch = lcd_clk_gate_switch_axg, + .clktree_probe = lcd_clktree_probe_axg, + .clktree_remove = lcd_clktree_remove_axg, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_axg, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12a_path0 = { + .pll_od_fb = PLL_OD_FB_HPLL_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A, + .pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_HPLL_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_HPLL_G12A, + + .clk_path_valid = 1, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_g12a_path0, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_hpll_g12a, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12a_path0, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12a_path1 = { + .pll_od_fb = PLL_OD_FB_GP0_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_GP0_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_GP0_G12A, + .pll_vco_fmin = PLL_VCO_MIN_GP0_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_GP0_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_GP0_G12A, + + .clk_path_valid = 1, + .vclk_sel = 1, + .pll_ctrl_table = pll_ctrl_table_g12a_path1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12a_path1, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12b_path0 = { + .pll_od_fb = PLL_OD_FB_HPLL_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A, + .pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_HPLL_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_HPLL_G12A, + + .clk_path_valid = 1, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_g12a_path0, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_hpll_g12a, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12b_path0, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12b_path1 = { + .pll_od_fb = PLL_OD_FB_GP0_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_GP0_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_GP0_G12A, + .pll_vco_fmin = PLL_VCO_MIN_GP0_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_GP0_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_GP0_G12A, + + .clk_path_valid = 1, + .vclk_sel = 1, + .pll_ctrl_table = pll_ctrl_table_g12a_path1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12b_path1, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_tl1 = { + .pll_od_fb = PLL_OD_FB_TL1, + .pll_m_max = PLL_M_MAX_TL1, + .pll_m_min = PLL_M_MIN_TL1, + .pll_n_max = PLL_N_MAX_TL1, + .pll_n_min = PLL_N_MIN_TL1, + .pll_frac_range = PLL_FRAC_RANGE_TL1, + .pll_od_sel_max = PLL_OD_SEL_MAX_TL1, + .pll_ref_fmax = PLL_FREF_MAX_TL1, + .pll_ref_fmin = PLL_FREF_MIN_TL1, + .pll_vco_fmax = PLL_VCO_MAX_TL1, + .pll_vco_fmin = PLL_VCO_MIN_TL1, + .pll_out_fmax = CLK_DIV_IN_MAX_TL1, + .pll_out_fmin = PLL_VCO_MIN_TL1 / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TL1, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TL1, + .xd_out_fmax = ENCL_CLK_IN_MAX_TL1, + .ss_level_max = SS_LEVEL_MAX_TL1, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_tl1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_tl1, + .clk_gate_switch = lcd_clk_gate_switch_tl1, + .clktree_probe = lcd_clktree_probe_tl1, + .clktree_remove = lcd_clktree_remove_tl1, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static void lcd_clk_config_chip_init(struct lcd_clk_config_s *cConf) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - lcd_drv->clk_gate_state = 0; switch (lcd_drv->data->chip_type) { + case LCD_CHIP_GXL: + case LCD_CHIP_GXM: + cConf->data = &lcd_clk_data_gxl; + break; + case LCD_CHIP_TXL: + cConf->data = &lcd_clk_data_txl; + break; + case LCD_CHIP_TXLX: + cConf->data = &lcd_clk_data_txlx; + break; case LCD_CHIP_AXG: - lcd_drv->dsi_host_gate = devm_clk_get(lcd_drv->dev, - "dsi_host_gate"); - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: clk dsi_host_gate\n", __func__); - - lcd_drv->dsi_phy_gate = devm_clk_get(lcd_drv->dev, - "dsi_phy_gate"); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: clk dsi_phy_gate\n", __func__); - - lcd_drv->dsi_meas = devm_clk_get(lcd_drv->dev, - "dsi_meas"); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: clk dsi_meas\n", __func__); - - lcd_drv->mipi_enable_gate = devm_clk_get( - lcd_drv->dev, "mipi_enable_gate"); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: clk mipi_enable_gate\n", __func__); - - lcd_drv->mipi_bandgap_gate = devm_clk_get( - lcd_drv->dev, "mipi_bandgap_gate"); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: clk mipi_bandgap_gate\n", __func__); + cConf->data = &lcd_clk_data_axg; break; case LCD_CHIP_G12A: + if (lcd_drv->lcd_clk_path) + cConf->data = &lcd_clk_data_g12a_path1; + else + cConf->data = &lcd_clk_data_g12a_path0; + break; case LCD_CHIP_G12B: - lcd_drv->dsi_host_gate = devm_clk_get(lcd_drv->dev, - "dsi_host_gate"); - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: clk dsi_host_gate\n", __func__); - - lcd_drv->dsi_phy_gate = devm_clk_get(lcd_drv->dev, - "dsi_phy_gate"); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: clk dsi_phy_gate\n", __func__); - - lcd_drv->dsi_meas = devm_clk_get(lcd_drv->dev, - "dsi_meas"); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: clk dsi_meas\n", __func__); - - lcd_drv->encl_top_gate = devm_clk_get( - lcd_drv->dev, "encl_top_gate"); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: clk encl_top_gate\n", __func__); - - lcd_drv->encl_int_gate = devm_clk_get( - lcd_drv->dev, "encl_int_gate"); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: clk encl_int_gate\n", __func__); - - lcd_drv->gp0_pll = devm_clk_get(lcd_drv->dev, "gp0_pll"); - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: clk gp0_pll\n", __func__); + if (lcd_drv->lcd_clk_path) + cConf->data = &lcd_clk_data_g12b_path1; + else + cConf->data = &lcd_clk_data_g12b_path0; + break; + case LCD_CHIP_TL1: + cConf->data = &lcd_clk_data_tl1; break; default: - lcd_drv->encl_top_gate = devm_clk_get(lcd_drv->dev, - "encl_top_gate"); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: get encl_top_gate error\n", __func__); - - lcd_drv->encl_int_gate = devm_clk_get(lcd_drv->dev, - "encl_int_gate"); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: get encl_int_gate error\n", __func__); + LCDPR("%s: invalid chip type\n", __func__); break; } - LCDPR("%s\n", __func__); + if (cConf->data) + cConf->pll_od_fb = cConf->data->pll_od_fb; + if (lcd_debug_print_flag > 0) + lcd_clk_config_init_print(); } -static void lcd_clktree_remove(void) +int lcd_clk_path_change(int sel) { + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); + if (cConf->data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return -1; + } + + if (cConf->data->clk_path_valid == 0) { + LCDPR("%s: current chip not support\n", __func__); + return -1; + } switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - if (!IS_ERR(lcd_drv->mipi_bandgap_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->mipi_bandgap_gate); - if (!IS_ERR(lcd_drv->mipi_enable_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->mipi_enable_gate); - if (!IS_ERR(lcd_drv->dsi_meas)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_meas); - if (!IS_ERR(lcd_drv->dsi_phy_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_phy_gate); - if (!IS_ERR(lcd_drv->dsi_host_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate); - if (!IS_ERR(lcd_drv->gp0_pll)) - devm_clk_put(lcd_drv->dev, lcd_drv->gp0_pll); - break; case LCD_CHIP_G12A: case LCD_CHIP_G12B: - if (!IS_ERR(lcd_drv->dsi_host_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate); - if (!IS_ERR(lcd_drv->dsi_phy_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_phy_gate); - if (!IS_ERR(lcd_drv->dsi_meas)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_meas); - if (!IS_ERR(lcd_drv->encl_top_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_top_gate); - if (!IS_ERR(lcd_drv->encl_int_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_int_gate); + if (sel) + cConf->data = &lcd_clk_data_g12a_path1; + else + cConf->data = &lcd_clk_data_g12a_path0; + cConf->pll_od_fb = cConf->data->pll_od_fb; + + if (lcd_debug_print_flag > 0) + lcd_clk_config_init_print(); break; default: - if (!IS_ERR(lcd_drv->encl_top_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_top_gate); - if (!IS_ERR(lcd_drv->encl_int_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_int_gate); - break; + LCDERR("%s: current chip not support\n", __func__); + return -1; } + + return 0; } void lcd_clk_config_probe(void) { spin_lock_init(&lcd_clk_lock); - lcd_clk_config_chip_init(); - lcd_clktree_probe(); + lcd_clk_config_chip_init(&clk_conf); + if (clk_conf.data == NULL) + return; + + if (clk_conf.data->clktree_probe) + clk_conf.data->clktree_probe(); } void lcd_clk_config_remove(void) { - lcd_clktree_remove(); + if (clk_conf.data == NULL) + return; + + if (clk_conf.data->clktree_remove) + clk_conf.data->clktree_remove(); } diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h index b2ab734..8a52cda 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h @@ -25,6 +25,56 @@ * clk config * ********************************** */ +#define LCD_CLK_CTRL_EN 0 +#define LCD_CLK_CTRL_RST 1 +#define LCD_CLK_CTRL_FRAC 2 +#define LCD_CLK_CTRL_END 0xffff + +#define LCD_CLK_REG_END 0xffff +#define LCD_CLK_CTRL_CNT_MAX 10 +struct lcd_clk_ctrl_s { + unsigned int flag; + unsigned int reg; + unsigned int bit; + unsigned int len; +}; + +struct lcd_clk_data_s { + /* clk path node parameters */ + unsigned int pll_od_fb; + unsigned int pll_m_max; + unsigned int pll_m_min; + unsigned int pll_n_max; + unsigned int pll_n_min; + unsigned int pll_frac_range; + unsigned int pll_od_sel_max; + unsigned int pll_ref_fmax; + unsigned int pll_ref_fmin; + unsigned int pll_vco_fmax; + unsigned int pll_vco_fmin; + unsigned int pll_out_fmax; + unsigned int pll_out_fmin; + unsigned int div_in_fmax; + unsigned int div_out_fmax; + unsigned int xd_out_fmax; + unsigned int ss_level_max; + + unsigned char clk_path_valid; + unsigned char vclk_sel; + struct lcd_clk_ctrl_s *pll_ctrl_table; + char **pll_ss_table; + + void (*clk_generate_parameter)(struct lcd_config_s *pconf); + void (*pll_frac_generate)(struct lcd_config_s *pconf); + void (*set_spread_spectrum)(unsigned int ss_level); + void (*clk_set)(struct lcd_config_s *pconf); + void (*clk_gate_switch)(struct aml_lcd_drv_s *lcd_drv, int status); + void (*clktree_probe)(void); + void (*clktree_remove)(void); + void (*clk_config_init_print)(void); + int (*clk_config_print)(char *buf, int offset); +}; + struct lcd_clk_config_s { /* unit: kHz */ /* IN-OUT parameters */ unsigned int fin; @@ -32,355 +82,60 @@ struct lcd_clk_config_s { /* unit: kHz */ /* pll parameters */ unsigned int pll_mode; /* txl */ - unsigned int od_fb; + unsigned int pll_od_fb; unsigned int pll_m; unsigned int pll_n; unsigned int pll_fvco; unsigned int pll_od1_sel; unsigned int pll_od2_sel; unsigned int pll_od3_sel; + unsigned int pll_pi_div_sel; /* for tcon */ unsigned int pll_level; unsigned int pll_frac; unsigned int pll_fout; unsigned int ss_level; unsigned int div_sel; unsigned int xd; - - /* clk path node parameters */ - unsigned int ss_level_max; - unsigned int pll_m_max; - unsigned int pll_m_min; - unsigned int pll_n_max; - unsigned int pll_n_min; - unsigned int pll_frac_range; - unsigned int pll_od_sel_max; unsigned int div_sel_max; unsigned int xd_max; - unsigned int pll_ref_fmax; - unsigned int pll_ref_fmin; - unsigned int pll_vco_fmax; - unsigned int pll_vco_fmin; - unsigned int pll_out_fmax; - unsigned int pll_out_fmin; - unsigned int div_in_fmax; - unsigned int div_out_fmax; - unsigned int xd_out_fmax; unsigned int err_fmin; -}; - -/* ********************************** - * pll & clk parameter - * ********************************** - */ -/* ******** clk calculation ******** */ -#define PLL_WAIT_LOCK_CNT 200 - /* frequency unit: kHz */ -#define FIN_FREQ (24 * 1000) -/* clk max error */ -#define MAX_ERROR (2 * 1000) -/* ******** register bit ******** */ -/* divider */ -#define CRT_VID_DIV_MAX 255 - -#define DIV_PRE_SEL_MAX 6 -#define EDP_DIV0_SEL_MAX 15 -#define EDP_DIV1_SEL_MAX 8 - -/* g9tv, g9bb, gxbb divider */ -#define CLK_DIV_I2O 0 -#define CLK_DIV_O2I 1 -enum div_sel_e { - CLK_DIV_SEL_1 = 0, - CLK_DIV_SEL_2, /* 1 */ - CLK_DIV_SEL_3, /* 2 */ - CLK_DIV_SEL_3p5, /* 3 */ - CLK_DIV_SEL_3p75, /* 4 */ - CLK_DIV_SEL_4, /* 5 */ - CLK_DIV_SEL_5, /* 6 */ - CLK_DIV_SEL_6, /* 7 */ - CLK_DIV_SEL_6p25, /* 8 */ - CLK_DIV_SEL_7, /* 9 */ - CLK_DIV_SEL_7p5, /* 10 */ - CLK_DIV_SEL_12, /* 11 */ - CLK_DIV_SEL_14, /* 12 */ - CLK_DIV_SEL_15, /* 13 */ - CLK_DIV_SEL_2p5, /* 14 */ - CLK_DIV_SEL_MAX, + struct lcd_clk_data_s *data; }; +struct lcd_clktree_s { + unsigned char clk_gate_state; -/* ********************************** - * GXTVBB - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXTVBB 31 -#define LCD_PLL_EN_GXTVBB 30 -#define LCD_PLL_RST_GXTVBB 28 -#define LCD_PLL_N_GXTVBB 9 -#define LCD_PLL_M_GXTVBB 0 - -#define LCD_PLL_OD3_GXTVBB 18 -#define LCD_PLL_OD2_GXTVBB 22 -#define LCD_PLL_OD1_GXTVBB 16 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXTVBB 0 -#define SS_LEVEL_MAX_GXTVBB 5 -#define PLL_M_MIN_GXTVBB 2 -#define PLL_M_MAX_GXTVBB 511 -#define PLL_N_MIN_GXTVBB 1 -#define PLL_N_MAX_GXTVBB 1 -#define PLL_FRAC_RANGE_GXTVBB (1 << 10) -#define PLL_OD_SEL_MAX_GXTVBB 3 -#define PLL_FREF_MIN_GXTVBB (5 * 1000) -#define PLL_FREF_MAX_GXTVBB (25 * 1000) -#define PLL_VCO_MIN_GXTVBB (3000 * 1000) -#define PLL_VCO_MAX_GXTVBB (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXTVBB (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXTVBB (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXTVBB (620 * 1000) - -/* ********************************** - * GXL - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXL 31 -#define LCD_PLL_EN_GXL 30 -#define LCD_PLL_RST_GXL 28 -#define LCD_PLL_N_GXL 9 -#define LCD_PLL_M_GXL 0 - -#define LCD_PLL_OD3_GXL 19 -#define LCD_PLL_OD2_GXL 23 -#define LCD_PLL_OD1_GXL 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXL 1 -#define SS_LEVEL_MAX_GXL 5 -#define PLL_M_MIN_GXL 2 -#define PLL_M_MAX_GXL 511 -#define PLL_N_MIN_GXL 1 -#define PLL_N_MAX_GXL 1 -#define PLL_FRAC_RANGE_GXL (1 << 10) -#define PLL_OD_SEL_MAX_GXL 3 -#define PLL_FREF_MIN_GXL (5 * 1000) -#define PLL_FREF_MAX_GXL (25 * 1000) -#define PLL_VCO_MIN_GXL (3000 * 1000) -#define PLL_VCO_MAX_GXL (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXL (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXL (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXL (620 * 1000) - -/* ********************************** - * GXM - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXM 31 -#define LCD_PLL_EN_GXM 30 -#define LCD_PLL_RST_GXM 28 -#define LCD_PLL_N_GXM 9 -#define LCD_PLL_M_GXM 0 - -#define LCD_PLL_OD3_GXM 19 -#define LCD_PLL_OD2_GXM 23 -#define LCD_PLL_OD1_GXM 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXM 1 -#define SS_LEVEL_MAX_GXM 5 -#define PLL_M_MIN_GXM 2 -#define PLL_M_MAX_GXM 511 -#define PLL_N_MIN_GXM 1 -#define PLL_N_MAX_GXM 1 -#define PLL_FRAC_RANGE_GXM (1 << 10) -#define PLL_OD_SEL_MAX_GXM 3 -#define PLL_FREF_MIN_GXM (5 * 1000) -#define PLL_FREF_MAX_GXM (25 * 1000) -#define PLL_VCO_MIN_GXM (3000 * 1000) -#define PLL_VCO_MAX_GXM (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXM (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXM (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXM (620 * 1000) - -/* ********************************** - * TXL - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_TXL 31 -#define LCD_PLL_EN_TXL 30 -#define LCD_PLL_RST_TXL 28 -#define LCD_PLL_N_TXL 9 -#define LCD_PLL_M_TXL 0 - -#define LCD_PLL_OD3_TXL 19 -#define LCD_PLL_OD2_TXL 23 -#define LCD_PLL_OD1_TXL 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_TXL 1 /* update od_fb to 1 for ss width */ -#define SS_LEVEL_MAX_TXL 5 -#define PLL_M_MIN_TXL 2 -#define PLL_M_MAX_TXL 511 -#define PLL_N_MIN_TXL 1 -#define PLL_N_MAX_TXL 1 -#define PLL_FRAC_RANGE_TXL (1 << 10) -#define PLL_OD_SEL_MAX_TXL 3 -#define PLL_FREF_MIN_TXL (5 * 1000) -#define PLL_FREF_MAX_TXL (25 * 1000) -#define PLL_VCO_MIN_TXL (2950 * 1000) -#define PLL_VCO_MAX_TXL (5900 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_TXL (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_TXL (3100 * 1000) -#define ENCL_CLK_IN_MAX_TXL (620 * 1000) - -/* ********************************** - * TXLX - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_TXLX 31 -#define LCD_PLL_EN_TXLX 30 -#define LCD_PLL_RST_TXLX 28 -#define LCD_PLL_N_TXLX 9 -#define LCD_PLL_M_TXLX 0 - -#define LCD_PLL_OD3_TXLX 19 -#define LCD_PLL_OD2_TXLX 23 -#define LCD_PLL_OD1_TXLX 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_TXLX 0 -#define SS_LEVEL_MAX_TXLX 6 -#define PLL_M_MIN_TXLX 2 -#define PLL_M_MAX_TXLX 511 -#define PLL_N_MIN_TXLX 1 -#define PLL_N_MAX_TXLX 1 -#define PLL_FRAC_RANGE_TXLX (1 << 10) -#define PLL_OD_SEL_MAX_TXLX 3 -#define PLL_FREF_MIN_TXLX (5 * 1000) -#define PLL_FREF_MAX_TXLX (25 * 1000) -#define PLL_VCO_MIN_TXLX (3000 * 1000) -#define PLL_VCO_MAX_TXLX (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_TXLX (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_TXLX (3100 * 1000) -#define ENCL_CLK_IN_MAX_TXLX (620 * 1000) - -/* ********************************** - * AXG - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL */ -#define LCD_PLL_LOCK_AXG 31 -#define LCD_PLL_EN_AXG 30 -#define LCD_PLL_RST_AXG 29 -#define LCD_PLL_OD_AXG 16 -#define LCD_PLL_N_AXG 9 -#define LCD_PLL_M_AXG 0 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_AXG 0 -#define SS_LEVEL_MAX_AXG 5 -#define PLL_M_MIN_AXG 2 -#define PLL_M_MAX_AXG 511 -#define PLL_N_MIN_AXG 1 -#define PLL_N_MAX_AXG 1 -#define PLL_FRAC_RANGE_AXG (1 << 10) -#define PLL_OD_SEL_MAX_AXG 3 -#define PLL_FREF_MIN_AXG (5 * 1000) -#define PLL_FREF_MAX_AXG (25 * 1000) -#define PLL_VCO_MIN_AXG (960 * 1000) -#define PLL_VCO_MAX_AXG (1920 * 1000) - -/* video */ -#define CRT_VID_CLK_IN_MAX_AXG (1920 * 1000) -#define ENCL_CLK_IN_MAX_AXG (200 * 1000) - -/* G12A */ -/* ******** register bit ******** */ -/* PLL_CNTL bit: GP0 */ -#define LCD_PLL_LOCK_GP0_G12A 31 -#define LCD_PLL_EN_GP0_G12A 28 -#define LCD_PLL_RST_GP0_G12A 29 -#define LCD_PLL_OD_GP0_G12A 16 -#define LCD_PLL_N_GP0_G12A 10 -#define LCD_PLL_M_GP0_G12A 0 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GP0_G12A 0 -#define SS_LEVEL_MAX_GP0_G12A 1 -#define PLL_FRAC_RANGE_GP0_G12A (1 << 17) -#define PLL_OD_SEL_MAX_GP0_G12A 5 -#define PLL_VCO_MIN_GP0_G12A (3000 * 1000) -#define PLL_VCO_MAX_GP0_G12A (6000 * 1000) - -/* PLL_CNTL bit: hpll */ -#define LCD_PLL_LOCK_HPLL_G12A 31 -#define LCD_PLL_EN_HPLL_G12A 28 -#define LCD_PLL_RST_HPLL_G12A 29 -#define LCD_PLL_N_HPLL_G12A 10 -#define LCD_PLL_M_HPLL_G12A 0 - -#define LCD_PLL_OD3_HPLL_G12A 20 -#define LCD_PLL_OD2_HPLL_G12A 18 -#define LCD_PLL_OD1_HPLL_G12A 16 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_HPLL_G12A 0 -#define SS_LEVEL_MAX_HPLL_G12A 1 -#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17) -#define PLL_OD_SEL_MAX_HPLL_G12A 3 -#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000) -#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000) - -/* video */ -#define PLL_M_MIN_G12A 2 -#define PLL_M_MAX_G12A 511 -#define PLL_N_MIN_G12A 1 -#define PLL_N_MAX_G12A 1 -#define PLL_FREF_MIN_G12A (5 * 1000) -#define PLL_FREF_MAX_G12A (25 * 1000) -#define CRT_VID_CLK_IN_MAX_G12A (6000 * 1000) -#define ENCL_CLK_IN_MAX_G12A (200 * 1000) + struct clk *encl_top_gate; + struct clk *encl_int_gate; + struct clk *dsi_host_gate; + struct clk *dsi_phy_gate; + struct clk *dsi_meas; + struct clk *mipi_enable_gate; + struct clk *mipi_bandgap_gate; + struct clk *gp0_pll; + struct clk *tcon_gate; + struct clk *tcon_clk; +}; /* ******** api ******** */ extern int meson_clk_measure(unsigned int clk_mux); extern int lcd_debug_info_len(int num); extern struct lcd_clk_config_s *get_lcd_clk_config(void); -extern int lcd_clk_path_change(int sel); extern int lcd_clk_config_print(char *buf, int offset); extern int lcd_encl_clk_msr(void); extern void lcd_pll_reset(void); extern char *lcd_get_spread_spectrum(void); -extern void lcd_set_spread_spectrum(void); +extern void lcd_set_spread_spectrum(unsigned int ss_level); extern void lcd_clk_update(struct lcd_config_s *pconf); extern void lcd_clk_set(struct lcd_config_s *pconf); extern void lcd_clk_disable(void); extern void lcd_clk_generate_parameter(struct lcd_config_s *pconf); extern void lcd_clk_gate_switch(int status); +extern int lcd_clk_path_change(int sel); extern void lcd_clk_config_probe(void); extern void lcd_clk_config_remove(void); diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h new file mode 100644 index 0000000..928ba65 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h @@ -0,0 +1,417 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _LCD_CLK_CONFIG_CTRL_H +#define _LCD_CLK_CONFIG_CTRL_H + +#include "lcd_reg.h" +#include "lcd_clk_config.h" + +/* ********************************** + * GXL + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_GXL 31 +#define LCD_PLL_EN_GXL 30 +#define LCD_PLL_RST_GXL 28 +#define LCD_PLL_N_GXL 9 +#define LCD_PLL_M_GXL 0 + +#define LCD_PLL_OD3_GXL 19 +#define LCD_PLL_OD2_GXL 23 +#define LCD_PLL_OD1_GXL 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_GXL 1 +#define PLL_M_MIN_GXL 2 +#define PLL_M_MAX_GXL 511 +#define PLL_N_MIN_GXL 1 +#define PLL_N_MAX_GXL 1 +#define PLL_FRAC_RANGE_GXL (1 << 10) +#define PLL_OD_SEL_MAX_GXL 3 +#define PLL_FREF_MIN_GXL (5 * 1000) +#define PLL_FREF_MAX_GXL (25 * 1000) +#define PLL_VCO_MIN_GXL (3000 * 1000) +#define PLL_VCO_MAX_GXL (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_GXL (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_GXL (3100 * 1000) +#define ENCL_CLK_IN_MAX_GXL (620 * 1000) + +/* ********************************** + * TXL + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_TXL 31 +#define LCD_PLL_EN_TXL 30 +#define LCD_PLL_RST_TXL 28 +#define LCD_PLL_N_TXL 9 +#define LCD_PLL_M_TXL 0 + +#define LCD_PLL_OD3_TXL 19 +#define LCD_PLL_OD2_TXL 23 +#define LCD_PLL_OD1_TXL 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TXL 1 /* update od_fb to 1 for ss width */ +#define PLL_M_MIN_TXL 2 +#define PLL_M_MAX_TXL 511 +#define PLL_N_MIN_TXL 1 +#define PLL_N_MAX_TXL 1 +#define PLL_FRAC_RANGE_TXL (1 << 10) +#define PLL_OD_SEL_MAX_TXL 3 +#define PLL_FREF_MIN_TXL (5 * 1000) +#define PLL_FREF_MAX_TXL (25 * 1000) +#define PLL_VCO_MIN_TXL (2950 * 1000) +#define PLL_VCO_MAX_TXL (5900 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TXL (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TXL (3100 * 1000) +#define ENCL_CLK_IN_MAX_TXL (620 * 1000) + +/* ********************************** + * TXLX + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_TXLX 31 +#define LCD_PLL_EN_TXLX 30 +#define LCD_PLL_RST_TXLX 28 +#define LCD_PLL_N_TXLX 9 +#define LCD_PLL_M_TXLX 0 + +#define LCD_PLL_OD3_TXLX 19 +#define LCD_PLL_OD2_TXLX 23 +#define LCD_PLL_OD1_TXLX 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TXLX 0 +#define PLL_M_MIN_TXLX 2 +#define PLL_M_MAX_TXLX 511 +#define PLL_N_MIN_TXLX 1 +#define PLL_N_MAX_TXLX 1 +#define PLL_FRAC_RANGE_TXLX (1 << 10) +#define PLL_OD_SEL_MAX_TXLX 3 +#define PLL_FREF_MIN_TXLX (5 * 1000) +#define PLL_FREF_MAX_TXLX (25 * 1000) +#define PLL_VCO_MIN_TXLX (3000 * 1000) +#define PLL_VCO_MAX_TXLX (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TXLX (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TXLX (3100 * 1000) +#define ENCL_CLK_IN_MAX_TXLX (620 * 1000) + +/* ********************************** + * AXG + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL */ +#define LCD_PLL_LOCK_AXG 31 +#define LCD_PLL_EN_AXG 30 +#define LCD_PLL_RST_AXG 29 +#define LCD_PLL_OD_AXG 16 +#define LCD_PLL_N_AXG 9 +#define LCD_PLL_M_AXG 0 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_AXG 0 +#define PLL_M_MIN_AXG 2 +#define PLL_M_MAX_AXG 511 +#define PLL_N_MIN_AXG 1 +#define PLL_N_MAX_AXG 1 +#define PLL_FRAC_RANGE_AXG (1 << 10) +#define PLL_OD_SEL_MAX_AXG 3 +#define PLL_FREF_MIN_AXG (5 * 1000) +#define PLL_FREF_MAX_AXG (25 * 1000) +#define PLL_VCO_MIN_AXG (960 * 1000) +#define PLL_VCO_MAX_AXG (1920 * 1000) + +/* video */ +#define CRT_VID_CLK_IN_MAX_AXG (1920 * 1000) +#define ENCL_CLK_IN_MAX_AXG (200 * 1000) + +/* G12A */ +/* ******** register bit ******** */ +/* PLL_CNTL bit: GP0 */ +#define LCD_PLL_LOCK_GP0_G12A 31 +#define LCD_PLL_EN_GP0_G12A 28 +#define LCD_PLL_RST_GP0_G12A 29 +#define LCD_PLL_OD_GP0_G12A 16 +#define LCD_PLL_N_GP0_G12A 10 +#define LCD_PLL_M_GP0_G12A 0 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_GP0_G12A 0 +#define PLL_FRAC_RANGE_GP0_G12A (1 << 17) +#define PLL_OD_SEL_MAX_GP0_G12A 5 +#define PLL_VCO_MIN_GP0_G12A (3000 * 1000) +#define PLL_VCO_MAX_GP0_G12A (6000 * 1000) + +/* PLL_CNTL bit: hpll */ +#define LCD_PLL_LOCK_HPLL_G12A 31 +#define LCD_PLL_EN_HPLL_G12A 28 +#define LCD_PLL_RST_HPLL_G12A 29 +#define LCD_PLL_N_HPLL_G12A 10 +#define LCD_PLL_M_HPLL_G12A 0 + +#define LCD_PLL_OD3_HPLL_G12A 20 +#define LCD_PLL_OD2_HPLL_G12A 18 +#define LCD_PLL_OD1_HPLL_G12A 16 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_HPLL_G12A 0 +#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17) +#define PLL_OD_SEL_MAX_HPLL_G12A 3 +#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000) +#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000) + +/* gp0 & hpll common */ +#define PLL_M_MIN_G12A 2 +#define PLL_M_MAX_G12A 511 +#define PLL_N_MIN_G12A 1 +#define PLL_N_MAX_G12A 1 +#define PLL_FREF_MIN_G12A (5 * 1000) +#define PLL_FREF_MAX_G12A (25 * 1000) + +/* video */ +#define CRT_VID_CLK_IN_MAX_G12A (6000 * 1000) +#define ENCL_CLK_IN_MAX_G12A (200 * 1000) + +/* ********************************** + * TL1 + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x20 */ +#define LCD_PLL_LOCK_TL1 31 +#define LCD_PLL_EN_TL1 28 +#define LCD_PLL_RST_TL1 29 +#define LCD_PLL_N_TL1 10 +#define LCD_PLL_M_TL1 0 + +#define LCD_PLL_OD3_TL1 19 +#define LCD_PLL_OD2_TL1 23 +#define LCD_PLL_OD1_TL1 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TL1 0 +#define PLL_M_MIN_TL1 2 +#define PLL_M_MAX_TL1 511 +#define PLL_N_MIN_TL1 1 +#define PLL_N_MAX_TL1 1 +#define PLL_FRAC_RANGE_TL1 (1 << 17) +#define PLL_OD_SEL_MAX_TL1 3 +#define PLL_FREF_MIN_TL1 (5 * 1000) +#define PLL_FREF_MAX_TL1 (25 * 1000) +#define PLL_VCO_MIN_TL1 (3000 * 1000) +#define PLL_VCO_MAX_TL1 (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TL1 (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TL1 (3100 * 1000) +#define ENCL_CLK_IN_MAX_TL1 (400 * 1000) + + +/* ********************************** + * Spread Spectrum + * ********************************** + */ +#define SS_LEVEL_MAX_GXL 0 +#define SS_LEVEL_MAX_AXG 0 +#define SS_LEVEL_MAX_GP0_G12A 0 +#define SS_LEVEL_MAX_HPLL_G12A 0 + +#define SS_LEVEL_MAX_TXL 5 +static char *lcd_pll_ss_table_txl[] = { + "0, disable", + "1, +/-0.3%", + "2, +/-0.4%", + "3, +/-0.9%", + "4, +/-1.2%", +}; + +#define SS_LEVEL_MAX_TXLX 6 +static char *lcd_pll_ss_table_txlx[] = { + "0, disable", + "1, +/-0.3%", + "2, +/-0.5%", + "3, +/-1.0%", + "4, +/-1.6%", + "5, +/-3.0%", +}; + +#define SS_LEVEL_MAX_TL1 0 + + +static unsigned int pll_ss_reg_txl[][2] = { + /* cntl3 cntl4 */ + { 0, 0}, /* disable */ + {((1 << 14) | (0xc << 10)), 0}, /* 1: +/-0.3% */ + {((1 << 14) | (0x8 << 10)), (0x1 << 2)}, /* 2: +/-0.4% */ + {((1 << 14) | (0xc << 10)), (0x2 << 2)}, /* 3: +/-0.9% */ + {((1 << 14) | (0xc << 10)), (0x3 << 2)}, /* 4: +/-1.2% */ +}; + + +static unsigned int pll_ss_reg_txlx[][3] = { + /* cntl3 cntl4 cntl5 */ + { 0, 0, 0}, /* disable */ + {((1 << 14) | (0x6 << 10)), (0x1 << 2), 0}, /* 1: +/-0.3% */ + {((1 << 14) | (0xa << 10)), (0x1 << 2), 0}, /* 2: +/-0.5% */ + {((1 << 14) | (0xa << 10)), (0x3 << 2), 0}, /* 3: +/-1.0% */ + {((1 << 14) | (0x8 << 10)), (0x3 << 2), (0x1 << 30)}, /* 4: +/-1.6% */ + {((1 << 14) | (0xa << 10)), (0x3 << 2), (0x2 << 30)}, /* 5: +/-3.0% */ +}; + +/* ********************************** + * pll control + * ********************************** + */ +struct lcd_clk_ctrl_s pll_ctrl_table_txl[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_HDMI_PLL_CNTL, LCD_PLL_EN_TXL, 1}, + {LCD_CLK_CTRL_RST, HHI_HDMI_PLL_CNTL, LCD_PLL_RST_TXL, 1}, + {LCD_CLK_CTRL_FRAC, HHI_HDMI_PLL_CNTL2, 0, 12}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_axg[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_GP0_PLL_CNTL_AXG, LCD_PLL_EN_AXG, 1}, + {LCD_CLK_CTRL_RST, HHI_GP0_PLL_CNTL_AXG, LCD_PLL_RST_AXG, 1}, + {LCD_CLK_CTRL_FRAC, HHI_GP0_PLL_CNTL1_AXG, 0, 12}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path0[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_HDMI_PLL_CNTL, LCD_PLL_EN_HPLL_G12A, 1}, + {LCD_CLK_CTRL_RST, HHI_HDMI_PLL_CNTL, LCD_PLL_RST_HPLL_G12A, 1}, + {LCD_CLK_CTRL_FRAC, HHI_HDMI_PLL_CNTL2, 0, 19}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path1[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_EN_GP0_G12A, 1}, + {LCD_CLK_CTRL_RST, HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_RST_GP0_G12A, 1}, + {LCD_CLK_CTRL_FRAC, HHI_GP0_PLL_CNTL1_G12A, 0, 19}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_tl1[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_TCON_PLL_CNTL0, LCD_PLL_EN_TL1, 1}, + {LCD_CLK_CTRL_RST, HHI_TCON_PLL_CNTL0, LCD_PLL_RST_TL1, 1}, + {LCD_CLK_CTRL_FRAC, HHI_TCON_PLL_CNTL1, 0, 17}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +/* ********************************** + * pll & clk parameter + * ********************************** + */ +/* ******** clk calculation ******** */ +#define PLL_WAIT_LOCK_CNT 200 + /* frequency unit: kHz */ +#define FIN_FREQ (24 * 1000) +/* clk max error */ +#define MAX_ERROR (2 * 1000) + +/* ******** register bit ******** */ +/* divider */ +#define CRT_VID_DIV_MAX 255 + +static const unsigned int od_fb_table[2] = {1, 2}; + +static const unsigned int od_table[6] = { + 1, 2, 4, 8, 16, 32 +}; + +static const unsigned int pi_div_table[2] = {2, 4}; + +static char *lcd_clk_div_sel_table[] = { + "1", + "2", + "3", + "3.5", + "3.75", + "4", + "5", + "6", + "6.25", + "7", + "7.5", + "12", + "14", + "15", + "2.5", + "invalid", +}; + +/* g9tv, g9bb, gxbb divider */ +#define CLK_DIV_I2O 0 +#define CLK_DIV_O2I 1 +enum div_sel_e { + CLK_DIV_SEL_1 = 0, + CLK_DIV_SEL_2, /* 1 */ + CLK_DIV_SEL_3, /* 2 */ + CLK_DIV_SEL_3p5, /* 3 */ + CLK_DIV_SEL_3p75, /* 4 */ + CLK_DIV_SEL_4, /* 5 */ + CLK_DIV_SEL_5, /* 6 */ + CLK_DIV_SEL_6, /* 7 */ + CLK_DIV_SEL_6p25, /* 8 */ + CLK_DIV_SEL_7, /* 9 */ + CLK_DIV_SEL_7p5, /* 10 */ + CLK_DIV_SEL_12, /* 11 */ + CLK_DIV_SEL_14, /* 12 */ + CLK_DIV_SEL_15, /* 13 */ + CLK_DIV_SEL_2p5, /* 14 */ + CLK_DIV_SEL_MAX, +}; + +static unsigned int lcd_clk_div_table[][3] = { + /* divider, shift_val, shift_sel */ + {CLK_DIV_SEL_1, 0xffff, 0,}, + {CLK_DIV_SEL_2, 0x0aaa, 0,}, + {CLK_DIV_SEL_3, 0x0db6, 0,}, + {CLK_DIV_SEL_3p5, 0x36cc, 1,}, + {CLK_DIV_SEL_3p75, 0x6666, 2,}, + {CLK_DIV_SEL_4, 0x0ccc, 0,}, + {CLK_DIV_SEL_5, 0x739c, 2,}, + {CLK_DIV_SEL_6, 0x0e38, 0,}, + {CLK_DIV_SEL_6p25, 0x0000, 3,}, + {CLK_DIV_SEL_7, 0x3c78, 1,}, + {CLK_DIV_SEL_7p5, 0x78f0, 2,}, + {CLK_DIV_SEL_12, 0x0fc0, 0,}, + {CLK_DIV_SEL_14, 0x3f80, 1,}, + {CLK_DIV_SEL_15, 0x7f80, 2,}, + {CLK_DIV_SEL_2p5, 0x5294, 2,}, + {CLK_DIV_SEL_MAX, 0xffff, 0,}, +}; + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.c b/drivers/amlogic/media/vout/lcd/lcd_common.c index b8817ea..cbbcac6 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.c +++ b/drivers/amlogic/media/vout/lcd/lcd_common.c @@ -45,11 +45,13 @@ struct lcd_type_match_s { }; static struct lcd_type_match_s lcd_type_match_table[] = { - {"ttl", LCD_TTL}, - {"lvds", LCD_LVDS}, - {"vbyone", LCD_VBYONE}, - {"mipi", LCD_MIPI}, - {"invalid", LCD_TYPE_MAX}, + {"ttl", LCD_TTL}, + {"lvds", LCD_LVDS}, + {"vbyone", LCD_VBYONE}, + {"mipi", LCD_MIPI}, + {"minilvds", LCD_MLVDS}, + {"p2p", LCD_P2P}, + {"invalid", LCD_TYPE_MAX}, }; int lcd_type_str_to_type(const char *str) @@ -361,6 +363,37 @@ void lcd_vbyone_pinmux_set(int status) pconf->pinmux_flag = index; } +void lcd_tcon_pinmux_set(int status) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + pconf = lcd_drv->lcd_config; + if (status) { + if (pconf->pinmux_flag == 0) { + pconf->pinmux_flag = 1; + /* request pinmux */ + pconf->pin = devm_pinctrl_get_select(lcd_drv->dev, + "tcon"); + if (IS_ERR(pconf->pin)) + LCDERR("set tcon pinmux error\n"); + } else { + LCDPR("tcon pinmux is already selected\n"); + } + } else { + if (pconf->pinmux_flag) { + pconf->pinmux_flag = 0; + /* release pinmux */ + devm_pinctrl_put(pconf->pin); + } else { + LCDPR("tcon pinmux is already released\n"); + } + } +} + unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf) { unsigned int channel_on = 0; diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h index 968b949..ce93c41 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.h +++ b/drivers/amlogic/media/vout/lcd/lcd_common.h @@ -31,7 +31,9 @@ /* 20180626: txl suuport */ /* 20180718: mute: wait vsync for display shadow */ /* 20180827: add pinmux off support */ -#define LCD_DRV_VERSION "20180827" +/* 20180928: tl1 support, optimize clk config */ +/* 20181012: tl1 support tcon */ +#define LCD_DRV_VERSION "20181012" #define VPP_OUT_SATURATE (1 << 0) @@ -41,6 +43,10 @@ #define LVDS_PHY_CNTL1_G9TV 0x606cca80 #define LVDS_PHY_CNTL2_G9TV 0x0000006c #define LVDS_PHY_CNTL3_G9TV 0x00000800 + +#define LVDS_PHY_CNTL1_TL1 0x6c60ca80 +#define LVDS_PHY_CNTL2_TL1 0x00000070 +#define LVDS_PHY_CNTL3_TL1 0x03ff0c00 /* -------------------------- */ /* -------------------------- */ @@ -52,6 +58,13 @@ #define VX1_PHY_CNTL3_G9TV 0x00ff0800 /* -------------------------- */ +/* -------------------------- */ +/* minilvds phy parameters define */ +/* -------------------------- */ +#define MLVDS_PHY_CNTL1_TL1 0x6c60ca80 +#define MLVDS_PHY_CNTL2_TL1 0x00000070 +#define MLVDS_PHY_CNTL3_TL1 0x03ff0c00 + /* ******** mipi_dsi_phy ******** */ /* bit[15:11] */ @@ -86,6 +99,7 @@ extern void lcd_cpu_gpio_set(unsigned int index, int value); extern unsigned int lcd_cpu_gpio_get(unsigned int index); extern void lcd_ttl_pinmux_set(int status); extern void lcd_vbyone_pinmux_set(int status); +extern void lcd_tcon_pinmux_set(int status); extern unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf); extern int lcd_power_load_from_dts(struct lcd_config_s *pconf, struct device_node *child); @@ -102,11 +116,27 @@ extern int lcd_vmode_change(struct lcd_config_s *pconf); extern void lcd_venc_change(struct lcd_config_s *pconf); extern void lcd_if_enable_retry(struct lcd_config_s *pconf); +/* lcd tcon */ +extern void lcd_tcon_reg_table_print(void); +extern void lcd_tcon_reg_readback_print(void); +extern int lcd_tcon_info_print(char *buf, int offset); +extern int lcd_tcon_od_set(int flag); +extern int lcd_tcon_od_get(void); +extern int lcd_tcon_reg_table_size_get(void); +extern unsigned char *lcd_tcon_reg_table_get(void); + +extern int lcd_tcon_core_reg_get(unsigned char *buf, unsigned int size); +extern void lcd_tcon_core_reg_update(void); +extern int lcd_tcon_enable(struct lcd_config_s *pconf); +extern void lcd_tcon_disable(void); +extern int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv); + /* lcd debug */ +extern int lcd_debug_info_len(int num); extern void lcd_debug_test(unsigned int num); extern void lcd_mute_setting(unsigned char flag); -extern int lcd_class_creat(void); -extern int lcd_class_remove(void); +extern int lcd_debug_probe(void); +extern int lcd_debug_remove(void); /* lcd driver */ #ifdef CONFIG_AMLOGIC_LCD_TV @@ -119,7 +149,7 @@ extern int lcd_tv_probe(struct device *dev); extern int lcd_tv_remove(struct device *dev); #endif #ifdef CONFIG_AMLOGIC_LCD_TABLET -int lcd_mipi_test_read(struct dsi_read_s *dread); +extern int lcd_mipi_test_read(struct dsi_read_s *dread); extern void lcd_tablet_vout_server_init(void); extern void lcd_tablet_vout_server_remove(void); extern void lcd_tablet_clk_config_change(struct lcd_config_s *pconf); diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c index 4e154aa..83bf97b 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_debug.c +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -33,6 +35,10 @@ #include #include "lcd_tablet/mipi_dsi_util.h" #endif +#include "lcd_debug.h" + +static struct lcd_debug_info_reg_s *lcd_debug_info_reg; +static struct lcd_debug_info_if_s *lcd_debug_info_if; #define PR_BUF_MAX 2048 @@ -246,12 +252,254 @@ static int lcd_power_step_print(struct lcd_config_s *pconf, int status, return len; } +static int lcd_power_info_print(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int len = 0; + + len += lcd_power_step_print(lcd_drv->lcd_config, 1, + (buf+len), (len + offset)); + len += lcd_power_step_print(lcd_drv->lcd_config, 0, + (buf+len), (len + offset)); + len += lcd_cpu_gpio_register_print(lcd_drv->lcd_config, + (buf+len), (len + offset)); + + return len; +} + +static int lcd_info_print_ttl(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "clk_pol %u\n" + "hvsync_valid %u\n" + "de_valid %u\n" + "rb_swap %u\n" + "bit_swap %u\n\n", + pconf->lcd_control.ttl_config->clk_pol, + ((pconf->lcd_control.ttl_config->sync_valid >> 0) & 1), + ((pconf->lcd_control.ttl_config->sync_valid >> 1) & 1), + ((pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1), + ((pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_lvds(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lvds_repack %u\n" + "dual_port %u\n" + "pn_swap %u\n" + "port_swap %u\n" + "lane_reverse %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "phy_clk_vswing 0x%x\n" + "phy_clk_preem 0x%x\n\n", + pconf->lcd_control.lvds_config->lvds_repack, + pconf->lcd_control.lvds_config->dual_port, + pconf->lcd_control.lvds_config->pn_swap, + pconf->lcd_control.lvds_config->port_swap, + pconf->lcd_control.lvds_config->lane_reverse, + pconf->lcd_control.lvds_config->phy_vswing, + pconf->lcd_control.lvds_config->phy_preem, + pconf->lcd_control.lvds_config->phy_clk_vswing, + pconf->lcd_control.lvds_config->phy_clk_preem); + + return len; +} + +static int lcd_info_print_vbyone(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + struct vbyone_config_s *vx1_conf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + vx1_conf = pconf->lcd_control.vbyone_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lane_count %u\n" + "region_num %u\n" + "byte_mode %u\n" + "color_fmt %u\n" + "bit_rate %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "intr_en %u\n" + "vsync_intr_en %u\n" + "ctrl_flag 0x%x\n\n", + vx1_conf->lane_count, + vx1_conf->region_num, + vx1_conf->byte_mode, + vx1_conf->color_fmt, + vx1_conf->bit_rate, + vx1_conf->phy_vswing, + vx1_conf->phy_preem, + vx1_conf->intr_en, + vx1_conf->vsync_intr_en, + vx1_conf->ctrl_flag); + if (vx1_conf->ctrl_flag & 0x1) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "power_on_reset_en %u\n" + "power_on_reset_delay %ums\n\n", + (vx1_conf->ctrl_flag & 0x1), + vx1_conf->power_on_reset_delay); + } + if (vx1_conf->ctrl_flag & 0x2) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "hpd_data_delay_en %u\n" + "hpd_data_delay %ums\n\n", + ((vx1_conf->ctrl_flag >> 1) & 0x1), + vx1_conf->hpd_data_delay); + } + if (vx1_conf->ctrl_flag & 0x4) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "cdr_training_hold_en %u\n" + "cdr_training_hold %ums\n\n", + ((vx1_conf->ctrl_flag >> 2) & 0x1), + vx1_conf->cdr_training_hold); + } + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_mipi(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int len = 0; + +#ifdef CONFIG_AMLOGIC_LCD_TABLET + mipi_dsi_print_info(lcd_drv->lcd_config); +#endif + + return len; +} + +static int lcd_info_print_mlvds(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "channel_num %d\n" + "channel_sel1 0x%08x\n" + "channel_sel1 0x%08x\n" + "clk_phase 0x%04x\n" + "pn_swap %u\n" + "bit_swap %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "bit_rate %dHz\n" + "pi_clk_sel 0x%03x\n\n", + pconf->lcd_control.mlvds_config->channel_num, + pconf->lcd_control.mlvds_config->channel_sel0, + pconf->lcd_control.mlvds_config->channel_sel1, + pconf->lcd_control.mlvds_config->clk_phase, + pconf->lcd_control.mlvds_config->pn_swap, + pconf->lcd_control.mlvds_config->bit_swap, + pconf->lcd_control.mlvds_config->phy_vswing, + pconf->lcd_control.mlvds_config->phy_preem, + pconf->lcd_control.mlvds_config->bit_rate, + pconf->lcd_control.mlvds_config->pi_clk_sel); + + len += lcd_tcon_info_print((buf+len), (len+offset)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_p2p(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "channel_num %d\n" + "channel_sel1 0x%08x\n" + "channel_sel1 0x%08x\n" + "clk_phase 0x%04x\n" + "pn_swap %u\n" + "bit_swap %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "bit_rate %dHz\n" + "pi_clk_sel 0x%03x\n\n", + pconf->lcd_control.p2p_config->channel_num, + pconf->lcd_control.p2p_config->channel_sel0, + pconf->lcd_control.p2p_config->channel_sel1, + pconf->lcd_control.p2p_config->clk_phase, + pconf->lcd_control.p2p_config->pn_swap, + pconf->lcd_control.p2p_config->bit_swap, + pconf->lcd_control.p2p_config->phy_vswing, + pconf->lcd_control.p2p_config->phy_preem, + pconf->lcd_control.p2p_config->bit_rate, + pconf->lcd_control.p2p_config->pi_clk_sel); + + len += lcd_tcon_info_print((buf+len), (len+offset)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + static int lcd_info_print(char *buf, int offset) { unsigned int lcd_clk, sync_duration; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); struct lcd_config_s *pconf; - struct vbyone_config_s *vx1_conf; int n, len = 0; pconf = lcd_drv->lcd_config; @@ -329,211 +577,21 @@ static int lcd_info_print(char *buf, int offset) pconf->lcd_timing.video_on_pixel, pconf->lcd_timing.video_on_line); - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "clk_pol %u\n" - "hvsync_valid %u\n" - "de_valid %u\n" - "rb_swap %u\n" - "bit_swap %u\n\n", - pconf->lcd_control.ttl_config->clk_pol, - ((pconf->lcd_control.ttl_config->sync_valid >> 0) & 1), - ((pconf->lcd_control.ttl_config->sync_valid >> 1) & 1), - ((pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1), - ((pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1)); - - len += snprintf((buf+len), n, - "pinmux_flag %d\n" - "pinmux_pointer 0x%p\n\n", - pconf->pinmux_flag, - pconf->pin); - break; - case LCD_LVDS: - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "lvds_repack %u\n" - "dual_port %u\n" - "pn_swap %u\n" - "port_swap %u\n" - "lane_reverse %u\n" - "phy_vswing 0x%x\n" - "phy_preem 0x%x\n" - "phy_clk_vswing 0x%x\n" - "phy_clk_preem 0x%x\n\n", - pconf->lcd_control.lvds_config->lvds_repack, - pconf->lcd_control.lvds_config->dual_port, - pconf->lcd_control.lvds_config->pn_swap, - pconf->lcd_control.lvds_config->port_swap, - pconf->lcd_control.lvds_config->lane_reverse, - pconf->lcd_control.lvds_config->phy_vswing, - pconf->lcd_control.lvds_config->phy_preem, - pconf->lcd_control.lvds_config->phy_clk_vswing, - pconf->lcd_control.lvds_config->phy_clk_preem); - break; - case LCD_VBYONE: - vx1_conf = pconf->lcd_control.vbyone_config; - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "lane_count %u\n" - "region_num %u\n" - "byte_mode %u\n" - "color_fmt %u\n" - "bit_rate %u\n" - "phy_vswing 0x%x\n" - "phy_preem 0x%x\n" - "intr_en %u\n" - "vsync_intr_en %u\n" - "ctrl_flag 0x%x\n\n", - pconf->lcd_control.vbyone_config->lane_count, - pconf->lcd_control.vbyone_config->region_num, - pconf->lcd_control.vbyone_config->byte_mode, - pconf->lcd_control.vbyone_config->color_fmt, - pconf->lcd_control.vbyone_config->bit_rate, - pconf->lcd_control.vbyone_config->phy_vswing, - pconf->lcd_control.vbyone_config->phy_preem, - pconf->lcd_control.vbyone_config->intr_en, - pconf->lcd_control.vbyone_config->vsync_intr_en, - pconf->lcd_control.vbyone_config->ctrl_flag); - if (vx1_conf->ctrl_flag & 0x1) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "power_on_reset_en %u\n" - "power_on_reset_delay %ums\n\n", - (vx1_conf->ctrl_flag & 0x1), - vx1_conf->power_on_reset_delay); - } - if (vx1_conf->ctrl_flag & 0x2) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hpd_data_delay_en %u\n" - "hpd_data_delay %ums\n\n", - ((vx1_conf->ctrl_flag >> 1) & 0x1), - vx1_conf->hpd_data_delay); - } - if (vx1_conf->ctrl_flag & 0x4) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "cdr_training_hold_en %u\n" - "cdr_training_hold %ums\n\n", - ((vx1_conf->ctrl_flag >> 2) & 0x1), - vx1_conf->cdr_training_hold); + if (lcd_debug_info_if) { + if (lcd_debug_info_if->interface_print) { + len += lcd_debug_info_if->interface_print((buf+len), + (len+offset)); + } else { + LCDERR("%s: interface_print is null\n", __func__); } - - len += snprintf((buf+len), n, - "pinmux_flag %d\n" - "pinmux_pointer 0x%p\n\n", - pconf->pinmux_flag, - pconf->pin); - break; - case LCD_MIPI: -#ifdef CONFIG_AMLOGIC_LCD_TABLET - mipi_dsi_print_info(pconf); -#endif - break; - default: - break; + } else { + LCDERR("%s: lcd_debug_info_if is null\n", __func__); } return len; } -static int lcd_power_info_print(char *buf, int offset) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int len = 0; - - len += lcd_power_step_print(lcd_drv->lcd_config, 1, - (buf+len), (len + offset)); - len += lcd_power_step_print(lcd_drv->lcd_config, 0, - (buf+len), (len + offset)); - len += lcd_cpu_gpio_register_print(lcd_drv->lcd_config, - (buf+len), (len + offset)); - - return len; -} - -static unsigned int lcd_reg_dump_clk[] = { - HHI_HDMI_PLL_CNTL, - HHI_HDMI_PLL_CNTL2, - HHI_HDMI_PLL_CNTL3, - HHI_HDMI_PLL_CNTL4, - HHI_HDMI_PLL_CNTL5, - HHI_HDMI_PLL_CNTL6, - HHI_VID_PLL_CLK_DIV, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, -}; - -static unsigned int lcd_reg_dump_clk_axg[] = { - HHI_GP0_PLL_CNTL_AXG, - HHI_GP0_PLL_CNTL2_AXG, - HHI_GP0_PLL_CNTL3_AXG, - HHI_GP0_PLL_CNTL4_AXG, - HHI_GP0_PLL_CNTL5_AXG, - HHI_GP0_PLL_CNTL1_AXG, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, -}; - -static unsigned int lcd_reg_dump_clk_gp0_g12a[] = { - HHI_GP0_PLL_CNTL0_G12A, - HHI_GP0_PLL_CNTL1_G12A, - HHI_GP0_PLL_CNTL2_G12A, - HHI_GP0_PLL_CNTL3_G12A, - HHI_GP0_PLL_CNTL4_G12A, - HHI_GP0_PLL_CNTL5_G12A, - HHI_GP0_PLL_CNTL6_G12A, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, - HHI_MIPIDSI_PHY_CLK_CNTL, -}; - -static unsigned int lcd_reg_dump_clk_hpll_g12a[] = { - HHI_HDMI_PLL_CNTL, - HHI_HDMI_PLL_CNTL2, - HHI_HDMI_PLL_CNTL3, - HHI_HDMI_PLL_CNTL4, - HHI_HDMI_PLL_CNTL5, - HHI_HDMI_PLL_CNTL6, - HHI_HDMI_PLL_CNTL7, - HHI_VID_PLL_CLK_DIV, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, - HHI_MIPIDSI_PHY_CLK_CNTL, -}; - -static unsigned int lcd_reg_dump_encl[] = { - VPU_VIU_VENC_MUX_CTRL, - ENCL_VIDEO_EN, - ENCL_VIDEO_MODE, - ENCL_VIDEO_MODE_ADV, - ENCL_VIDEO_MAX_PXCNT, - ENCL_VIDEO_MAX_LNCNT, - ENCL_VIDEO_HAVON_BEGIN, - ENCL_VIDEO_HAVON_END, - ENCL_VIDEO_VAVON_BLINE, - ENCL_VIDEO_VAVON_ELINE, - ENCL_VIDEO_HSO_BEGIN, - ENCL_VIDEO_HSO_END, - ENCL_VIDEO_VSO_BEGIN, - ENCL_VIDEO_VSO_END, - ENCL_VIDEO_VSO_BLINE, - ENCL_VIDEO_VSO_ELINE, - ENCL_VIDEO_RGBIN_CTRL, - L_GAMMA_CNTL_PORT, - L_RGB_BASE_ADDR, - L_RGB_COEFF_ADDR, - L_POL_CNTL_ADDR, - L_DITH_CNTL_ADDR, -}; - -static int lcd_ttl_reg_print(char *buf, int offset) +static int lcd_reg_print_ttl(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -609,7 +667,7 @@ static int lcd_ttl_reg_print(char *buf, int offset) return len; } -static int lcd_lvds_reg_print(char *buf, int offset) +static int lcd_reg_print_lvds(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -645,53 +703,30 @@ static int lcd_lvds_reg_print(char *buf, int offset) return len; } -static int lcd_vbyone_reg_print(char *buf, int offset) +static int lcd_reg_print_vbyone(char *buf, int offset) { unsigned int reg; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int n, len = 0; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, "\nvbyone regs:\n"); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - n = lcd_debug_info_len(len + offset); - reg = PERIPHS_PIN_MUX_7; - len += snprintf((buf+len), n, - "VX1_PINMUX [0x%04x] = 0x%08x\n", - reg, lcd_periphs_read(reg)); - break; - case LCD_CHIP_TXLX: - n = lcd_debug_info_len(len + offset); - reg = PERIPHS_PIN_MUX_0; - len += snprintf((buf+len), n, - "VX1_PINMUX [0x%04x] = 0x%08x\n", - reg, lcd_periphs_read(reg)); - break; - default: - break; - } n = lcd_debug_info_len(len + offset); reg = VBO_STATUS_L; len += snprintf((buf+len), n, "VX1_STATUS [0x%04x] = 0x%08x\n", reg, lcd_vcbus_read(reg)); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TXLX: - n = lcd_debug_info_len(len + offset); - reg = VBO_INFILTER_CTRL; - len += snprintf((buf+len), n, - "VBO_INFILTER_CTRL [0x%04x] = 0x%08x\n", - reg, lcd_vcbus_read(reg)); - n = lcd_debug_info_len(len + offset); - reg = VBO_INSGN_CTRL; - len += snprintf((buf+len), n, - "VBO_INSGN_CTRL [0x%04x] = 0x%08x\n", - reg, lcd_vcbus_read(reg)); - break; - default: - break; - } + + n = lcd_debug_info_len(len + offset); + reg = VBO_INFILTER_CTRL; + len += snprintf((buf+len), n, + "VBO_INFILTER_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_vcbus_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = VBO_INSGN_CTRL; + len += snprintf((buf+len), n, + "VBO_INSGN_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_vcbus_read(reg)); + n = lcd_debug_info_len(len + offset); reg = VBO_FSM_HOLDER_L; len += snprintf((buf+len), n, @@ -726,7 +761,7 @@ static int lcd_vbyone_reg_print(char *buf, int offset) return len; } -static int lcd_mipi_reg_print(char *buf, int offset) +static int lcd_reg_print_mipi(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -807,7 +842,229 @@ static int lcd_mipi_reg_print(char *buf, int offset) return len; } -static int lcd_phy_analog_reg_print(char *buf, int offset) +static int lcd_reg_print_mlvds(char *buf, int offset) +{ + unsigned int reg; + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nmlvds regs:\n"); + + n = lcd_debug_info_len(len + offset); + reg = HHI_TCON_CLK_CNTL; + len += snprintf((buf+len), n, + "HHI_TCON_CLK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL0; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL0 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL1; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL1 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL2; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL2 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + + n = lcd_debug_info_len(len + offset); + reg = TCON_TOP_CTRL; + len += snprintf((buf+len), n, + "TCON_TOP_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RGB_IN_MUX; + len += snprintf((buf+len), n, + "TCON_RGB_IN_MUX [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL0; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL1; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS0; + len += snprintf((buf+len), n, + "TCON_STATUS0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_PLLLOCK_CNTL; + len += snprintf((buf+len), n, + "TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RST_CTRL; + len += snprintf((buf+len), n, + "TCON_RST_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST0; + len += snprintf((buf+len), n, + "TCON_AXI_OFST0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST1; + len += snprintf((buf+len), n, + "TCON_AXI_OFST1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST2; + len += snprintf((buf+len), n, + "TCON_AXI_OFST2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_CLK_CTRL; + len += snprintf((buf+len), n, + "TCON_CLK_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS1; + len += snprintf((buf+len), n, + "TCON_STATUS1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_DDRIF_CTRL1; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_DDRIF_CTRL2; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_INTR_MASKN; + len += snprintf((buf+len), n, + "TCON_INTR_MASKN [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_INTR; + len += snprintf((buf+len), n, + "TCON_INTR [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + + return len; +} + +static int lcd_reg_print_p2p(char *buf, int offset) +{ + unsigned int reg; + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nmlvds regs:\n"); + + n = lcd_debug_info_len(len + offset); + reg = HHI_TCON_CLK_CNTL; + len += snprintf((buf+len), n, + "HHI_TCON_CLK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL0; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL0 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL1; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL1 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL2; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL2 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + + n = lcd_debug_info_len(len + offset); + reg = TCON_TOP_CTRL; + len += snprintf((buf+len), n, + "TCON_TOP_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RGB_IN_MUX; + len += snprintf((buf+len), n, + "TCON_RGB_IN_MUX [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL0; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL1; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS0; + len += snprintf((buf+len), n, + "TCON_STATUS0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_PLLLOCK_CNTL; + len += snprintf((buf+len), n, + "TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RST_CTRL; + len += snprintf((buf+len), n, + "TCON_RST_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST0; + len += snprintf((buf+len), n, + "TCON_AXI_OFST0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST1; + len += snprintf((buf+len), n, + "TCON_AXI_OFST1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST2; + len += snprintf((buf+len), n, + "TCON_AXI_OFST2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_CLK_CTRL; + len += snprintf((buf+len), n, + "TCON_CLK_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS1; + len += snprintf((buf+len), n, + "TCON_STATUS1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_DDRIF_CTRL1; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_DDRIF_CTRL2; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_INTR_MASKN; + len += snprintf((buf+len), n, + "TCON_INTR_MASKN [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_INTR; + len += snprintf((buf+len), n, + "TCON_INTR [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + + return len; +} + +static int lcd_reg_print_phy_analog(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -833,7 +1090,7 @@ static int lcd_phy_analog_reg_print(char *buf, int offset) return len; } -static int lcd_mipi_phy_analog_reg_print(char *buf, int offset) +static int lcd_reg_print_mipi_phy_analog(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -864,84 +1121,79 @@ static int lcd_reg_print(char *buf, int offset) struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int i, n, len = 0; struct lcd_config_s *pconf; + unsigned int *table; pconf = lcd_drv->lcd_config; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, "\nclk regs:\n"); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_axg); i++) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_axg[i], - lcd_hiu_read(lcd_reg_dump_clk_axg[i])); - } - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_gp0_g12a); - i++) { + if (lcd_debug_info_reg) { + if (lcd_debug_info_reg->reg_clk_table) { + table = lcd_debug_info_reg->reg_clk_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_gp0_g12a[i], - lcd_hiu_read( - lcd_reg_dump_clk_gp0_g12a[i])); + "hiu [0x%08x] = 0x%08x\n", + table[i], lcd_hiu_read(table[i])); + i++; } } else { - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_hpll_g12a); - i++) { + LCDERR("%s: reg_clk_table is null\n", __func__); + } + + if (lcd_debug_info_reg->reg_encl_table) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nencl regs:\n"); + table = lcd_debug_info_reg->reg_encl_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_hpll_g12a[i], - lcd_hiu_read( - lcd_reg_dump_clk_hpll_g12a[i])); + "vcbus [0x%04x] = 0x%08x\n", + table[i], lcd_vcbus_read(table[i])); + i++; } + } else { + LCDERR("%s: reg_encl_table is null\n", __func__); } - break; - default: - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk); i++) { + + if (lcd_debug_info_reg->reg_pinmux_table) { n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk[i], - lcd_hiu_read(lcd_reg_dump_clk[i])); + len += snprintf((buf+len), n, "\npinmux regs:\n"); + table = lcd_debug_info_reg->reg_pinmux_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; + len += snprintf((buf+len), n, + "PERIPHS_PIN_MUX [0x%08x] = 0x%08x\n", + table[i], lcd_periphs_read(table[i])); + i++; + } } - break; + } else { + LCDERR("%s: lcd_debug_info_reg is null\n", __func__); } - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, "\nencl regs:\n"); - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_encl); i++) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "vcbus [0x%04x] = 0x%08x\n", - lcd_reg_dump_encl[i], - lcd_vcbus_read(lcd_reg_dump_encl[i])); - } + if (lcd_debug_info_if) { + if (lcd_debug_info_if->reg_dump_interface) { + len += lcd_debug_info_if->reg_dump_interface((buf+len), + (len+offset)); + } else { + LCDERR("%s: reg_dump_interface is null\n", __func__); + } - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - len += lcd_ttl_reg_print((buf+len), (len + offset)); - break; - case LCD_LVDS: - len += lcd_lvds_reg_print((buf+len), (len + offset)); - len += lcd_phy_analog_reg_print((buf+len), (len + offset)); - break; - case LCD_VBYONE: - len += lcd_vbyone_reg_print((buf+len), (len + offset)); - len += lcd_phy_analog_reg_print((buf+len), (len + offset)); - break; - case LCD_MIPI: - len += lcd_mipi_reg_print((buf+len), (len + offset)); - len += lcd_mipi_phy_analog_reg_print((buf+len), (len + offset)); - break; - default: - break; + if (lcd_debug_info_if->reg_dump_phy) { + len += lcd_debug_info_if->reg_dump_phy((buf+len), + (len+offset)); + } + } else { + LCDERR("%s: lcd_debug_info_if is null\n", __func__); } return len; @@ -1464,6 +1716,8 @@ static ssize_t lcd_debug_change_store(struct class *class, struct lvds_config_s *lvds_conf; struct vbyone_config_s *vx1_conf; struct dsi_config_s *dsi_conf; + struct mlvds_config_s *mlvds_conf; + struct p2p_config_s *p2p_conf; pconf = lcd_drv->lcd_config; switch (buf[0]) { @@ -1635,32 +1889,95 @@ static ssize_t lcd_debug_change_store(struct class *class, } break; case 'm': - dsi_conf = pconf->lcd_control.mipi_config; - ret = sscanf(buf, "mipi %d %d %d %d %d %d %d %d", - &val[0], &val[1], &val[2], &val[3], - &val[4], &val[5], &val[6], &val[7]); - if (ret == 8) { - dsi_conf->lane_num = (unsigned char)val[0]; - dsi_conf->bit_rate_max = val[1]; - dsi_conf->factor_numerator = val[2]; - dsi_conf->operation_mode_init = (unsigned char)val[3]; - dsi_conf->operation_mode_display = - (unsigned char)val[4]; - dsi_conf->video_mode_type = (unsigned char)val[5]; - dsi_conf->clk_always_hs = (unsigned char)val[6]; - dsi_conf->phy_switch = (unsigned char)val[7]; - pr_info("change mipi_dsi config:\n" + if (buf[1] == 'i') { + dsi_conf = pconf->lcd_control.mipi_config; + ret = sscanf(buf, "mipi %d %d %d %d %d %d %d %d", + &val[0], &val[1], &val[2], &val[3], + &val[4], &val[5], &val[6], &val[7]); + if (ret == 8) { + dsi_conf->lane_num = (unsigned char)val[0]; + dsi_conf->bit_rate_max = val[1]; + dsi_conf->factor_numerator = val[2]; + dsi_conf->operation_mode_init = + (unsigned char)val[3]; + dsi_conf->operation_mode_display = + (unsigned char)val[4]; + dsi_conf->video_mode_type = + (unsigned char)val[5]; + dsi_conf->clk_always_hs = (unsigned char)val[6]; + dsi_conf->phy_switch = (unsigned char)val[7]; + pr_info("change mipi_dsi config:\n" "lane_num=%d, bit_rate_max=%dMhz, factor_numerator=%d\n" "operation_mode_init=%d, operation_mode_display=%d\n" "video_mode_type=%d, clk_always_hs=%d, phy_switch=%d\n", - dsi_conf->lane_num, - dsi_conf->bit_rate_max, - dsi_conf->factor_numerator, - dsi_conf->operation_mode_init, - dsi_conf->operation_mode_display, - dsi_conf->video_mode_type, - dsi_conf->clk_always_hs, - dsi_conf->phy_switch); + dsi_conf->lane_num, + dsi_conf->bit_rate_max, + dsi_conf->factor_numerator, + dsi_conf->operation_mode_init, + dsi_conf->operation_mode_display, + dsi_conf->video_mode_type, + dsi_conf->clk_always_hs, + dsi_conf->phy_switch); + lcd_debug_change_clk_change( + pconf->lcd_timing.lcd_clk); + pconf->change_flag = 1; + } else { + LCDERR("invalid data\n"); + return -EINVAL; + } + } else if (buf[1] == 'l') { + mlvds_conf = pconf->lcd_control.mlvds_config; + ret = sscanf(buf, "mlvds %d %x %x %x %d %d", + &val[0], &val[1], &val[2], &val[3], + &val[4], &val[5]); + if (ret == 6) { + mlvds_conf->channel_num = val[0]; + mlvds_conf->channel_sel0 = val[1]; + mlvds_conf->channel_sel1 = val[2]; + mlvds_conf->clk_phase = val[3]; + mlvds_conf->pn_swap = val[4]; + mlvds_conf->bit_swap = val[5]; + pr_info("change mlvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + mlvds_conf->channel_num, + mlvds_conf->channel_sel0, + mlvds_conf->channel_sel1, + mlvds_conf->clk_phase, + mlvds_conf->pn_swap, + mlvds_conf->bit_swap); + lcd_debug_change_clk_change( + pconf->lcd_timing.lcd_clk); + pconf->change_flag = 1; + } else { + LCDERR("invalid data\n"); + return -EINVAL; + } + } + break; + case 'p': + p2p_conf = pconf->lcd_control.p2p_config; + ret = sscanf(buf, "p2p %d %x %x %x %d %d", + &val[0], &val[1], &val[2], &val[3], &val[4], &val[5]); + if (ret == 6) { + p2p_conf->channel_num = val[0]; + p2p_conf->channel_sel0 = val[1]; + p2p_conf->channel_sel1 = val[2]; + p2p_conf->clk_phase = val[3]; + p2p_conf->pn_swap = val[4]; + p2p_conf->bit_swap = val[5]; + pr_info("change mlvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + p2p_conf->channel_num, + p2p_conf->channel_sel0, + p2p_conf->channel_sel1, + p2p_conf->clk_phase, + p2p_conf->pn_swap, p2p_conf->bit_swap); lcd_debug_change_clk_change(pconf->lcd_timing.lcd_clk); pconf->change_flag = 1; } else { @@ -1912,7 +2229,7 @@ static ssize_t lcd_debug_ss_store(struct class *class, return -EINVAL; } lcd_drv->lcd_config->lcd_timing.ss_level = temp; - lcd_set_spread_spectrum(); + lcd_set_spread_spectrum(temp); return count; } @@ -1950,6 +2267,7 @@ static ssize_t lcd_debug_clk_store(struct class *class, if (ret) { pr_info("change clk_path error\n"); } else { + lcd_drv->lcd_clk_path = temp; lcd_clk_generate_parameter(lcd_drv->lcd_config); pr_info("change clk_path: %d\n", temp); } @@ -2580,17 +2898,6 @@ static const char *lcd_mipi_debug_usage_str = { "\n" }; -static const char *lcd_edp_debug_usage_str = { -"Usage:\n" -" echo > edp ; set edp config\n" -"data format:\n" -" : 0=1.62G, 1=2.7G\n" -" : 1/2/4\n" -" : 0=no use, 1=use, default=0\n" -" : 0=asyncronous, 1=synchronous, default=1\n" -"\n" -}; - static const char *lcd_mipi_cmd_debug_usage_str = { "Usage:\n" " echo ...... > mpcmd ; send mipi cmd\n" @@ -2607,6 +2914,50 @@ static const char *lcd_mipi_cmd_debug_usage_str = { "\n" }; +static const char *lcd_mlvds_debug_usage_str = { +"Usage:\n" +" echo > minilvds ; set minilvds config\n" +"data format:\n" +" : minilvds 8 channels mapping in tx 10 channels\n" +" : bit[13:12]=clk01_pi_sel, bit[11:8]=pi2, bit[7:4]=pi1, bit[3:0]=pi0\n" +" : 0=normal, 1=swap p/n channels\n" +" : 0=normal, 1=swap bit LSB/MSB\n" +"\n" +}; + +static const char *lcd_p2p_debug_usage_str = { +"Usage:\n" +" echo > minilvds ; set minilvds config\n" +"data format:\n" +" : minilvds 8 channels mapping in tx 10 channels\n" +" : bit[13:12]=clk01_pi_sel, bit[11:8]=pi2, bit[7:4]=pi1, bit[3:0]=pi0\n" +" : 0=normal, 1=swap p/n channels\n" +" : 0=normal, 1=swap bit LSB/MSB\n" +"\n" +}; + +static const char *lcd_debug_tcon_usage_str = { + "Usage:\n" + " echo reg > tcon ; print tcon system regs\n" + " echo reg save > tcon ; save tcon system regs to bin file\n" + "\n" + " echo table > tcon ; print tcon reg table\n" + " echo table r > tcon ; read tcon reg table by specified index\n" + " echo table w > tcon ; write tcon reg table by specified index\n" + " echo table d > tcon ; dump tcon reg table\n" + "data format:\n" + " : hex number\n" + " : hex number\n" + " : dec number\n" + "\n" + " echo table update > tcon ; update tcon reg table into tcon system regs\n" + " echo table save > tcon ; save tcon reg table to bin file\n" + "\n" + " echo od > tcon ; tcon over driver control\n" + "data format:\n" + " : 0=disable, 1=enable\n" +}; + static ssize_t lcd_ttl_debug_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -2631,10 +2982,22 @@ static ssize_t lcd_mipi_debug_show(struct class *class, return sprintf(buf, "%s\n", lcd_mipi_debug_usage_str); } -static ssize_t lcd_edp_debug_show(struct class *class, +static ssize_t lcd_mlvds_debug_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", lcd_mlvds_debug_usage_str); +} + +static ssize_t lcd_p2p_debug_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", lcd_p2p_debug_usage_str); +} + +static ssize_t lcd_tcon_debug_show(struct class *class, struct class_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", lcd_edp_debug_usage_str); + return sprintf(buf, "%s\n", lcd_debug_tcon_usage_str); } static ssize_t lcd_ttl_debug_store(struct class *class, @@ -2832,10 +3195,66 @@ static ssize_t lcd_mipi_debug_store(struct class *class, return count; } -static ssize_t lcd_edp_debug_store(struct class *class, +static ssize_t lcd_mlvds_debug_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct mlvds_config_s *mlvds_conf; + + mlvds_conf = lcd_drv->lcd_config->lcd_control.mlvds_config; + ret = sscanf(buf, "%d %x %x %x %d %d", + &mlvds_conf->channel_num, + &mlvds_conf->channel_sel0, &mlvds_conf->channel_sel1, + &mlvds_conf->clk_phase, + &mlvds_conf->pn_swap, &mlvds_conf->bit_swap); + if (ret == 6) { + pr_info("set minilvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + mlvds_conf->channel_num, + mlvds_conf->channel_sel0, mlvds_conf->channel_sel1, + mlvds_conf->clk_phase, + mlvds_conf->pn_swap, mlvds_conf->bit_swap); + lcd_debug_config_update(); + } else { + pr_info("invalid data\n"); + return -EINVAL; + } + + return count; +} + +static ssize_t lcd_p2p_debug_store(struct class *class, struct class_attribute *attr, const char *buf, size_t count) { - pr_info("to do\n"); + int ret = 0; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct p2p_config_s *p2p_conf; + + p2p_conf = lcd_drv->lcd_config->lcd_control.p2p_config; + ret = sscanf(buf, "%d %x %x %x %d %d", + &p2p_conf->channel_num, + &p2p_conf->channel_sel0, &p2p_conf->channel_sel1, + &p2p_conf->clk_phase, + &p2p_conf->pn_swap, &p2p_conf->bit_swap); + if (ret == 6) { + pr_info("set minilvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + p2p_conf->channel_num, + p2p_conf->channel_sel0, p2p_conf->channel_sel1, + p2p_conf->clk_phase, + p2p_conf->pn_swap, p2p_conf->bit_swap); + lcd_debug_config_update(); + } else { + pr_info("invalid data\n"); + return -EINVAL; + } return count; } @@ -2944,6 +3363,82 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) __func__, cnt); } break; + case LCD_MLVDS: + if (cnt >= 2) { + if ((para[0] > 7) || (para[1] > 3)) { + LCDERR("%s: wrong value:\n", __func__); + pr_info("vswing=%d, preemphasis=%d\n", + para[0], para[1]); + return; + } + + pconf->lcd_control.mlvds_config->phy_vswing = para[0]; + pconf->lcd_control.mlvds_config->phy_preem = para[1]; + + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); + data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); + data32 |= ((para[0] << 3) | (para[0] << 0) | + (para[1] << 23)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); + data32 &= ~((0x3 << 14) | (0x3 << 12) | + (0x3 << 26) | (0x3 << 24)); + data32 |= ((para[1] << 14) | (para[1] << 12) | + (para[1] << 26) | (para[1] << 24)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); + data32 &= ~((0x3 << 6) | (0x3 << 4) | + (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); + data32 |= ((para[1] << 6) | (para[1] << 4) | + (para[1] << 2) | (para[1] << 0) | + (para[1] << 30)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + + LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", + __func__, para[0], para[1]); + } else { + LCDERR("%s: invalid parameters cnt: %d\n", + __func__, cnt); + } + break; + case LCD_P2P: + if (cnt >= 2) { + if ((para[0] > 7) || (para[1] > 3)) { + LCDERR("%s: wrong value:\n", __func__); + pr_info("vswing=%d, preemphasis=%d\n", + para[0], para[1]); + return; + } + + pconf->lcd_control.p2p_config->phy_vswing = para[0]; + pconf->lcd_control.p2p_config->phy_preem = para[1]; + + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); + data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); + data32 |= ((para[0] << 3) | (para[0] << 0) | + (para[1] << 23)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); + data32 &= ~((0x3 << 14) | (0x3 << 12) | + (0x3 << 26) | (0x3 << 24)); + data32 |= ((para[1] << 14) | (para[1] << 12) | + (para[1] << 26) | (para[1] << 24)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); + data32 &= ~((0x3 << 6) | (0x3 << 4) | + (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); + data32 |= ((para[1] << 6) | (para[1] << 4) | + (para[1] << 2) | (para[1] << 0) | + (para[1] << 30)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + + LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", + __func__, para[0], para[1]); + } else { + LCDERR("%s: invalid parameters cnt: %d\n", + __func__, cnt); + } + break; default: LCDERR("%s: not support lcd_type: %s\n", __func__, lcd_type_type_to_str(type)); @@ -2981,6 +3476,20 @@ static ssize_t lcd_phy_debug_show(struct class *class, len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", vswing, preem); break; + case LCD_MLVDS: + vswing = pconf->lcd_control.mlvds_config->phy_vswing; + preem = pconf->lcd_control.mlvds_config->phy_preem; + len += sprintf(buf+len, "%s:\n", __func__); + len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", + vswing, preem); + break; + case LCD_P2P: + vswing = pconf->lcd_control.p2p_config->phy_vswing; + preem = pconf->lcd_control.p2p_config->phy_preem; + len += sprintf(buf+len, "%s:\n", __func__); + len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", + vswing, preem); + break; default: len = sprintf(buf, "%s: invalid lcd_type: %d\n", __func__, pconf->lcd_basic.lcd_type); @@ -3010,6 +3519,224 @@ static ssize_t lcd_phy_debug_store(struct class *class, return count; } +static void lcd_tcon_reg_table_save(char *path, unsigned char *reg_table, + unsigned int size) +{ + struct file *filp = NULL; + loff_t pos = 0; + void *buf = NULL; + mm_segment_t old_fs = get_fs(); + + set_fs(KERNEL_DS); + filp = filp_open(path, O_RDWR|O_CREAT, 0666); + + if (IS_ERR(filp)) { + LCDERR("%s: create %s error\n", __func__, path); + set_fs(old_fs); + return; + } + + pos = 0; + buf = (void *)reg_table; + vfs_write(filp, buf, size, &pos); + + vfs_fsync(filp, 0); + filp_close(filp, NULL); + set_fs(old_fs); + + LCDPR("save tcon reg table to %s finished\n", path); +} + +static void lcd_tcon_reg_save(char *path, unsigned int size) +{ + struct file *filp = NULL; + loff_t pos = 0; + unsigned char *temp; + void *buf = NULL; + mm_segment_t old_fs = get_fs(); + int ret; + + set_fs(KERNEL_DS); + filp = filp_open(path, O_RDWR|O_CREAT, 0666); + + if (IS_ERR(filp)) { + LCDERR("%s: create %s error\n", __func__, path); + set_fs(old_fs); + return; + } + + temp = kcalloc(size, sizeof(unsigned char), GFP_KERNEL); + if (!temp) { + LCDERR("%s: Not enough memory\n", __func__); + filp_close(filp, NULL); + set_fs(old_fs); + return; + } + ret = lcd_tcon_core_reg_get(temp, size); + if (ret) { + LCDPR("save tcon reg failed\n"); + filp_close(filp, NULL); + set_fs(old_fs); + kfree(temp); + return; + } + + pos = 0; + buf = (void *)temp; + vfs_write(filp, buf, size, &pos); + + vfs_fsync(filp, 0); + filp_close(filp, NULL); + set_fs(old_fs); + kfree(temp); + + LCDPR("save tcon reg to %s success\n", path); +} + +static ssize_t lcd_tcon_debug_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + char *buf_orig; + char *parm[47] = {NULL}; + unsigned int temp = 0, val, i, n, size; + unsigned char data; + unsigned char *table; + int ret = -1; + + size = lcd_tcon_reg_table_size_get(); + if (size <= 0) + return count; + table = lcd_tcon_reg_table_get(); + if (table == NULL) + return count; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + if (buf_orig == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return count; + } + lcd_debug_parse_param(buf_orig, (char **)&parm); + + if (strcmp(parm[0], "reg") == 0) { + if (parm[1] == NULL) { + lcd_tcon_reg_readback_print(); + goto lcd_tcon_debug_store_end; + } + if (strcmp(parm[1], "save") == 0) { + if (parm[2] != NULL) + lcd_tcon_reg_save(parm[2], size); + else + pr_info("invalid save path\n"); + } + } else if (strcmp(parm[0], "table") == 0) { + if (parm[1] == NULL) { + lcd_tcon_reg_table_print(); + goto lcd_tcon_debug_store_end; + } + if (strcmp(parm[1], "r") == 0) { + if (parm[2] != NULL) { + ret = kstrtouint(parm[2], 16, &temp); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + if (temp < size) { + data = table[temp]; + pr_info("read tcon table[%d]=0x%02x\n", + temp, data); + } else { + pr_info("invalid table index: %d\n", + temp); + } + } + } else if (strcmp(parm[1], "w") == 0) { + if (parm[3] != NULL) { + ret = kstrtouint(parm[2], 16, &temp); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + ret = kstrtouint(parm[3], 16, &val); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + data = (unsigned char)val; + if (temp < size) { + table[temp] = data; + pr_info("write tcon table[%d]=0x%02x\n", + temp, data); + } else { + pr_info("invalid table index: %d\n", + temp); + } + } + } else if (strcmp(parm[1], "d") == 0) { + if (parm[3] != NULL) { + ret = 0; + if (!kstrtouint(parm[2], 16, &val)) + temp = (unsigned int)val; + else + ret = 1; + if (!kstrtouint(parm[3], 16, &val)) + n = (unsigned char)val; + else + ret = 1; + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + pr_info("dump tcon table:\n"); + for (i = temp; i < (temp + n); i++) { + if (i > size) + break; + data = table[i]; + pr_info(" [%d]=0x%02x\n", temp, data); + } + } + } else if (strcmp(parm[1], "update") == 0) { + lcd_tcon_core_reg_update(); + } else if (strcmp(parm[1], "save") == 0) { + if (parm[2] != NULL) + lcd_tcon_reg_table_save(parm[2], table, size); + else + pr_info("invalid save path\n"); + } + } else if (strcmp(parm[0], "od") == 0) { /* over drive */ + if (parm[1] != NULL) { + if (strcmp(parm[1], "status") == 0) { + temp = lcd_tcon_od_get(); + if (temp) { + LCDPR("tcon od is enabled: %d\n", temp); + } else { + LCDPR("tcon od is disabled: %d\n", + temp); + } + } else { + if (!kstrtouint(parm[1], 10, &temp)) { + if (temp) + lcd_tcon_od_set(1); + else + lcd_tcon_od_set(0); + } + } + } + } else { + LCDERR("wrong command\n"); + goto lcd_tcon_debug_store_err; + } + +lcd_tcon_debug_store_end: + kfree(buf_orig); + return count; + +lcd_tcon_debug_store_err: + kfree(buf_orig); + return count; +} + static ssize_t lcd_mipi_cmd_debug_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -3223,25 +3950,51 @@ static ssize_t lcd_mipi_mode_debug_store(struct class *class, return count; } -static struct class_attribute lcd_interface_debug_class_attrs[] = { +static struct class_attribute lcd_debug_class_attrs_ttl[] = { __ATTR(ttl, 0644, lcd_ttl_debug_show, lcd_ttl_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_lvds[] = { __ATTR(lvds, 0644, lcd_lvds_debug_show, lcd_lvds_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_vbyone[] = { __ATTR(vbyone, 0644, lcd_vx1_debug_show, lcd_vx1_debug_store), - __ATTR(mipi, 0644, - lcd_mipi_debug_show, lcd_mipi_debug_store), - __ATTR(edp, 0644, - lcd_edp_debug_show, lcd_edp_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_mlvds[] = { + __ATTR(mlvds, 0644, + lcd_mlvds_debug_show, lcd_mlvds_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(tcon, 0644, + lcd_tcon_debug_show, lcd_tcon_debug_store), + __ATTR(null, 0644, NULL, NULL), }; -static struct class_attribute lcd_phy_debug_class_attrs[] = { +static struct class_attribute lcd_debug_class_attrs_p2p[] = { + __ATTR(p2p, 0644, + lcd_p2p_debug_show, lcd_p2p_debug_store), __ATTR(phy, 0644, lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(tcon, 0644, + lcd_tcon_debug_show, lcd_tcon_debug_store), + __ATTR(null, 0644, NULL, NULL), }; -static struct class_attribute lcd_mipi_debug_class_attrs[] = { +static struct class_attribute lcd_debug_class_attrs_mipi[] = { + __ATTR(mipi, 0644, + lcd_mipi_debug_show, lcd_mipi_debug_store), __ATTR(mpcmd, 0644, lcd_mipi_cmd_debug_show, lcd_mipi_cmd_debug_store), __ATTR(mpread, 0644, @@ -3249,13 +4002,16 @@ static struct class_attribute lcd_mipi_debug_class_attrs[] = { __ATTR(mpstate, 0644, lcd_mipi_state_debug_show, NULL), __ATTR(mpmode, 0644, lcd_mipi_mode_debug_show, lcd_mipi_mode_debug_store), + __ATTR(null, 0644, NULL, NULL), }; -int lcd_class_creat(void) +#define LCD_DEBUG_CLASS_ATTRS_IF_MAX 10 +static int lcd_class_creat(void) { - int i; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int type; + struct class *lcd_class; + struct class_attribute *lcd_attr; + int i; lcd_drv->lcd_screen_restore = lcd_screen_restore; lcd_drv->lcd_screen_black = lcd_screen_black; @@ -3267,81 +4023,227 @@ int lcd_class_creat(void) LCDERR("create lcd debug class fail\n"); return -1; } + lcd_class = lcd_drv->lcd_debug_class; for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_debug_class_attrs[i])) { + if (class_create_file(lcd_class, &lcd_debug_class_attrs[i])) { LCDERR("create lcd debug attribute %s fail\n", lcd_debug_class_attrs[i].attr.name); } } - type = lcd_drv->lcd_config->lcd_basic.lcd_type; - for (i = 0; i < ARRAY_SIZE(lcd_interface_debug_class_attrs); i++) { - if (strcmp(lcd_interface_debug_class_attrs[i].attr.name, - lcd_type_type_to_str(type))) - continue; - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_interface_debug_class_attrs[i])) { - LCDERR("create lcd_interface debug attribute %s fail\n", - lcd_interface_debug_class_attrs[i].attr.name); + if (lcd_debug_info_if) { + if (lcd_debug_info_if->class_attrs) { + lcd_attr = lcd_debug_info_if->class_attrs; + while (lcd_attr) { + if (strcmp(lcd_attr->attr.name, "null") == 0) + break; + if (class_create_file(lcd_class, lcd_attr)) { + LCDERR( + "create lcd_interface debug attribute %s fail\n", + lcd_attr->attr.name); + } + lcd_attr++; + } + } else { + LCDERR("lcd_debug_info_if class_attrs is null\n"); } + } else { + LCDERR("lcd_debug_info_if is null\n"); } - switch (type) { - case LCD_LVDS: - case LCD_VBYONE: - for (i = 0; i < ARRAY_SIZE(lcd_phy_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_phy_debug_class_attrs[i])) { - LCDERR("create phy debug attribute %s fail\n", - lcd_phy_debug_class_attrs[i].attr.name); - } - } - break; - case LCD_MIPI: - dread.value = kcalloc(DSI_READ_CNT_MAX, sizeof(unsigned char), - GFP_KERNEL); - lcd_drv->lcd_config->lcd_control.mipi_config->dread = &dread; - for (i = 0; i < ARRAY_SIZE - (lcd_mipi_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_mipi_debug_class_attrs[i])) { - LCDERR("create mipi debug attr %s fail\n", - lcd_mipi_debug_class_attrs[i].attr.name); + return 0; +} + +static int lcd_class_remove(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct class *lcd_class; + struct class_attribute *lcd_attr; + int i; + + lcd_class = lcd_drv->lcd_debug_class; + + for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) + class_remove_file(lcd_class, &lcd_debug_class_attrs[i]); + + if (lcd_debug_info_if) { + if (lcd_debug_info_if->class_attrs) { + lcd_attr = lcd_debug_info_if->class_attrs; + while (lcd_attr) { + if (strcmp(lcd_attr->attr.name, "null") == 0) + break; + class_remove_file(lcd_class, lcd_attr); + lcd_attr++; } } - break; - default: - break; } + class_destroy(lcd_drv->lcd_debug_class); + lcd_drv->lcd_debug_class = NULL; + return 0; } -int lcd_class_remove(void) +/* ********************************** + * lcd debug match data + * ********************************** + */ +/* chip_type data */ +static struct lcd_debug_info_reg_s lcd_debug_info_reg_gxl = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_gxl, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_txl = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_txl, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_txlx = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_txlx, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_axg = { + .reg_clk_table = lcd_reg_dump_clk_axg, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path0 = { + .reg_clk_table = lcd_reg_dump_clk_hpll_g12a, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path1 = { + .reg_clk_table = lcd_reg_dump_clk_gp0_g12a, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_tl1 = { + .reg_clk_table = lcd_reg_dump_clk_tl1, + .reg_encl_table = lcd_reg_dump_encl_tl1, + .reg_pinmux_table = lcd_reg_dump_pinmux_tl1, +}; + +/* interface data */ +static struct lcd_debug_info_if_s lcd_debug_info_if_ttl = { + .interface_print = lcd_info_print_ttl, + .reg_dump_interface = lcd_reg_print_ttl, + .reg_dump_phy = NULL, + .class_attrs = lcd_debug_class_attrs_ttl, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_lvds = { + .interface_print = lcd_info_print_lvds, + .reg_dump_interface = lcd_reg_print_lvds, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_lvds, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_vbyone = { + .interface_print = lcd_info_print_vbyone, + .reg_dump_interface = lcd_reg_print_vbyone, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_vbyone, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_mipi = { + .interface_print = lcd_info_print_mipi, + .reg_dump_interface = lcd_reg_print_mipi, + .reg_dump_phy = lcd_reg_print_mipi_phy_analog, + .class_attrs = lcd_debug_class_attrs_mipi, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_mlvds = { + .interface_print = lcd_info_print_mlvds, + .reg_dump_interface = lcd_reg_print_mlvds, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_mlvds, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_p2p = { + .interface_print = lcd_info_print_p2p, + .reg_dump_interface = lcd_reg_print_p2p, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_p2p, +}; + +int lcd_debug_probe(void) { - int i; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int type; + int lcd_type, ret; - for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) { - class_remove_file(lcd_drv->lcd_debug_class, - &lcd_debug_class_attrs[i]); + lcd_type = lcd_drv->lcd_config->lcd_basic.lcd_type; + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_debug_info_reg = &lcd_debug_info_reg_tl1; + break; + case LCD_CHIP_G12A: + case LCD_CHIP_G12B: + if (lcd_drv->lcd_clk_path) + lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path1; + else + lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path0; + break; + case LCD_CHIP_AXG: + lcd_debug_info_reg = &lcd_debug_info_reg_axg; + break; + case LCD_CHIP_TXLX: + lcd_debug_info_reg = &lcd_debug_info_reg_txlx; + break; + case LCD_CHIP_TXL: + lcd_debug_info_reg = &lcd_debug_info_reg_txl; + break; + case LCD_CHIP_GXL: + case LCD_CHIP_GXM: + lcd_debug_info_reg = &lcd_debug_info_reg_gxl; + break; + default: + lcd_debug_info_reg = NULL; + break; } - type = lcd_drv->lcd_config->lcd_basic.lcd_type; - for (i = 0; i < ARRAY_SIZE(lcd_interface_debug_class_attrs); i++) { - if (strcmp(lcd_interface_debug_class_attrs[i].attr.name, - lcd_type_type_to_str(type))) - continue; - class_remove_file(lcd_drv->lcd_debug_class, - &lcd_interface_debug_class_attrs[i]); + switch (lcd_type) { + case LCD_TTL: + lcd_debug_info_if = &lcd_debug_info_if_ttl; + break; + case LCD_LVDS: + lcd_debug_info_if = &lcd_debug_info_if_lvds; + break; + case LCD_VBYONE: + lcd_debug_info_if = &lcd_debug_info_if_vbyone; + break; + case LCD_MIPI: + lcd_debug_info_if = &lcd_debug_info_if_mipi; + break; + case LCD_MLVDS: + lcd_debug_info_if = &lcd_debug_info_if_mlvds; + break; + case LCD_P2P: + lcd_debug_info_if = &lcd_debug_info_if_p2p; + break; + default: + lcd_debug_info_if = NULL; + break; } - class_destroy(lcd_drv->lcd_debug_class); - lcd_drv->lcd_debug_class = NULL; + ret = lcd_class_creat(); - return 0; + return ret; } +int lcd_debug_remove(void) +{ + int ret; + + ret = lcd_class_remove(); + return ret; +} diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.h b/drivers/amlogic/media/vout/lcd/lcd_debug.h new file mode 100644 index 0000000..8c72d7b0 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.h @@ -0,0 +1,187 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_debug.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AML_LCD_DEBUG_H__ +#define __AML_LCD_DEBUG_H__ +#include "lcd_reg.h" + +#define LCD_DEBUG_REG_CNT_MAX 30 +#define LCD_DEBUG_REG_END 0xffffffff + +struct lcd_debug_info_reg_s { + unsigned int *reg_clk_table; + unsigned int *reg_encl_table; + unsigned int *reg_pinmux_table; +}; + +struct lcd_debug_info_if_s { + int (*interface_print)(char *buf, int offset); + int (*reg_dump_interface)(char *buf, int offset); + int (*reg_dump_phy)(char *buf, int offset); + struct class_attribute *class_attrs; +}; + +static unsigned int lcd_reg_dump_clk_dft[] = { + HHI_HDMI_PLL_CNTL, + HHI_HDMI_PLL_CNTL2, + HHI_HDMI_PLL_CNTL3, + HHI_HDMI_PLL_CNTL4, + HHI_HDMI_PLL_CNTL5, + HHI_HDMI_PLL_CNTL6, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_axg[] = { + HHI_GP0_PLL_CNTL_AXG, + HHI_GP0_PLL_CNTL2_AXG, + HHI_GP0_PLL_CNTL3_AXG, + HHI_GP0_PLL_CNTL4_AXG, + HHI_GP0_PLL_CNTL5_AXG, + HHI_GP0_PLL_CNTL1_AXG, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_gp0_g12a[] = { + HHI_GP0_PLL_CNTL0_G12A, + HHI_GP0_PLL_CNTL1_G12A, + HHI_GP0_PLL_CNTL2_G12A, + HHI_GP0_PLL_CNTL3_G12A, + HHI_GP0_PLL_CNTL4_G12A, + HHI_GP0_PLL_CNTL5_G12A, + HHI_GP0_PLL_CNTL6_G12A, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + HHI_MIPIDSI_PHY_CLK_CNTL, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_hpll_g12a[] = { + HHI_HDMI_PLL_CNTL, + HHI_HDMI_PLL_CNTL2, + HHI_HDMI_PLL_CNTL3, + HHI_HDMI_PLL_CNTL4, + HHI_HDMI_PLL_CNTL5, + HHI_HDMI_PLL_CNTL6, + HHI_HDMI_PLL_CNTL7, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + HHI_MIPIDSI_PHY_CLK_CNTL, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_tl1[] = { + HHI_TCON_PLL_CNTL0, + HHI_TCON_PLL_CNTL1, + HHI_TCON_PLL_CNTL2, + HHI_TCON_PLL_CNTL3, + HHI_TCON_PLL_CNTL4, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_encl_dft[] = { + VPU_VIU_VENC_MUX_CTRL, + ENCL_VIDEO_EN, + ENCL_VIDEO_MODE, + ENCL_VIDEO_MODE_ADV, + ENCL_VIDEO_MAX_PXCNT, + ENCL_VIDEO_MAX_LNCNT, + ENCL_VIDEO_HAVON_BEGIN, + ENCL_VIDEO_HAVON_END, + ENCL_VIDEO_VAVON_BLINE, + ENCL_VIDEO_VAVON_ELINE, + ENCL_VIDEO_HSO_BEGIN, + ENCL_VIDEO_HSO_END, + ENCL_VIDEO_VSO_BEGIN, + ENCL_VIDEO_VSO_END, + ENCL_VIDEO_VSO_BLINE, + ENCL_VIDEO_VSO_ELINE, + ENCL_VIDEO_RGBIN_CTRL, + L_GAMMA_CNTL_PORT, + L_RGB_BASE_ADDR, + L_RGB_COEFF_ADDR, + L_POL_CNTL_ADDR, + L_DITH_CNTL_ADDR, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_encl_tl1[] = { + VPU_VIU_VENC_MUX_CTRL, + ENCL_VIDEO_EN, + ENCL_VIDEO_MODE, + ENCL_VIDEO_MODE_ADV, + ENCL_VIDEO_MAX_PXCNT, + ENCL_VIDEO_MAX_LNCNT, + ENCL_VIDEO_HAVON_BEGIN, + ENCL_VIDEO_HAVON_END, + ENCL_VIDEO_VAVON_BLINE, + ENCL_VIDEO_VAVON_ELINE, + ENCL_VIDEO_HSO_BEGIN, + ENCL_VIDEO_HSO_END, + ENCL_VIDEO_VSO_BEGIN, + ENCL_VIDEO_VSO_END, + ENCL_VIDEO_VSO_BLINE, + ENCL_VIDEO_VSO_ELINE, + ENCL_VIDEO_RGBIN_CTRL, + ENCL_INBUF_CNTL0, + ENCL_INBUF_CNTL1, + L_GAMMA_CNTL_PORT, + L_RGB_BASE_ADDR, + L_RGB_COEFF_ADDR, + L_POL_CNTL_ADDR, + L_DITH_CNTL_ADDR, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_gxl[] = { + PERIPHS_PIN_MUX_1, + PERIPHS_PIN_MUX_3, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_txl[] = { + PERIPHS_PIN_MUX_0, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_txlx[] = { + PERIPHS_PIN_MUX_0, + PERIPHS_PIN_MUX_8, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_tl1[] = { + PERIPHS_PIN_MUX_7, + PERIPHS_PIN_MUX_8, + PERIPHS_PIN_MUX_9, + LCD_DEBUG_REG_END, +}; + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.c b/drivers/amlogic/media/vout/lcd/lcd_reg.c index 93c5690..690bc66 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_reg.c +++ b/drivers/amlogic/media/vout/lcd/lcd_reg.c @@ -30,7 +30,8 @@ #define LCD_MAP_PERIPHS 0 #define LCD_MAP_DSI_HOST 1 #define LCD_MAP_DSI_PHY 2 -#define LCD_MAP_MAX 3 +#define LCD_MAP_TCON 3 +#define LCD_MAP_MAX 4 int lcd_reg_gxb[] = { LCD_MAP_PERIPHS, @@ -43,6 +44,12 @@ int lcd_reg_axg[] = { LCD_MAP_MAX, }; +int lcd_reg_tl1[] = { + LCD_MAP_TCON, + LCD_MAP_PERIPHS, + LCD_MAP_MAX, +}; + struct lcd_reg_map_s { unsigned int base_addr; unsigned int size; @@ -55,7 +62,6 @@ static struct lcd_reg_map_s *lcd_reg_map; int lcd_ioremap(struct platform_device *pdev) { int i = 0; - int ret = 0; int *table; struct resource *res; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); @@ -63,7 +69,7 @@ int lcd_ioremap(struct platform_device *pdev) lcd_reg_map = kcalloc(LCD_MAP_MAX, sizeof(struct lcd_reg_map_s), GFP_KERNEL); if (lcd_reg_map == NULL) { - LCDPR("lcd_reg_map buf malloc error\n"); + LCDERR("%s: lcd_reg_map buf malloc error\n", __func__); return -1; } table = lcd_drv->data->reg_map_table; @@ -72,19 +78,29 @@ int lcd_ioremap(struct platform_device *pdev) break; res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (res == NULL) { + LCDERR("%s: lcd_reg resource get error\n", __func__); + kfree(lcd_reg_map); + lcd_reg_map = NULL; + return -1; + } lcd_reg_map[table[i]].base_addr = res->start; lcd_reg_map[table[i]].size = resource_size(res); lcd_reg_map[table[i]].p = devm_ioremap_nocache(&pdev->dev, res->start, lcd_reg_map[table[i]].size); if (lcd_reg_map[table[i]].p == NULL) { lcd_reg_map[table[i]].flag = 0; - LCDERR("reg map failed: 0x%x\n", + LCDERR("%s: reg map failed: 0x%x\n", + __func__, lcd_reg_map[table[i]].base_addr); - ret = -1; + kfree(lcd_reg_map); + lcd_reg_map = NULL; + return -1; } else { lcd_reg_map[table[i]].flag = 1; if (lcd_debug_print_flag) { - LCDPR("reg mapped: 0x%x -> %p\n", + LCDPR("%s: reg mapped: 0x%x -> %p\n", + __func__, lcd_reg_map[table[i]].base_addr, lcd_reg_map[table[i]].p); } @@ -93,7 +109,7 @@ int lcd_ioremap(struct platform_device *pdev) i++; } - return ret; + return 0; } static int check_lcd_ioremap(int n) @@ -167,6 +183,44 @@ static inline void __iomem *check_lcd_dsi_phy_reg(unsigned int _reg) return p; } +static inline void __iomem *check_lcd_tcon_reg(unsigned int _reg) +{ + void __iomem *p; + int reg_bus; + unsigned int reg_offset; + + reg_bus = LCD_MAP_TCON; + if (check_lcd_ioremap(reg_bus)) + return NULL; + + reg_offset = LCD_REG_OFFSET(_reg); + if (reg_offset >= lcd_reg_map[reg_bus].size) { + LCDERR("invalid dsi_phy reg offset: 0x%04x\n", _reg); + return NULL; + } + p = lcd_reg_map[reg_bus].p + reg_offset; + return p; +} + +static inline void __iomem *check_lcd_tcon_reg_byte(unsigned int _reg) +{ + void __iomem *p; + int reg_bus; + unsigned int reg_offset; + + reg_bus = LCD_MAP_TCON; + if (check_lcd_ioremap(reg_bus)) + return NULL; + + reg_offset = LCD_REG_OFFSET_BYTE(_reg); + if (reg_offset >= lcd_reg_map[reg_bus].size) { + LCDERR("invalid dsi_phy reg offset: 0x%04x\n", _reg); + return NULL; + } + p = lcd_reg_map[reg_bus].p + reg_offset; + return p; +} + unsigned int lcd_vcbus_read(unsigned int reg) { return aml_read_vcbus(reg); @@ -357,3 +411,75 @@ void dsi_phy_clr_mask(unsigned int reg, unsigned int _mask) dsi_phy_write(reg, (dsi_phy_read(reg) & (~(_mask)))); } +unsigned int lcd_tcon_read(unsigned int _reg) +{ + void __iomem *p; + + p = check_lcd_tcon_reg(_reg); + if (p) + return readl(p); + else + return -1; +}; +void lcd_tcon_write(unsigned int _reg, unsigned int _value) +{ + void __iomem *p; + + p = check_lcd_tcon_reg(_reg); + if (p) + writel(_value, p); +}; + +void lcd_tcon_setb(unsigned int reg, unsigned int value, + unsigned int _start, unsigned int _len) +{ + lcd_tcon_write(reg, ((lcd_tcon_read(reg) & + (~(((1L << _len)-1) << _start))) | + ((value & ((1L << _len)-1)) << _start))); +} +unsigned int lcd_tcon_getb(unsigned int reg, + unsigned int _start, unsigned int _len) +{ + return (lcd_tcon_read(reg) >> _start) & ((1L << _len)-1); +} + +void lcd_tcon_set_mask(unsigned int reg, unsigned int _mask) +{ + lcd_tcon_write(reg, (lcd_tcon_read(reg) | (_mask))); +} +void lcd_tcon_clr_mask(unsigned int reg, unsigned int _mask) +{ + lcd_tcon_write(reg, (lcd_tcon_read(reg) & (~(_mask)))); +} + +unsigned char lcd_tcon_read_byte(unsigned int _reg) +{ + void __iomem *p; + + p = check_lcd_tcon_reg_byte(_reg); + if (p) + return readb(p); + else + return -1; +}; +void lcd_tcon_write_byte(unsigned int _reg, unsigned char _value) +{ + void __iomem *p; + + p = check_lcd_tcon_reg_byte(_reg); + if (p) + writeb(_value, p); +}; + +void lcd_tcon_setb_byte(unsigned int reg, unsigned char value, + unsigned int _start, unsigned int _len) +{ + lcd_tcon_write_byte(reg, ((lcd_tcon_read_byte(reg) & + (~(((1L << _len)-1) << _start))) | + ((value & ((1L << _len)-1)) << _start))); +} +unsigned char lcd_tcon_getb_byte(unsigned int reg, + unsigned int _start, unsigned int _len) +{ + return (lcd_tcon_read_byte(reg) >> _start) & ((1L << _len)-1); +} diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.h b/drivers/amlogic/media/vout/lcd/lcd_reg.h index 29f5d7a6..b09f71d 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_reg.h +++ b/drivers/amlogic/media/vout/lcd/lcd_reg.h @@ -22,8 +22,9 @@ /* register offset address define */ /* base & offset */ -#define LCD_REG_OFFSET(reg) ((reg << 2)) +#define LCD_REG_OFFSET(reg) ((reg << 2)) #define LCD_REG_OFFSET_MIPI_HOST(reg) (((reg & 0xff) << 2)) +#define LCD_REG_OFFSET_BYTE(reg) ((reg)) /* PERIPHS: 0xc8834400 */ @@ -120,13 +121,6 @@ #define HHI_EDP_APB_CLK_CNTL_M8M2 0x82 #define HHI_EDP_TX_PHY_CNTL0 0x9c #define HHI_EDP_TX_PHY_CNTL1 0x9d -/* m8b */ -#define HHI_VID_PLL_CNTL 0xc8 -#define HHI_VID_PLL_CNTL2 0xc9 -#define HHI_VID_PLL_CNTL3 0xca -#define HHI_VID_PLL_CNTL4 0xcb -#define HHI_VID_PLL_CNTL5 0xcc -#define HHI_VID_PLL_CNTL6 0xcd /* g9tv */ #define HHI_HDMI_PLL_CNTL 0xc8 #define HHI_HDMI_PLL_CNTL2 0xc9 @@ -134,8 +128,14 @@ #define HHI_HDMI_PLL_CNTL4 0xcb #define HHI_HDMI_PLL_CNTL5 0xcc #define HHI_HDMI_PLL_CNTL6 0xcd -/*G12A*/ +/* G12A */ #define HHI_HDMI_PLL_CNTL7 0xce +/* TL1 */ +#define HHI_TCON_PLL_CNTL0 0x020 +#define HHI_TCON_PLL_CNTL1 0x021 +#define HHI_TCON_PLL_CNTL2 0x022 +#define HHI_TCON_PLL_CNTL3 0x023 +#define HHI_TCON_PLL_CNTL4 0x0df #define HHI_DSI_LVDS_EDP_CNTL0 0xd1 #define HHI_DSI_LVDS_EDP_CNTL1 0xd2 @@ -179,6 +179,11 @@ #define HHI_MIPI_CNTL1 0x01 #define HHI_MIPI_CNTL2 0x02 +#define HHI_DIF_TCON_CNTL0 0x3c +#define HHI_DIF_TCON_CNTL1 0x3d +#define HHI_DIF_TCON_CNTL2 0x3e +#define HHI_TCON_CLK_CNTL 0xf0 + /* Global control: RESET_CBUS_BASE = 0x11 */ #define VERSION_CTRL 0x1100 #define RESET0_REGISTER 0x1101 @@ -904,85 +909,40 @@ #define ENCL_DACSEL_0 0x1cc9 #define ENCL_DACSEL_1 0x1cca +#define ENCL_INBUF_CNTL0 0x1cd3 +#define ENCL_INBUF_CNTL1 0x1cd4 + /* ******************************** - * ENCT: VCBUS_BASE = 0x1c - */ -/* ENCT */ -/* bit 15:8 -- vfifo2vd_vd_sel - * bit 7 -- vfifo2vd_drop - * bit 6:1 -- vfifo2vd_delay - * bit 0 -- vfifo2vd_en + * TCON TOP: TCON_TOP_BASE = 0x2000 + * ******************************** */ -#define ENCT_VFIFO2VD_CTL 0x1c20 -/* bit 12:0 -- vfifo2vd_pixel_start */ -#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 -/* bit 12:00 -- vfifo2vd_pixel_end */ -#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 -/* bit 10:0 -- vfifo2vd_line_top_start */ -#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 -/* bit 10:00 -- vfifo2vd_line_top_end */ -#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 -/* bit 10:00 -- vfifo2vd_line_bot_start */ -#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 -/* bit 10:00 -- vfifo2vd_line_bot_end */ -#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 -#define ENCT_VFIFO2VD_CTL2 0x1c27 -#define ENCT_TST_EN 0x1c28 -#define ENCT_TST_MDSEL 0x1c29 -#define ENCT_TST_Y 0x1c2a -#define ENCT_TST_CB 0x1c2b -#define ENCT_TST_CR 0x1c2c -#define ENCT_TST_CLRBAR_STRT 0x1c2d -#define ENCT_TST_CLRBAR_WIDTH 0x1c2e -#define ENCT_TST_VDCNT_STSET 0x1c2f +#define TCON_CORE_REG_START 0x0000 -/* ENCT registers */ -#define ENCT_VIDEO_EN 0x1c60 -#define ENCT_VIDEO_Y_SCL 0x1c61 -#define ENCT_VIDEO_PB_SCL 0x1c62 -#define ENCT_VIDEO_PR_SCL 0x1c63 -#define ENCT_VIDEO_Y_OFFST 0x1c64 -#define ENCT_VIDEO_PB_OFFST 0x1c65 -#define ENCT_VIDEO_PR_OFFST 0x1c66 -/* ----- Video mode */ -#define ENCT_VIDEO_MODE 0x1c67 -#define ENCT_VIDEO_MODE_ADV 0x1c68 -/* --------------- Debug pins */ -#define ENCT_DBG_PX_RST 0x1c69 -#define ENCT_DBG_LN_RST 0x1c6a -#define ENCT_DBG_PX_INT 0x1c6b -#define ENCT_DBG_LN_INT 0x1c6c -/* ----------- Video Advanced setting */ -#define ENCT_VIDEO_YFP1_HTIME 0x1c6d -#define ENCT_VIDEO_YFP2_HTIME 0x1c6e -#define ENCT_VIDEO_YC_DLY 0x1c6f -#define ENCT_VIDEO_MAX_PXCNT 0x1c70 -#define ENCT_VIDEO_HAVON_END 0x1c71 -#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 -#define ENCT_VIDEO_VAVON_ELINE 0x1c73 -#define ENCT_VIDEO_VAVON_BLINE 0x1c74 -#define ENCT_VIDEO_HSO_BEGIN 0x1c75 -#define ENCT_VIDEO_HSO_END 0x1c76 -#define ENCT_VIDEO_VSO_BEGIN 0x1c77 -#define ENCT_VIDEO_VSO_END 0x1c78 -#define ENCT_VIDEO_VSO_BLINE 0x1c79 -#define ENCT_VIDEO_VSO_ELINE 0x1c7a -#define ENCT_VIDEO_MAX_LNCNT 0x1c7b -#define ENCT_VIDEO_BLANKY_VAL 0x1c7c -#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d -#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e -#define ENCT_VIDEO_HOFFST 0x1c7f -#define ENCT_VIDEO_VOFFST 0x1c80 -#define ENCT_VIDEO_RGB_CTRL 0x1c81 -#define ENCT_VIDEO_FILT_CTRL 0x1c82 -#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 -#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 -#define ENCT_VIDEO_MATRIX_CB 0x1c85 -#define ENCT_VIDEO_MATRIX_CR 0x1c86 -#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 -#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 -#define ENCT_DACSEL_0 0x1c89 -#define ENCT_DACSEL_1 0x1c8a +#define TCON_CTRL_TIMING_BASE 0x01b0 + +#define TCON_TOP_CTRL 0x2000 +#define TCON_RGB_IN_MUX 0x2001 +#define TCON_OUT_CH_SEL0 0x2002 +#define TCON_OUT_CH_SEL1 0x2003 +#define TCON_I2C_DEGLITCH_CNTL 0x2004 +#define TCON_STATUS0 0x2008 /* read only */ +#define TCON_PLLLOCK_CNTL 0x2009 +#define TCON_PLLLCK_RST_CNT 0x200a +#define TCON_RST_CTRL 0x200b +#define TCON_AXI_OFST0 0x200c +#define TCON_DDRIF_CTRL0 0x200d +#define TCON_CLK_CTRL 0x200e +#define TCON_DDRIF_CTRL1 0x200f +#define TCON_STATUS1 0x2010 /* read only */ +#define TCON_DDRIF_CTRL2 0x2011 +#define TCON_STATUS2 0x2012 /* read only */ +#define TCON_AXI_OFST1 0x2013 +#define TCON_AXI_OFST2 0x2014 +#define TCON_GPO_CTRL0 0x2015 +#define TCON_GPO_CTRL1 0x2016 +#define TCON_GPO_CTRL2 0x2017 +#define TCON_INTR_MASKN 0x2022 +#define TCON_INTR 0x2023 /* read only */ /* ******************************** * Video post-processing: VPP_VCBUS_BASE = 0x1d @@ -1497,6 +1457,9 @@ /* *********************************************** * register access api */ +extern int lcd_reg_gxb[]; +extern int lcd_reg_axg[]; +extern int lcd_reg_tl1[]; extern int lcd_ioremap(struct platform_device *pdev); extern unsigned int lcd_vcbus_read(unsigned int _reg); @@ -1530,22 +1493,34 @@ extern void lcd_pinmux_clr_mask(unsigned int _reg, unsigned int _mask); extern unsigned int dsi_host_read(unsigned int _reg); extern void dsi_host_write(unsigned int _reg, unsigned int _value); extern void dsi_host_setb(unsigned int reg, unsigned int value, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern unsigned int dsi_host_getb(unsigned int reg, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern void dsi_host_set_mask(unsigned int reg, unsigned int _mask); extern void dsi_host_clr_mask(unsigned int reg, unsigned int _mask); extern unsigned int dsi_phy_read(unsigned int _reg); extern void dsi_phy_write(unsigned int _reg, unsigned int _value); extern void dsi_phy_setb(unsigned int reg, unsigned int value, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern unsigned int dsi_phy_getb(unsigned int reg, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern void dsi_phy_set_mask(unsigned int reg, unsigned int _mask); extern void dsi_phy_clr_mask(unsigned int reg, unsigned int _mask); -extern int lcd_reg_gxb[]; -extern int lcd_reg_axg[]; -#endif +extern unsigned int lcd_tcon_read(unsigned int _reg); +extern void lcd_tcon_write(unsigned int _reg, unsigned int _value); +extern void lcd_tcon_setb(unsigned int reg, unsigned int value, + unsigned int _start, unsigned int _len); +extern unsigned int lcd_tcon_getb(unsigned int reg, + unsigned int _start, unsigned int _len); +extern void lcd_tcon_set_mask(unsigned int reg, unsigned int _mask); +extern void lcd_tcon_clr_mask(unsigned int reg, unsigned int _mask); +extern unsigned char lcd_tcon_read_byte(unsigned int _reg); +extern void lcd_tcon_write_byte(unsigned int _reg, unsigned char _value); +extern void lcd_tcon_setb_byte(unsigned int reg, unsigned char value, + unsigned int _start, unsigned int _len); +extern unsigned char lcd_tcon_getb_byte(unsigned int reg, + unsigned int _start, unsigned int _len); +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c index fada75b..d5d69bb 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c @@ -342,6 +342,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf) { unsigned int h_active, v_active; unsigned int video_on_pixel, video_on_line; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag) LCDPR("%s\n", __func__); @@ -371,6 +372,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE, pconf->lcd_timing.vs_ve_addr); lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3); + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; + default: + break; + } + /* default black pattern */ lcd_vcbus_write(ENCL_TST_MDSEL, 0); lcd_vcbus_write(ENCL_TST_Y, 0); diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c index 856faa5..dfe6da1 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c @@ -1190,7 +1190,13 @@ static void lcd_config_init(struct lcd_config_s *pconf) lcd_tablet_config_update(pconf); lcd_clk_generate_parameter(pconf); ss_level = pconf->lcd_timing.ss_level; - cconf->ss_level = (ss_level >= cconf->ss_level_max) ? 0 : ss_level; + if (cconf->data) { + cconf->ss_level = (ss_level >= cconf->data->ss_level_max) ? + 0 : ss_level; + } else { + LCDERR("%s: clk config data is null\n", __func__); + cconf->ss_level = 0; + } lcd_tablet_config_post_update(pconf); } diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c index 9f80de2..b08e16a 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c @@ -1921,14 +1921,15 @@ void mipi_dsi_link_off(struct lcd_config_s *pconf) void lcd_mipi_dsi_config_set(struct lcd_config_s *pconf) { unsigned int pclk, bit_rate, lcd_bits; - unsigned int bit_rate_max, bit_rate_min, pll_out_fmin; + unsigned int bit_rate_max, bit_rate_min, pll_out_fmin = 0; struct dsi_config_s *dconf = pconf->lcd_control.mipi_config; struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int n; unsigned int temp; /* unit in kHz for calculation */ - pll_out_fmin = cConf->pll_out_fmin; + if (cConf->data) + pll_out_fmin = cConf->data->pll_out_fmin; pclk = pconf->lcd_timing.lcd_clk / 1000; /* data format */ diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.c b/drivers/amlogic/media/vout/lcd/lcd_tcon.c new file mode 100644 index 0000000..b2e2671 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.c @@ -0,0 +1,623 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lcd_common.h" +#include "lcd_reg.h" +#include "lcd_tcon.h" + +#define TCON_INTR_MASKN_VAL 0x0 /* default mask all */ + +static struct reserved_mem tcon_fb_rmem = {.base = 0, .size = 0}; + +static struct lcd_tcon_data_s *lcd_tcon_data; + +static int lcd_tcon_valid_check(void) +{ + if (lcd_tcon_data == NULL) { + LCDERR("invalid tcon data\n"); + return -1; + } + if (lcd_tcon_data->tcon_valid == 0) { + LCDERR("invalid tcon\n"); + return -1; + } + + return 0; +} + +static void lcd_tcon_od_check(unsigned char *table) +{ + unsigned int reg, bit; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) + return; + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (((table[reg] >> bit) & 1) == 0) + return; + + if (lcd_tcon_data->axi_offset_addr == 0) { + table[reg] &= ~(1 << bit); + LCDPR("%s: invalid fb, disable od function\n", __func__); + } +} + +void lcd_tcon_core_reg_update(void) +{ + unsigned char *table; + unsigned int len, temp; + int i, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + len = lcd_tcon_data->reg_table_len; + table = lcd_tcon_data->reg_table; + if (table == NULL) { + LCDERR("%s: table is NULL\n", __func__); + return; + } + lcd_tcon_od_check(table); + if (lcd_tcon_data->core_reg_width == 8) { + for (i = 0; i < len; i++) { + lcd_tcon_write_byte((i + TCON_CORE_REG_START), + table[i]); + } + } else { + for (i = 0; i < len; i++) + lcd_tcon_write((i + TCON_CORE_REG_START), table[i]); + } + LCDPR("tcon core regs update\n"); + + if (lcd_tcon_data->reg_core_od != REG_LCD_TCON_MAX) { + i = lcd_tcon_data->reg_core_od; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(i + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(i + TCON_CORE_REG_START); + LCDPR("%s: tcon od reg readback: 0x%04x = 0x%04x\n", + __func__, i, temp); + } +} + +static int lcd_tcon_top_set_tl1(void) +{ + unsigned int axi_reg[3] = { + TCON_AXI_OFST0, TCON_AXI_OFST1, TCON_AXI_OFST2 + }; + unsigned int addr[3] = {0, 0, 0}; + unsigned int size[3] = {0, 0, 0}; + int i; + + LCDPR("lcd tcon top set\n"); + + if (lcd_tcon_data->axi_offset_addr == 0) { + LCDERR("%s: invalid axi_offset_addr\n", __func__); + } else { + addr[0] = lcd_tcon_data->axi_offset_addr; + addr[1] = addr[0] + size[0]; + addr[2] = addr[1] + size[1]; + for (i = 0; i < 3; i++) { + lcd_tcon_write(axi_reg[i], addr[i]); + LCDPR("set tcon axi_offset_addr[%d]: 0x%08x\n", + i, addr[i]); + } + } + + lcd_tcon_write(TCON_CLK_CTRL, 0x001f); + lcd_tcon_write(TCON_TOP_CTRL, 0x8999); + lcd_tcon_write(TCON_PLLLOCK_CNTL, 0x0037); + lcd_tcon_write(TCON_RST_CTRL, 0x003f); + lcd_tcon_write(TCON_RST_CTRL, 0x0000); + lcd_tcon_write(TCON_DDRIF_CTRL0, 0x33fff000); + lcd_tcon_write(TCON_DDRIF_CTRL1, 0x300300); + + return 0; +} + +static int lcd_tcon_enable_tl1(struct lcd_config_s *pconf) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + /* step 1: tcon top */ + lcd_tcon_top_set_tl1(); + + /* step 2: tcon_core_reg_update */ + lcd_tcon_core_reg_update(); + + /* step 3: tcon_top_output_set */ + lcd_tcon_write(TCON_OUT_CH_SEL1, 0xba98); /* out swap for ch8~11 */ + LCDPR("set tcon ch_sel: 0x%08x, 0x%08x\n", + lcd_tcon_read(TCON_OUT_CH_SEL0), + lcd_tcon_read(TCON_OUT_CH_SEL1)); + + /* step 4: tcon_intr_mask */ + lcd_tcon_write(TCON_INTR_MASKN, TCON_INTR_MASKN_VAL); + + return 0; +} + +static irqreturn_t lcd_tcon_isr(int irq, void *dev_id) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + unsigned int temp; + + if ((lcd_drv->lcd_status & LCD_STATUS_IF_ON) == 0) + return IRQ_HANDLED; + + temp = lcd_tcon_read(TCON_INTR); + if (temp & 0x2) { + LCDPR("%s: tcon sw_reset triggered\n", __func__); + lcd_tcon_core_reg_update(); + } + if (temp & 0x40) + LCDPR("%s: tcon ddr interface error triggered\n", __func__); + + return IRQ_HANDLED; +} + +static void lcd_tcon_intr_init(struct aml_lcd_drv_s *lcd_drv) +{ + unsigned int tcon_irq = 0; + + if (!lcd_drv->res_tcon_irq) { + LCDERR("res_tcon_irq is null\n"); + return; + } + tcon_irq = lcd_drv->res_tcon_irq->start; + LCDPR("tcon_irq: %d\n", tcon_irq); + + if (request_irq(tcon_irq, lcd_tcon_isr, IRQF_SHARED, + "lcd_tcon", (void *)"lcd_tcon")) + LCDERR("can't request lcd_tcon irq\n"); + else { + LCDPR("request lcd_tcon successful\n"); + } + + lcd_tcon_write(TCON_INTR_MASKN, TCON_INTR_MASKN_VAL); +} + +static int lcd_tcon_config(struct aml_lcd_drv_s *lcd_drv) +{ + int key_len, reg_len, ret; + + /* init reserved memory */ + ret = of_reserved_mem_device_init(lcd_drv->dev); + if ((ret != 0) && ((void *)tcon_fb_rmem.base == NULL)) { + LCDERR("failed to init tcon axi reserved memory\n"); + } else { + lcd_tcon_data->axi_offset_addr = + virt_to_phys((void *)tcon_fb_rmem.base); + } + LCDPR("tcon axi_offset_addr = 0x%08x\n", + lcd_tcon_data->axi_offset_addr); + + /* get reg table from unifykey */ + reg_len = lcd_tcon_data->reg_table_len; + if (lcd_tcon_data->reg_table == NULL) { + lcd_tcon_data->reg_table = + kcalloc(reg_len, sizeof(unsigned char), GFP_KERNEL); + if (!lcd_tcon_data->reg_table) { + LCDERR("%s: Not enough memory\n", __func__); + return -1; + } + } + key_len = reg_len; + ret = lcd_unifykey_get_no_header("lcd_tcon", + lcd_tcon_data->reg_table, &key_len); + if (ret) { + kfree(lcd_tcon_data->reg_table); + lcd_tcon_data->reg_table = NULL; + LCDERR("%s: !!!!!!!!tcon unifykey load error!!!!!!!!\n", + __func__); + return -1; + } + if (key_len != reg_len) { + kfree(lcd_tcon_data->reg_table); + lcd_tcon_data->reg_table = NULL; + LCDERR("%s: !!!!!!!!tcon unifykey load length error!!!!!!!!\n", + __func__); + return -1; + } + LCDPR("tcon: load key len: %d\n", key_len); + + lcd_tcon_intr_init(lcd_drv); + + return 0; +} + +/* ********************************** + * tcon function api + * ********************************** + */ +#define PR_BUF_MAX 200 +void lcd_tcon_reg_table_print(void) +{ + int i, j, n, cnt; + char *buf; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + if (lcd_tcon_data->reg_table == NULL) { + LCDERR("%s: reg_table is null\n", __func__); + return; + } + + buf = kcalloc(PR_BUF_MAX, sizeof(char), GFP_KERNEL); + if (buf == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return; + } + + LCDPR("%s:\n", __func__); + cnt = lcd_tcon_data->reg_table_len; + for (i = 0; i < cnt; i += 16) { + n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i); + for (j = 0; j < 16; j++) { + if ((i + j) >= cnt) + break; + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_data->reg_table[i+j]); + } + buf[n] = '\0'; + pr_info("%s\n", buf); + } + kfree(buf); +} + +void lcd_tcon_reg_readback_print(void) +{ + int i, j, n, cnt; + char *buf; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + buf = kcalloc(PR_BUF_MAX, sizeof(char), GFP_KERNEL); + if (buf == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return; + } + + LCDPR("%s:\n", __func__); + cnt = lcd_tcon_data->reg_table_len; + for (i = 0; i < cnt; i += 16) { + n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i); + for (j = 0; j < 16; j++) { + if ((i + j) >= cnt) + break; + if (lcd_tcon_data->core_reg_width == 8) { + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_read_byte(i+j)); + } else { + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_read(i+j)); + } + } + buf[n] = '\0'; + pr_info("%s\n", buf); + } + kfree(buf); +} + +int lcd_tcon_info_print(char *buf, int offset) +{ + int len = 0, n, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return len; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "tcon info:\n" + "core_reg_width: %d\n" + "reg_table_len: %d\n" + "axi_offset_addr: 0x%08x\n\n", + lcd_tcon_data->core_reg_width, + lcd_tcon_data->reg_table_len, + lcd_tcon_data->axi_offset_addr); + + return len; +} + +int lcd_tcon_reg_table_size_get(void) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + return lcd_tcon_data->reg_table_len; +} + +unsigned char *lcd_tcon_reg_table_get(void) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return NULL; + + return lcd_tcon_data->reg_table; +} + +int lcd_tcon_core_reg_get(unsigned char *buf, unsigned int size) +{ + int i, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (size > lcd_tcon_data->reg_table_len) { + LCDERR("%s: size is not enough\n", __func__); + return -1; + } + + if (lcd_tcon_data->core_reg_width == 8) { + for (i = 0; i < size; i++) + buf[i] = lcd_tcon_read_byte(i + TCON_CORE_REG_START); + } else { + for (i = 0; i < size; i++) + buf[i] = lcd_tcon_read(i + TCON_CORE_REG_START); + } + + return 0; +} + +int lcd_tcon_od_set(int flag) +{ + unsigned int reg, bit, temp; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) { + LCDERR("%s: invalid od reg\n", __func__); + return -1; + } + + if (flag) { + if (lcd_tcon_data->axi_offset_addr == 0) { + LCDERR("%s: invalid fb, disable od function\n", + __func__); + return -1; + } + } + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(reg + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(reg + TCON_CORE_REG_START); + if (flag) + temp |= (1 << bit); + else + temp &= ~(1 << bit); + temp &= 0xff; + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_write_byte((reg + TCON_CORE_REG_START), temp); + else + lcd_tcon_write((reg + TCON_CORE_REG_START), temp); + + msleep(100); + LCDPR("%s: %d\n", __func__, flag); + + return 0; +} + +int lcd_tcon_od_get(void) +{ + unsigned int reg, bit, temp; + int ret = 0; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) { + LCDERR("%s: invalid od reg\n", __func__); + return -1; + } + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(reg + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(reg + TCON_CORE_REG_START); + ret = ((temp >> bit) & 1); + + return ret; +} + +int lcd_tcon_enable(struct lcd_config_s *pconf) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->tcon_enable) + lcd_tcon_data->tcon_enable(pconf); + + return 0; +} + +#define TCON_CTRL_TIMING_OFFSET 12 +void lcd_tcon_disable(void) +{ + unsigned int reg, i, cnt, offset, bit; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + LCDPR("%s\n", __func__); + + /* disable tcon intr */ + lcd_tcon_write(TCON_INTR_MASKN, 0); + + /* disable over_drive */ + if (lcd_tcon_data->reg_core_od != REG_LCD_TCON_MAX) { + reg = lcd_tcon_data->reg_core_od + TCON_CORE_REG_START; + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_write_byte(reg, 0); + else + lcd_tcon_write(reg, 0); + msleep(100); + } + + /* disable all ctrl signal */ + if (lcd_tcon_data->reg_core_ctrl_timing_base == REG_LCD_TCON_MAX) + goto lcd_tcon_disable_next; + reg = lcd_tcon_data->reg_core_ctrl_timing_base + TCON_CORE_REG_START; + offset = lcd_tcon_data->ctrl_timing_offset; + cnt = lcd_tcon_data->ctrl_timing_cnt; + for (i = 0; i < cnt; i++) { + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_setb_byte((reg + (i * offset)), 1, 3, 1); + else + lcd_tcon_setb((reg + (i * offset)), 1, 3, 1); + } + + /* disable top */ +lcd_tcon_disable_next: + if (lcd_tcon_data->reg_top_ctrl != REG_LCD_TCON_MAX) { + reg = lcd_tcon_data->reg_top_ctrl; + bit = lcd_tcon_data->bit_en; + lcd_tcon_setb(reg, 0, bit, 1); + } +} + +/* ********************************** + * tcon match data + * ********************************** + */ +static struct lcd_tcon_data_s tcon_data_tl1 = { + .tcon_valid = 0, + + .core_reg_width = LCD_TCON_CORE_REG_WIDTH_TL1, + .reg_table_len = LCD_TCON_TABLE_LEN_TL1, + + .reg_top_ctrl = TCON_TOP_CTRL, + .bit_en = BIT_TOP_EN_TL1, + + .reg_core_od = REG_LCD_TCON_MAX, + .bit_od_en = BIT_OD_EN_TL1, + + .reg_core_ctrl_timing_base = REG_CORE_CTRL_TIMING_BASE_TL1, + .ctrl_timing_offset = CTRL_TIMING_OFFSET_TL1, + .ctrl_timing_cnt = CTRL_TIMING_CNT_TL1, + + .axi_offset_addr = 0, + .reg_table = NULL, + + .tcon_enable = lcd_tcon_enable_tl1, +}; + +int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv) +{ + int ret = 0; + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_tcon_data = &tcon_data_tl1; + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + lcd_tcon_data->tcon_valid = 1; + break; + default: + break; + } + break; + default: + lcd_tcon_data = NULL; + break; + } + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + ret = lcd_tcon_config(lcd_drv); + + return ret; +} + +static int rmem_tcon_fb_device_init(struct reserved_mem *rmem, + struct device *dev) +{ + return 0; +} + +static const struct reserved_mem_ops rmem_tcon_fb_ops = { + .device_init = rmem_tcon_fb_device_init, +}; + +static int __init rmem_tcon_fb_setup(struct reserved_mem *rmem) +{ + /* + * phys_addr_t align = PAGE_SIZE; + * phys_addr_t mask = align - 1; + * if ((rmem->base & mask) || (rmem->size & mask)) { + * LCDERR("Reserved memory: incorrect alignment of region\n"); + * return -EINVAL; + * } + */ + tcon_fb_rmem.base = rmem->base; + tcon_fb_rmem.size = rmem->size; + rmem->ops = &rmem_tcon_fb_ops; + LCDPR("tcon: Reserved memory: created fb at 0x%p, size %ld MiB\n", + (void *)rmem->base, (unsigned long)rmem->size / SZ_1M); + return 0; +} +RESERVEDMEM_OF_DECLARE(fb, "amlogic, lcd_tcon-memory", rmem_tcon_fb_setup); + diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.h b/drivers/amlogic/media/vout/lcd/lcd_tcon.h new file mode 100644 index 0000000..8f210e6 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.h @@ -0,0 +1,63 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AML_LCD_TCON_H__ +#define __AML_LCD_TCON_H__ +#include + +#define REG_LCD_TCON_MAX 0xffff + +struct lcd_tcon_data_s { + unsigned char tcon_valid; + + unsigned int core_reg_width; + unsigned int reg_table_len; + + unsigned int reg_top_ctrl; + unsigned int bit_en; + + unsigned int reg_core_od; + unsigned int bit_od_en; + + unsigned int reg_core_ctrl_timing_base; + unsigned int ctrl_timing_offset; + unsigned int ctrl_timing_cnt; + + unsigned int axi_offset_addr; + unsigned char *reg_table; + + int (*tcon_enable)(struct lcd_config_s *pconf); +}; + +/* ********************************** + * tcon config + * ********************************** + */ +/* TL1 */ +#define LCD_TCON_CORE_REG_WIDTH_TL1 8 +#define LCD_TCON_TABLE_LEN_TL1 24000 +#define LCD_TCON_AXI_BANK_TL1 3 + +#define BIT_TOP_EN_TL1 4 + +#define REG_CORE_OD_TL1 0x5c +#define BIT_OD_EN_TL1 6 +#define REG_CORE_CTRL_TIMING_BASE_TL1 0x1b +#define CTRL_TIMING_OFFSET_TL1 12 +#define CTRL_TIMING_CNT_TL1 0 + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h b/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h new file mode 100644 index 0000000..fdf5398 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h @@ -0,0 +1,40993 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __LCD_TCON_REF_H__ +#define __LCD_TCON_REF_H__ + +static unsigned char tcon_boe_hd_hsd_n56[] = { + 0x40, + 0x44, + 0x44, + 0x44, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + 0x44, + 0x44, + 0x44, + 0x40, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x1B, + 0x00, + 0x00, + 0x0F, + 0xC8, + 0x00, + 0x11, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x6F, + 0x00, + 0x88, + 0x2B, + 0x00, + 0x10, + 0x32, + 0x54, + 0x76, + 0x90, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x07, + 0x80, + 0x03, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */ + 0x00, + 0x04, + 0x00, + 0x80, + 0x0F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x03, + 0x80, + 0x08, + 0x10, + 0x09, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xB4, + 0x33, + 0x00, + 0x3B, + 0x00, + 0x06, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE8, + 0x01, + 0x5A, + 0x00, + 0x2A, + 0xE8, + 0x00, + 0x02, + 0x00, + 0x02, + 0x3D, + 0xA3, + 0xC2, + 0x33, + 0x82, + 0xCA, + 0x28, + 0xC2, + 0x2D, + 0x22, + 0xB1, + 0xFB, + 0x1F, + 0xA1, + 0x56, + 0x11, + 0x90, + 0xBD, + 0x02, + 0xD0, + 0x14, + 0x00, + 0x20, + 0x56, + 0x55, + 0x6E, + 0xFF, + 0x3F, + 0x00, + 0x12, + 0xF3, + 0xC0, + 0x44, + 0x04, + 0x96, + 0xCC, + 0x01, + 0xFF, + 0x0A, + 0x0A, + 0x0A, + 0x0C, + 0x69, + 0x40, + 0x03, + 0x26, + 0x64, + 0x88, + 0x4C, + 0x00, + 0x11, + 0xC7, + 0x80, + 0x32, + 0x8E, + 0x88, + 0x00, + 0x0A, + 0x00, + 0x08, + 0x05, + 0xDC, + 0x03, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0A, + 0x00, + 0x00, + 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */ + 0xAB, + 0x42, + 0x00, + 0x00, + 0x00, + 0x01, + 0x0C, + 0x01, + 0x00, + 0x00, + 0xC0, + 0x03, + 0x1E, + 0x0C, + 0x20, + 0x00, + 0x88, + 0x08, + 0x00, + 0x64, + 0xC8, + 0x00, + 0x00, + 0x0A, + 0x20, + 0x00, + 0xCC, + 0x99, + 0x33, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x10, + 0x88, + 0x8F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x10, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x30, + 0xE8, + 0xFC, + 0x03, + 0x21, + 0x49, + 0xFF, + 0xFF, + 0xFF, + 0x04, + 0x20, + 0xA0, + 0x86, + 0x01, + 0x03, + 0xA0, + 0x86, + 0x01, + 0xD4, + 0x38, + 0x34, + 0xC0, + 0x38, + 0x74, + 0x01, + 0xF9, + 0xC7, + 0x11, + 0xC7, + 0x73, + 0x3C, + 0x80, + 0xE0, + 0xC7, + 0x1E, + 0x38, + 0x6D, + 0x60, + 0x64, + 0xF9, + 0xC3, + 0x06, + 0x18, + 0x9C, + 0x40, + 0x80, + 0xE0, + 0xC7, + 0x1E, + 0x38, + 0x4A, + 0x38, + 0x64, + 0x2C, + 0x07, + 0x00, + 0x07, + 0x0B, + 0xB8, + 0x80, + 0x70, + 0x07, + 0x00, + 0x07, + 0x05, + 0x14, + 0x80, + 0x3E, + 0xCC, + 0xCC, + 0xCC, + 0xFD, + 0xE8, + 0x80, + 0x20, + 0x89, + 0x85, + 0x22, + 0x03, + 0xE8, + 0x80, + 0x04, + 0x50, + 0xFF, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x01, + 0xF0, + 0xFF, + 0x02, + 0x23, + 0x03, + 0x44, + 0x29, + 0x11, + 0x10, + 0x01, + 0x00, + 0x01, + 0xF0, + 0xFF, + 0xFA, + 0xA0, + 0x0F, + 0x20, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x02, + 0xF0, + 0xFF, + 0xBC, + 0xC2, + 0x30, + 0x40, + 0x01, + 0x14, + 0x40, + 0x01, + 0x00, + 0x02, + 0x30, + 0x00, + 0xBC, + 0xC2, + 0x2B, + 0x40, + 0x01, + 0x35, + 0x40, + 0x01, + 0x00, + 0x03, + 0x40, + 0x00, + 0x79, + 0xE2, + 0x19, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x05, + 0xF0, + 0xFF, + 0x79, + 0x02, + 0x23, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x02, + 0xF0, + 0xFF, + 0x79, + 0x02, + 0x23, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x70, + 0x50, + 0x31, + 0xF0, + 0xF0, + 0xF4, + 0x20, + 0x00, + 0x10, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x10, + 0x02, + 0x10, + 0x10, + 0x10, + 0x10, + 0x10, + 0x10, + 0x04, + 0xAA, + 0x55, + 0x00, + 0x00, + 0x00, + 0x60, + 0x08, + 0x80, + 0x00, /* 0x2b1: 0x00 */ + 0x08, /* 0x2b2: 0x08 */ + 0x05, /* 0x2b3: 0x00 --> 0x05 */ + 0x58, /* 0x2b4: 0x08 --> 0x58 */ + 0x05, /* 0x2b5: 0x05 */ + 0x58, + 0x02, + 0x00, + 0x20, + 0x01, + 0x08, + 0x00, + 0x13, + 0x00, + 0x0C, + 0x0D, + 0xB7, + 0x03, + 0x94, + 0x18, + 0x00, + 0x10, + 0xF0, + 0x07, + 0x80, + 0x20, + 0x00, + 0x06, + 0x0B, + 0x0B, + 0x33, + 0x0E, + 0x1C, + 0x2A, + 0x38, + 0x46, + 0x54, + 0x62, + 0x69, + 0x70, + 0x77, + 0x79, + 0x7B, + 0x7D, + 0x7E, + 0x02, + 0x04, + 0x00, + 0x04, + 0x00, + 0x0D, + 0x3E, + 0x0E, + 0x3C, + 0x1F, + 0x3A, + 0x1F, + 0x38, + 0x1F, + 0x78, + 0x18, + 0x78, + 0x19, + 0x76, + 0x1A, + 0x76, + 0x1B, + 0x74, + 0x2C, + 0x74, + 0x2D, + 0x74, + 0x3D, + 0x74, + 0x6F, + 0x00, + 0x08, + 0x11, + 0x1A, + 0x23, + 0x2C, + 0x2D, + 0x3E, + 0x10, + 0x22, + 0x33, + 0x44, + 0x55, + 0x66, + 0x87, + 0x88, + 0x4F, + 0xA5, /* 0x30d: 0xa5 */ + 0xD7, /* 0x30e: 0x09 --> 0xd7 */ + 0x80, /* 0x30f: 0x60 --> 0x80 */ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 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0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x24, + 0xD5, +};/*end of boe hd hsd n56*/ + +static unsigned char tcon_boe_fhd_goa_n10[] = { + 0x40, + 0x44, + 0x44, + 0x44, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + 0x44, + 0x44, + 0x44, + 0x40, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x1B, + 0x00, + 0x20, /* 0x013 //0x00 --> 0x20 */ + 0x0F, + 0xC8, + 0x00, + 0x11, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x6F, + 0x00, + 0x88, + 0x2B, + 0x00, + 0x10, + 0x32, + 0x54, + 0x76, + 0x90, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x07, + 0x80, + 0x03, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */ + 0x00, + 0x04, + 0x00, + 0x80, + 0x0F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x03, + 0x80, + 0x08, + 0x10, + 0x09, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xB4, + 0x33, + 0x00, + 0x3B, + 0x00, + 0x06, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE8, + 0x01, + 0x5A, + 0x00, + 0x2A, + 0xE8, + 0x00, + 0x02, + 0x00, + 0x02, + 0x3D, + 0xA3, + 0xC2, + 0x33, + 0x82, + 0xCA, + 0x28, + 0xC2, + 0x2D, + 0x22, + 0xB1, + 0xFB, + 0x1F, + 0xA1, + 0x56, + 0x11, + 0x90, + 0xBD, + 0x02, + 0xD0, + 0x14, + 0x00, + 0x20, + 0x80, + 0x77, + 0x98, + 0xFF, + 0x4F, + 0x38, + 0x3E, + 0xF4, + 0xC0, + 0x44, + 0x04, + 0x96, + 0xCC, + 0x01, + 0xFF, + 0x0A, + 0x0A, + 0x0A, + 0x0C, + 0x89, + 0x70, + 0x04, + 0x4C, + 0x64, + 0xC0, + 0x6C, + 0x68, + 0x21, + 0xD0, + 0x80, + 0x52, + 0x00, + 0x88, + 0x00, + 0x0A, + 0x00, + 0x08, + 0x05, + 0xDC, + 0x03, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x38, + 0x11, + 0x11, + 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */ + 0x80, + 0x37, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0C, + 0x01, + 0x10, + 0x3C, + 0x82, /* 0x11e //0xc0 --> 0x82 */ + 0x27, /* 0x11f //0x03 --> 0x27 */ + 0x3C, /* 0x120 //0x1e --> 0x3c */ + 0x0C, + 0x20, + 0x00, + 0x18, + 0x0F, /* 0x125 //0x0b --> 0x0f */ + 0x00, + 0x64, + 0xC8, + 0x00, + 0x00, + 0x0A, + 0x20, + 0x00, + 0xCC, + 0x99, + 0x33, + 0xCC, + 0xDD, + 0xEE, + 0xCC, + 0xDD, + 0xEE, + 0xCC, + 0xDD, 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break; default: @@ -165,6 +167,86 @@ static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status) } } +static void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + if (status) { + vswing = pconf->lcd_control.mlvds_config->phy_vswing; + preem = pconf->lcd_control.mlvds_config->phy_preem; + if (vswing > 7) { + LCDERR("%s: wrong vswing_level=%d, use default\n", + __func__, vswing); + vswing = LVDS_PHY_VSWING_DFT; + } + if (preem > 3) { + LCDERR("%s: wrong preemphasis_level=%d, use default\n", + __func__, preem); + preem = LVDS_PHY_PREEM_DFT; + } + + data32 = MLVDS_PHY_CNTL1_TL1 | + (vswing << 3) | (vswing << 0) | (preem << 23); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = MLVDS_PHY_CNTL2_TL1 | + (preem << 14) | (preem << 12) | + (preem << 26) | (preem << 24); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = MLVDS_PHY_CNTL3_TL1 | + (preem << 6) | (preem << 4) | + (preem << 2) | (preem << 0) | (preem << 30); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + } +} + +static void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + if (status) { + vswing = pconf->lcd_control.p2p_config->phy_vswing; + preem = pconf->lcd_control.p2p_config->phy_preem; + if (vswing > 7) { + LCDERR("%s: wrong vswing_level=%d, use default\n", + __func__, vswing); + vswing = LVDS_PHY_VSWING_DFT; + } + if (preem > 3) { + LCDERR("%s: wrong preemphasis_level=%d, use default\n", + __func__, preem); + preem = LVDS_PHY_PREEM_DFT; + } + + data32 = MLVDS_PHY_CNTL1_TL1 | + (vswing << 3) | (vswing << 0) | (preem << 23); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = MLVDS_PHY_CNTL2_TL1 | + (preem << 14) | (preem << 12) | + (preem << 26) | (preem << 24); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = MLVDS_PHY_CNTL3_TL1 | + (preem << 6) | (preem << 4) | + (preem << 2) | (preem << 0) | (preem << 30); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + } +} + static void lcd_encl_tcon_set(struct lcd_config_s *pconf) { lcd_vcbus_write(L_RGB_BASE_ADDR, 0); @@ -209,6 +291,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf) { unsigned int h_active, v_active; unsigned int video_on_pixel, video_on_line; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag) LCDPR("%s\n", __func__); @@ -245,6 +328,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3); + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; + default: + break; + } + /* default black pattern */ lcd_vcbus_write(ENCL_TST_MDSEL, 0); lcd_vcbus_write(ENCL_TST_Y, 0); @@ -347,6 +439,89 @@ static void lcd_lvds_disable(void) lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */ } +static void lcd_mlvds_clk_util_set(struct lcd_config_s *pconf) +{ + unsigned int lcd_bits, div_sel; + + lcd_bits = pconf->lcd_basic.lcd_bits; + + switch (lcd_bits) { + case 6: + div_sel = 0; + break; + case 8: + div_sel = 2; + break; + default: + div_sel = 2; + break; + } + + /* set fifo_clk_sel */ + lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6)); + /* set cntl_ser_en: 8-channel to 1 */ + lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12); + + /* decoupling fifo enable, gated clock enable */ + lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1, + (1 << 30) | (0 << 25) | (1 << 24)); + /* decoupling fifo write enable after fifo enable */ + lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1); +} + +static void lcd_mlvds_control_set(struct lcd_config_s *pconf) +{ + unsigned int bit_num = 1; + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_mlvds_clk_util_set(pconf); + + switch (pconf->lcd_basic.lcd_bits) { + case 10: + bit_num = 0; + break; + case 8: + bit_num = 1; + break; + case 6: + bit_num = 2; + break; + case 4: + bit_num = 3; + break; + default: + bit_num = 1; + break; + } + + lcd_vcbus_write(LVDS_PACK_CNTL_ADDR, + (1 << 0) | // repack //[1:0] + (0 << 3) | // reserve + (0 << 4) | // lsb first + (0 << 5) | // pn swap + (1 << 6) | // dual port + (0 << 7) | // use tcon control + (bit_num << 8) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits. + (0 << 10) | //r_select //0:R, 1:G, 2:B, 3:0 + (1 << 12) | //g_select //0:R, 1:G, 2:B, 3:0 + (2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0; + + lcd_vcbus_write(LVDS_GEN_CNTL, + (lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (0x3 << 0))); + lcd_vcbus_setb(LVDS_GEN_CNTL, 1, 3, 1); + + lcd_tcon_enable(pconf); +} + +static void lcd_mlvds_disable(void) +{ + lcd_tcon_disable(); + + lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */ +} + #if 0 static void lcd_vbyone_ctlbits(int p3d_en, int p3d_lr, int mode) { @@ -623,6 +798,8 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf) static void lcd_vbyone_disable(void) { lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1); + lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1); + lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1); } #define VBYONE_INTR_UNMASK 0x2bff /* 0x2a00 */ @@ -1116,6 +1293,23 @@ static irqreturn_t lcd_vbyone_interrupt_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static void lcd_p2p_control_set(struct lcd_config_s *pconf) +{ + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_vbyone_control_set(pconf); + + lcd_tcon_enable(pconf); +} + +static void lcd_p2p_disable(void) +{ + lcd_tcon_disable(); + + lcd_vbyone_disable(); +} + static unsigned int vbyone_lane_num[] = { 1, 2, @@ -1185,6 +1379,61 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf) } } +static void lcd_mlvds_config_set(struct lcd_config_s *pconf) +{ + unsigned int bit_rate, pclk; + unsigned int lcd_bits, channel_num; + unsigned int channel_sel0, channel_sel1, pi_clk_sel; + unsigned int i, temp; + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_bits = pconf->lcd_basic.lcd_bits; + channel_num = pconf->lcd_control.mlvds_config->channel_num; + pclk = pconf->lcd_timing.lcd_clk / 1000; + bit_rate = lcd_bits * 3 * pclk / channel_num; + + pconf->lcd_control.mlvds_config->bit_rate = bit_rate * 1000; + + if (lcd_debug_print_flag) { + LCDPR("channel_num=%u, bit_rate=%u.%03uMHz, pclk=%u.%03uMhz\n", + channel_num, (bit_rate / 1000), (bit_rate % 1000), + (pclk / 1000), (pclk % 1000)); + } + + /* pi_clk select */ + /* mlvds channel: //tx 10 channels + * 0: d0_a + * 1: d1_a + * 2: d2_a + * 3: clk_a + * 4: d0_b + * 5: d1_b + * 6: d2_b + * 7: clk_b + */ + channel_sel0 = pconf->lcd_control.mlvds_config->channel_sel0; + channel_sel1 = pconf->lcd_control.mlvds_config->channel_sel1; + pi_clk_sel = 0; + for (i = 0; i < 8; i++) { + temp = (channel_sel0 >> (i*4)) & 0xf; + if ((temp == 3) || (temp == 7)) + pi_clk_sel |= (1 << i); + } + for (i = 0; i < 2; i++) { + temp = (channel_sel1 >> (i*4)) & 0xf; + if ((temp == 3) || (temp == 7)) + pi_clk_sel |= (1 << (i + 8)); + } + pconf->lcd_control.mlvds_config->pi_clk_sel = pi_clk_sel; + if (lcd_debug_print_flag) { + LCDPR( + "channel_sel0=0x%08x, channel_sel1=0x%08x, pi_clk_sel=0x%03x\n", + channel_sel0, channel_sel1, pi_clk_sel); + } +} + void lcd_tv_clk_config_change(struct lcd_config_s *pconf) { #ifdef CONFIG_AMLOGIC_VPU @@ -1194,6 +1443,9 @@ void lcd_tv_clk_config_change(struct lcd_config_s *pconf) case LCD_VBYONE: lcd_vbyone_config_set(pconf); break; + case LCD_MLVDS: + lcd_mlvds_config_set(pconf); + break; default: break; } @@ -1231,6 +1483,9 @@ void lcd_tv_config_update(struct lcd_config_s *pconf) case LCD_VBYONE: lcd_vbyone_config_set(pconf); break; + case LCD_MLVDS: + lcd_mlvds_config_set(pconf); + break; default: break; } @@ -1321,6 +1576,16 @@ int lcd_tv_driver_init(void) msecs_to_jiffies(LCD_VX1_WAIT_STABLE_DELAY)); } break; + case LCD_MLVDS: + lcd_mlvds_control_set(pconf); + lcd_tcon_pinmux_set(1); + lcd_mlvds_phy_set(pconf, 1); + break; + case LCD_P2P: + lcd_p2p_control_set(pconf); + lcd_tcon_pinmux_set(1); + lcd_p2p_phy_set(pconf, 1); + break; default: break; } @@ -1356,6 +1621,16 @@ void lcd_tv_driver_disable(void) lcd_vbyone_pinmux_set(0); lcd_vbyone_disable(); break; + case LCD_MLVDS: + lcd_mlvds_disable(); + lcd_mlvds_phy_set(pconf, 0); + lcd_tcon_pinmux_set(0); + break; + case LCD_P2P: + lcd_p2p_disable(); + lcd_p2p_phy_set(pconf, 0); + lcd_tcon_pinmux_set(0); + break; default: break; } diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c index f2e2ab6..9e441d1 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c @@ -1290,7 +1290,13 @@ static void lcd_config_init(struct lcd_config_s *pconf) lcd_tv_config_update(pconf); lcd_clk_generate_parameter(pconf); ss_level = pconf->lcd_timing.ss_level; - cconf->ss_level = (ss_level >= cconf->ss_level_max) ? 0 : ss_level; + if (cconf->data) { + cconf->ss_level = (ss_level >= cconf->data->ss_level_max) ? + 0 : ss_level; + } else { + LCDERR("%s: clk config data is null\n", __func__); + cconf->ss_level = 0; + } } static int lcd_get_config(struct lcd_config_s *pconf, struct device *dev) diff --git a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c index 9438913..015c357 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c +++ b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c @@ -204,6 +204,66 @@ int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len) return 0; } +int lcd_unifykey_check_no_header(char *key_name) +{ + unsigned int key_exist, keypermit, key_len; + int ret; + + key_exist = 0; + key_len = 0; + ret = key_unify_query(get_ukdev(), key_name, &key_exist, &keypermit); + if (ret < 0) { + if (lcd_debug_print_flag) + LCDUKEYERR("%s query exist error\n", key_name); + return -1; + } + if (key_exist == 0) { + if (lcd_debug_print_flag) + LCDUKEYERR("%s is not exist\n", key_name); + return -1; + } + + ret = key_unify_size(get_ukdev(), key_name, &key_len); + if (ret < 0) { + LCDUKEYERR("%s query size error\n", key_name); + return -1; + } + if (key_len == 0) { + if (lcd_debug_print_flag) + LCDUKEY("%s size is zero\n", key_name); + return -1; + } + if (lcd_debug_print_flag) + LCDUKEY("%s size: %d\n", key_name, key_len); + + return 0; +} + +int lcd_unifykey_get_no_header(char *key_name, unsigned char *buf, int *len) +{ + int key_len; + int ret; + + key_len = 0; + ret = lcd_unifykey_check_no_header(key_name); + if (ret < 0) + return -1; + ret = key_unify_size(get_ukdev(), key_name, &key_len); + if (key_len > *len) { + LCDUKEYERR("%s size(%d) is bigger than buf_size(%d)\n", + key_name, key_len, *len); + return -1; + } + *len = key_len; + + ret = key_unify_read(get_ukdev(), key_name, buf, key_len, &key_len); + if (ret < 0) { + LCDUKEYERR("%s unify read error\n", key_name); + return -1; + } + return 0; +} + void lcd_unifykey_print(void) { unsigned char *buf; @@ -313,6 +373,18 @@ int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len) return -1; } +int lcd_unifykey_check_no_header(char *key_name) +{ + LCDUKEYERR("Don't support unifykey\n"); + return -1; +} + +int lcd_unifykey_get_no_header(char *key_name, unsigned char *buf, int *len) +{ + LCDUKEYERR("Don't support unifykey\n"); + return -1; +} + void lcd_unifykey_print(void) { LCDUKEYERR("Don't support unifykey\n"); diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c index e726f0e..14dce11 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_vout.c +++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c @@ -36,7 +36,6 @@ #ifdef CONFIG_OF #include #endif -#include #include #include #include @@ -966,7 +965,7 @@ static int lcd_mode_probe(struct device *dev) break; } - lcd_class_creat(); + lcd_debug_probe(); lcd_fops_create(); lcd_notifier_register(); @@ -1063,6 +1062,7 @@ static int lcd_config_probe(struct platform_device *pdev) lcd_driver->res_vsync_irq = NULL; lcd_driver->res_vsync2_irq = NULL; lcd_driver->res_vx1_irq = NULL; + lcd_driver->res_tcon_irq = NULL; /* lcd driver assign */ ret = of_property_read_string(lcd_driver->dev->of_node, "mode", &str); @@ -1129,6 +1129,12 @@ static int lcd_config_probe(struct platform_device *pdev) platform_get_resource(pdev, IORESOURCE_IRQ, 1); } } + ret = of_property_read_string_index(lcd_driver->dev->of_node, + "interrupt-names", 2, &str); + if (ret == 0) { + lcd_driver->res_tcon_irq = platform_get_resource(pdev, + IORESOURCE_IRQ, 2); + } lcd_driver->lcd_info = &lcd_vinfo; lcd_driver->lcd_config = &lcd_config_dft; @@ -1218,12 +1224,6 @@ static void lcd_vsync_irq_remove(void) #ifdef CONFIG_OF -static struct lcd_data_s lcd_data_gxtvbb = { - .chip_type = LCD_CHIP_GXTVBB, - .chip_name = "gxtvbb", - .reg_map_table = &lcd_reg_gxb[0], -}; - static struct lcd_data_s lcd_data_gxl = { .chip_type = LCD_CHIP_GXL, .chip_name = "gxl", @@ -1266,12 +1266,14 @@ static struct lcd_data_s lcd_data_g12b = { .reg_map_table = &lcd_reg_axg[0], }; +static struct lcd_data_s lcd_data_tl1 = { + .chip_type = LCD_CHIP_TL1, + .chip_name = "tl1", + .reg_map_table = &lcd_reg_tl1[0], +}; + static const struct of_device_id lcd_dt_match_table[] = { { - .compatible = "amlogic, lcd-gxtvbb", - .data = &lcd_data_gxtvbb, - }, - { .compatible = "amlogic, lcd-gxl", .data = &lcd_data_gxl, }, @@ -1299,6 +1301,10 @@ static const struct of_device_id lcd_dt_match_table[] = { .compatible = "amlogic, lcd-g12b", .data = &lcd_data_g12b, }, + { + .compatible = "amlogic, lcd-tl1", + .data = &lcd_data_tl1, + }, {}, }; #endif @@ -1390,7 +1396,7 @@ static int lcd_remove(struct platform_device *pdev) if (lcd_driver) { lcd_vsync_irq_remove(); lcd_fops_remove(); - lcd_class_remove(); + lcd_debug_remove(); lcd_config_remove(lcd_driver->dev); kfree(lcd_driver); diff --git a/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h b/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h index 70e2efb..2204c6c 100644 --- a/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h +++ b/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h @@ -253,6 +253,9 @@ extern int lcd_unifykey_header_check(unsigned char *buf, struct aml_lcd_unifykey_header_s *header); extern int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len); +extern int lcd_unifykey_check_no_header(char *key_name); +extern int lcd_unifykey_get_no_header(char *key_name, + unsigned char *buf, int *len); extern void lcd_unifykey_print(void); #endif diff --git a/include/linux/amlogic/media/vout/lcd/lcd_vout.h b/include/linux/amlogic/media/vout/lcd/lcd_vout.h index 7348da4..ebf689f 100644 --- a/include/linux/amlogic/media/vout/lcd/lcd_vout.h +++ b/include/linux/amlogic/media/vout/lcd/lcd_vout.h @@ -81,14 +81,14 @@ enum lcd_mode_e { enum lcd_chip_e { - LCD_CHIP_GXTVBB = 0, - LCD_CHIP_GXL, /* 1 */ - LCD_CHIP_GXM, /* 2 */ - LCD_CHIP_TXL, /* 3 */ - LCD_CHIP_TXLX, /* 4 */ - LCD_CHIP_AXG, /* 5 */ - LCD_CHIP_G12A, /* 6 */ - LCD_CHIP_G12B, /* 7 */ + LCD_CHIP_GXL = 0, + LCD_CHIP_GXM, /* 1 */ + LCD_CHIP_TXL, /* 2 */ + LCD_CHIP_TXLX, /* 3 */ + LCD_CHIP_AXG, /* 4 */ + LCD_CHIP_G12A, /* 5 */ + LCD_CHIP_G12B, /* 6 */ + LCD_CHIP_TL1, /* 7 */ LCD_CHIP_MAX, }; @@ -103,6 +103,8 @@ enum lcd_type_e { LCD_LVDS, LCD_VBYONE, LCD_MIPI, + LCD_MLVDS, + LCD_P2P, LCD_TYPE_MAX, }; @@ -316,11 +318,47 @@ struct dsi_config_s { struct dsi_read_s *dread; }; +struct mlvds_config_s { + unsigned int channel_num; + unsigned int channel_sel0; + unsigned int channel_sel1; + unsigned int clk_phase; /* [13:12]=clk01_pi_sel, + * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 + */ + unsigned int pn_swap; + unsigned int bit_swap; /* MSB/LSB reverse */ + unsigned int phy_vswing; + unsigned int phy_preem; + + /* internal used */ + unsigned int pi_clk_sel; /* bit[9:0] */ + unsigned int bit_rate; /* Hz */ +}; + +struct p2p_config_s { + unsigned int channel_num; + unsigned int channel_sel0; + unsigned int channel_sel1; + unsigned int clk_phase; /* [13:12]=clk01_pi_sel, + * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 + */ + unsigned int pn_swap; + unsigned int bit_swap; /* MSB/LSB reverse */ + unsigned int phy_vswing; + unsigned int phy_preem; + + /* internal used */ + unsigned int pi_clk_sel; /* bit[9:0] */ + unsigned int bit_rate; /* Hz */ +}; + struct lcd_control_config_s { struct ttl_config_s *ttl_config; struct lvds_config_s *lvds_config; struct vbyone_config_s *vbyone_config; struct dsi_config_s *mipi_config; + struct mlvds_config_s *mlvds_config; + struct p2p_config_s *p2p_config; unsigned int *vlock_param; }; @@ -382,11 +420,6 @@ struct lcd_power_ctrl_s { int power_off_step_max; /* internal use for debug */ }; -struct lcd_clk_gate_ctrl_s { - struct reset_control *encl; - struct reset_control *vencl; -}; - #define LCD_ENABLE_RETRY_MAX 3 struct lcd_config_s { char *lcd_propname; @@ -402,7 +435,6 @@ struct lcd_config_s { unsigned char change_flag; unsigned char retry_enable_flag; unsigned char retry_enable_cnt; - struct lcd_clk_gate_ctrl_s rstc; }; struct lcd_duration_s { @@ -436,17 +468,6 @@ struct aml_lcd_drv_s { unsigned char viu_sel; unsigned char vsync_none_timer_flag; - unsigned char clk_gate_state; - struct clk *encl_top_gate; - struct clk *encl_int_gate; - - struct clk *dsi_host_gate; - struct clk *dsi_phy_gate; - struct clk *dsi_meas; - struct clk *mipi_enable_gate; - struct clk *mipi_bandgap_gate; - struct clk *gp0_pll; - struct device *dev; struct lcd_config_s *lcd_config; struct vinfo_s *lcd_info; @@ -472,6 +493,7 @@ struct aml_lcd_drv_s { struct resource *res_vsync_irq; struct resource *res_vsync2_irq; struct resource *res_vx1_irq; + struct resource *res_tcon_irq; struct mutex power_mutex; }; -- 2.7.4