From 2eb61fa5d68567435c4d0f1dcc0620bd9956edca Mon Sep 17 00:00:00 2001 From: Mark Murray Date: Wed, 4 Dec 2019 14:28:22 +0000 Subject: [PATCH] [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics. Summary: Add VMULL[BT]Q_(INT|POLY) intrinsics and unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71066 --- clang/include/clang/Basic/arm_mve.td | 34 ++++++ clang/include/clang/Basic/arm_mve_defs.td | 15 +++ clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | 125 ++++++++++++++++++++ clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | 125 ++++++++++++++++++++ clang/utils/TableGen/MveEmitter.cpp | 22 +++- llvm/include/llvm/IR/IntrinsicsARM.td | 14 +++ llvm/lib/Target/ARM/ARMInstrMVE.td | 126 +++++++++++++++------ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 8 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll | 121 ++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll | 121 ++++++++++++++++++++ 10 files changed, 668 insertions(+), 43 deletions(-) create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td index cc4b6d9..33e38ce 100644 --- a/clang/include/clang/Basic/arm_mve.td +++ b/clang/include/clang/Basic/arm_mve.td @@ -51,6 +51,21 @@ def vmulhq: Intrinsic $a, $b)>; def vrmulhq: Intrinsic $a, $b)>; +def vmullbq_int: Intrinsic + $a, $b, 0)>; +def vmulltq_int: Intrinsic + $a, $b, 1)>; +} + +let params = T.Poly, overrideKindLetter = "p" in { +def vmullbq_poly: Intrinsic + $a, $b, 0)>; +def vmulltq_poly: Intrinsic + $a, $b, 1)>; } let params = T.Float in { @@ -123,6 +138,25 @@ def vmulhq_m: Intrinsic< def vrmulhq_m: Intrinsic< Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), (IRInt<"rmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; +def vmullbq_int_m: Intrinsic< + DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), + (IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 0, + $pred, $inactive)>; +def vmulltq_int_m: Intrinsic< + DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), + (IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 1, + $pred, $inactive)>; +} + +let params = T.Poly, overrideKindLetter = "p" in { +def vmullbq_poly_m: Intrinsic< + DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), + (IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 0, + $pred, $inactive)>; +def vmulltq_poly_m: Intrinsic< + DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), + (IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 1, + $pred, $inactive)>; } // Predicated intrinsics - Float types only diff --git a/clang/include/clang/Basic/arm_mve_defs.td b/clang/include/clang/Basic/arm_mve_defs.td index 5aa10f2..6bc9b35 100644 --- a/clang/include/clang/Basic/arm_mve_defs.td +++ b/clang/include/clang/Basic/arm_mve_defs.td @@ -190,6 +190,7 @@ def CTO_Pred: ComplexTypeOp; class CTO_Tuple: ComplexTypeOp { int n = n_; } class CTO_Pointer: ComplexTypeOp { bit const = const_; } def CTO_CopyKind: ComplexTypeOp; +def CTO_DoubleSize: ComplexTypeOp; // ----------------------------------------------------------------------------- // Instances of Type intended to be used directly in the specification of an @@ -264,6 +265,11 @@ class CPtr: ComplexType<(CTO_Pointer<1> t)>; // matches that of s. class CopyKind: ComplexType<(CTO_CopyKind s, k)>; +// DoubleSize expects k to be a scalar type. It returns a scalar type +// whose kind (signed, unsigned or float) matches that of k, and whose size +// is double that of k, if possible. +class DoubleSize: ComplexType<(CTO_DoubleSize k)>; + // Unsigned expects t to be a scalar type, and expands to the unsigned // integer scalar of the same size. So it returns u16 if you give it s16 or // f16 (or u16 itself). @@ -274,6 +280,10 @@ class Unsigned: ComplexType<(CTO_CopyKind t, u32)>; def UScalar: Unsigned; def UVector: VecOf; +// DblVector expands to a vector of scalars of size twice the size of +// Scalar. +def DblVector: VecOf>; + // ----------------------------------------------------------------------------- // Internal definitions for specifying immediate arguments for an intrinsic. @@ -405,6 +415,10 @@ class Intrinsic { // True if the builtin has to avoid evaluating its arguments. bit nonEvaluating = 0; + + // Use to override the suffix letter to make e.g.vfooq_p16 + // with an override suffix letter of "p". + string overrideKindLetter = ""; } // Sometimes you have to use two separate Intrinsic declarations to @@ -433,6 +447,7 @@ def T { list Int16 = [s16, u16]; list Int32 = [s32, u32]; list Int64 = [s64, u64]; + list Poly = [u8, u16]; // Actually p8 and p16 list All8 = Int8; list All16 = Int16 # [f16]; list All32 = Int32 # [f32]; diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c new file mode 100644 index 0000000..124e205 --- /dev/null +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_vmullbq_int_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vmullbq_int_u8(uint8x16_t a, uint8x16_t b) +{ +#ifdef POLYMORPHIC + return vmullbq_int(a, b); +#else /* POLYMORPHIC */ + return vmullbq_int_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_int_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vmullbq_int_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vmullbq_int(a, b); +#else /* POLYMORPHIC */ + return vmullbq_int_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_int_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0) +// CHECK-NEXT: ret <2 x i64> [[TMP0]] +// +uint64x2_t test_vmullbq_int_u32(uint32x4_t a, uint32x4_t b) +{ +#ifdef POLYMORPHIC + return vmullbq_int(a, b); +#else /* POLYMORPHIC */ + return vmullbq_int_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_poly_p16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vmullbq_poly_p16(uint16x8_t a, uint16x8_t b) +{ +#ifdef POLYMORPHIC + return vmullbq_poly(a, b); +#else /* POLYMORPHIC */ + return vmullbq_poly_p16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_int_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vmullbq_int_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmullbq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmullbq_int_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_int_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vmullbq_int_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmullbq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmullbq_int_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_int_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP2]] +// +int64x2_t test_vmullbq_int_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmullbq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmullbq_int_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmullbq_poly_m_p8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vmullbq_poly_m_p8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmullbq_poly_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmullbq_poly_m_p8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c new file mode 100644 index 0000000..8659703 --- /dev/null +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_vmulltq_int_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vmulltq_int_u8(uint8x16_t a, uint8x16_t b) +{ +#ifdef POLYMORPHIC + return vmulltq_int(a, b); +#else /* POLYMORPHIC */ + return vmulltq_int_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_int_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vmulltq_int_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vmulltq_int(a, b); +#else /* POLYMORPHIC */ + return vmulltq_int_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_int_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1) +// CHECK-NEXT: ret <2 x i64> [[TMP0]] +// +uint64x2_t test_vmulltq_int_u32(uint32x4_t a, uint32x4_t b) +{ +#ifdef POLYMORPHIC + return vmulltq_int(a, b); +#else /* POLYMORPHIC */ + return vmulltq_int_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_poly_p16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vmulltq_poly_p16(uint16x8_t a, uint16x8_t b) +{ +#ifdef POLYMORPHIC + return vmulltq_poly(a, b); +#else /* POLYMORPHIC */ + return vmulltq_poly_p16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_int_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vmulltq_int_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmulltq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmulltq_int_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_int_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vmulltq_int_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmulltq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmulltq_int_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_int_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP2]] +// +int64x2_t test_vmulltq_int_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmulltq_int_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmulltq_int_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmulltq_poly_m_p8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vmulltq_poly_m_p8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vmulltq_poly_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vmulltq_poly_m_p8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} diff --git a/clang/utils/TableGen/MveEmitter.cpp b/clang/utils/TableGen/MveEmitter.cpp index 643d2d5..35a5e52 100644 --- a/clang/utils/TableGen/MveEmitter.cpp +++ b/clang/utils/TableGen/MveEmitter.cpp @@ -143,7 +143,7 @@ public: virtual std::string llvmName() const { PrintFatalError("no LLVM type name available for type " + cName()); } - virtual std::string acleSuffix() const { + virtual std::string acleSuffix(std::string) const { PrintFatalError("no ACLE suffix available for this type"); } }; @@ -180,7 +180,7 @@ public: std::string cName() const override { return "void"; } static bool classof(const Type *T) { return T->typeKind() == TypeKind::Void; } - std::string acleSuffix() const override { return ""; } + std::string acleSuffix(std::string) const override { return ""; } }; class PointerType : public Type { @@ -266,8 +266,9 @@ public: } return "Int" + utostr(Bits) + "Ty"; } - std::string acleSuffix() const override { - return "_" + toLetter(Kind) + utostr(Bits); + std::string acleSuffix(std::string overrideLetter) const override { + return "_" + (overrideLetter.size() ? overrideLetter : toLetter(Kind)) + + utostr(Bits); } bool isInteger() const { return Kind != ScalarTypeKind::Float; } bool requiresFloat() const override { return !isInteger(); } @@ -1093,6 +1094,16 @@ const Type *MveEmitter::getType(DagInit *D, const Type *Param) { PrintFatalError("Cannot find a type to satisfy CopyKind"); } + if (Op->getName() == "CTO_DoubleSize") { + const ScalarType *STKind = cast(getType(D->getArg(0), Param)); + for (const auto &kv : ScalarTypes) { + const ScalarType *RT = kv.second.get(); + if (RT->kind() == STKind->kind() && RT->sizeInBits() == 2*STKind->sizeInBits()) + return RT; + } + PrintFatalError("Cannot find a type to satisfy DoubleSize"); + } + PrintFatalError("Bad operator in type dag expression"); } @@ -1251,7 +1262,8 @@ ACLEIntrinsic::ACLEIntrinsic(MveEmitter &ME, Record *R, const Type *Param) StringRef BaseName = (R->isSubClassOf("NameOverride") ? R->getValueAsString("basename") : R->getName()); - FullName = (Twine(BaseName) + Param->acleSuffix()).str(); + StringRef overrideLetter = R->getValueAsString("overrideKindLetter"); + FullName = (Twine(BaseName) + Param->acleSuffix(overrideLetter)).str(); // Derive the intrinsic's polymorphic name, by removing components from the // full name as specified by its 'pnt' member ('polymorphic name type'), diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index cf89664..17dbf5f 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -840,6 +840,14 @@ def int_arm_mve_mulh_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_rmulh_predicated: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; +def int_arm_mve_mull_int_predicated: Intrinsic<[llvm_anyvector_ty], + [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty, + LLVMMatchType<1>], + [IntrNoMem]>; +def int_arm_mve_mull_poly_predicated: Intrinsic<[llvm_anyvector_ty], + [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty, + LLVMMatchType<1>], + [IntrNoMem]>; defm int_arm_mve_minv: IntrinsicSignSuffix<[llvm_i32_ty], [llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>; @@ -928,6 +936,12 @@ def int_arm_mve_vmulh: Intrinsic< def int_arm_mve_vrmulh: Intrinsic< [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; +def int_arm_mve_vmull: Intrinsic< + [llvm_anyvector_ty], + [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrNoMem]>; +def int_arm_mve_vmull_poly: Intrinsic< + [llvm_anyvector_ty], + [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrNoMem]>; // Intrinsic with a predicated and a non-predicated case. The predicated case // has two additional parameters: inactive (the value for inactive lanes, can diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index 10a4c6d..6a0cbd5 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -277,12 +277,17 @@ class mve_addr_q_shift : MemOperand { // A family of classes wrapping up information about the vector types // used by MVE. -class MVEVectorVTInfo size, - string suffixletter, bit unsigned> { +class MVEVectorVTInfo size, string suffixletter, bit unsigned> { // The LLVM ValueType representing the vector, so we can use it in // ISel patterns. ValueType Vec = vec; + // The LLVM ValueType representing a vector with elements double the size + // of those in Vec, so we can use it in ISel patterns. It is up to the + // invoker of this class to ensure that this is a correct choice. + ValueType DblVec = dblvec; + // An LLVM ValueType representing a corresponding vector of // predicate bits, for use in ISel patterns that handle an IR // intrinsic describing the predicated form of the instruction. @@ -309,34 +314,40 @@ class MVEVectorVTInfo size, // The suffix used in assembly language on an instruction operating // on this lane if it only cares about number of bits. - string BitsSuffix = !cast(LaneBits); + string BitsSuffix = !if(!eq(suffixletter, "p"), + !if(!eq(unsigned, 0b0), "8", "16"), + !cast(LaneBits)); // The suffix used on an instruction that mentions the whole type. string Suffix = suffixletter ## BitsSuffix; } // Integer vector types that don't treat signed and unsigned differently. -def MVE_v16i8 : MVEVectorVTInfo; -def MVE_v8i16 : MVEVectorVTInfo; -def MVE_v4i32 : MVEVectorVTInfo; -def MVE_v2i64 : MVEVectorVTInfo; +def MVE_v16i8 : MVEVectorVTInfo; +def MVE_v8i16 : MVEVectorVTInfo; +def MVE_v4i32 : MVEVectorVTInfo; +def MVE_v2i64 : MVEVectorVTInfo; // Explicitly signed and unsigned integer vectors. They map to the // same set of LLVM ValueTypes as above, but are represented // differently in assembly and instruction encodings. -def MVE_v16s8 : MVEVectorVTInfo; -def MVE_v8s16 : MVEVectorVTInfo; -def MVE_v4s32 : MVEVectorVTInfo; -def MVE_v2s64 : MVEVectorVTInfo; -def MVE_v16u8 : MVEVectorVTInfo; -def MVE_v8u16 : MVEVectorVTInfo; -def MVE_v4u32 : MVEVectorVTInfo; -def MVE_v2u64 : MVEVectorVTInfo; +def MVE_v16s8 : MVEVectorVTInfo; +def MVE_v8s16 : MVEVectorVTInfo; +def MVE_v4s32 : MVEVectorVTInfo; +def MVE_v2s64 : MVEVectorVTInfo; +def MVE_v16u8 : MVEVectorVTInfo; +def MVE_v8u16 : MVEVectorVTInfo; +def MVE_v4u32 : MVEVectorVTInfo; +def MVE_v2u64 : MVEVectorVTInfo; // FP vector types. -def MVE_v8f16 : MVEVectorVTInfo; -def MVE_v4f32 : MVEVectorVTInfo; -def MVE_v2f64 : MVEVectorVTInfo; +def MVE_v8f16 : MVEVectorVTInfo; +def MVE_v4f32 : MVEVectorVTInfo; +def MVE_v2f64 : MVEVectorVTInfo; + +// Polynomial vector types. +def MVE_v16p8 : MVEVectorVTInfo; +def MVE_v8p16 : MVEVectorVTInfo; // --------- Start of base classes for the instructions themselves @@ -3616,24 +3627,71 @@ class MVE_VMULL bits_21_20, let Inst{0} = 0b0; } -multiclass MVE_VMULL_multi bits_21_20, string cstr=""> { - def bh : MVE_VMULL; - def th : MVE_VMULL; -} +multiclass MVE_VMULL_m { + def "" : MVE_VMULL<"vmull" # !if(Top, "t", "b"), VTI.Suffix, VTI.Unsigned, + VTI.Size, Top, cstr>; + + let Predicates = [HasMVEInt] in { + // Unpredicated multiply + def : Pat<(VTI.DblVec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), + (i32 Top))), + (VTI.DblVec (!cast(NAME) + (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; -// For integer multiplies, bits 21:20 encode size, and bit 28 signedness. -// For polynomial multiplies, bits 21:20 take the unused value 0b11, and -// bit 28 switches to encoding the size. + // Predicated multiply + def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), + (i32 Top), + (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))), + (VTI.DblVec (!cast(NAME) + (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), + ARMVCCThen, (VTI.Pred VCCR:$mask), + (VTI.Vec MQPR:$inactive)))>; + } +} -defm MVE_VMULLs8 : MVE_VMULL_multi<"vmull", "s8", 0b0, 0b00>; -defm MVE_VMULLs16 : MVE_VMULL_multi<"vmull", "s16", 0b0, 0b01>; -defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10, "@earlyclobber $Qd">; -defm MVE_VMULLu8 : MVE_VMULL_multi<"vmull", "u8", 0b1, 0b00>; -defm MVE_VMULLu16 : MVE_VMULL_multi<"vmull", "u16", 0b1, 0b01>; -defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10, "@earlyclobber $Qd">; -defm MVE_VMULLp8 : MVE_VMULL_multi<"vmull", "p8", 0b0, 0b11>; -defm MVE_VMULLp16 : MVE_VMULL_multi<"vmull", "p16", 0b1, 0b11>; +// For polynomial multiplies, the size bits take the unused value 0b11, and +// the unsigned bit switches to encoding the size. + +defm MVE_VMULLBs8 : MVE_VMULL_m; +defm MVE_VMULLTs8 : MVE_VMULL_m; +defm MVE_VMULLBs16 : MVE_VMULL_m; +defm MVE_VMULLTs16 : MVE_VMULL_m; +defm MVE_VMULLBs32 : MVE_VMULL_m; +defm MVE_VMULLTs32 : MVE_VMULL_m; + +defm MVE_VMULLBu8 : MVE_VMULL_m; +defm MVE_VMULLTu8 : MVE_VMULL_m; +defm MVE_VMULLBu16 : MVE_VMULL_m; +defm MVE_VMULLTu16 : MVE_VMULL_m; +defm MVE_VMULLBu32 : MVE_VMULL_m; +defm MVE_VMULLTu32 : MVE_VMULL_m; + +defm MVE_VMULLBp8 : MVE_VMULL_m; +defm MVE_VMULLTp8 : MVE_VMULL_m; +defm MVE_VMULLBp16 : MVE_VMULL_m; +defm MVE_VMULLTp16 : MVE_VMULL_m; class MVE_VxMULH size, bit round, list pattern=[]> diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index d2c355c..72b2feb 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7895,10 +7895,10 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, case ARM::MVE_VQDMULLs32bh: case ARM::MVE_VQDMULLs32th: case ARM::MVE_VCMULf32: - case ARM::MVE_VMULLs32bh: - case ARM::MVE_VMULLs32th: - case ARM::MVE_VMULLu32bh: - case ARM::MVE_VMULLu32th: { + case ARM::MVE_VMULLBs32: + case ARM::MVE_VMULLTs32: + case ARM::MVE_VMULLBu32: + case ARM::MVE_VMULLTu32: { if (Operands[3]->getReg() == Operands[4]->getReg()) { return Error (Operands[3]->getStartLoc(), "Qd register and Qn register can't be identical"); diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll new file mode 100644 index 0000000..78f24fa --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll @@ -0,0 +1,121 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s + +define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullb.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0) + ret <8 x i16> %0 +} + +declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullb.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0) + ret <4 x i32> %0 +} + +declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 + +define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullb.s32 q2, q0, q1 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0) + ret <2 x i64> %0 +} + +declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_poly_p16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullb.p16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0) + ret <4 x i32> %0 +} + +declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 + +define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmullbt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <8 x i16> %2 +} + +declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 + +declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmullbt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive) + ret <4 x i32> %2 +} + +declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 + +declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 + +define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_int_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmullbt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive) + ret <2 x i64> %2 +} + +declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 + +declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 + +define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmullbq_poly_m_p8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmullbt.p8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <8 x i16> %2 +} + +declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll new file mode 100644 index 0000000..5dde90e --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll @@ -0,0 +1,121 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s + +define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullt.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1) + ret <8 x i16> %0 +} + +declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullt.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1) + ret <4 x i32> %0 +} + +declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 + +define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullt.s32 q2, q0, q1 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1) + ret <2 x i64> %0 +} + +declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_poly_p16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmullt.p16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1) + ret <4 x i32> %0 +} + +declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 + +define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmulltt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <8 x i16> %2 +} + +declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 + +declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 + +define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmulltt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive) + ret <4 x i32> %2 +} + +declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 + +declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 + +define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_int_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmulltt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> %inactive) + ret <2 x i64> %2 +} + +declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 + +declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 + +define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { +; CHECK-LABEL: test_vmulltq_poly_m_p8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vmulltt.p8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <8 x i16> %2 +} + +declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 -- 2.7.4