From 2e7656ae2fdd0cd898812b5762138c14149cb6e9 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 5 Feb 2021 08:09:47 -0600 Subject: [PATCH] intel/eu: SVB writes only happen on Gen6 It's a Gen6 XFB thing. It's never used for anything else so there's no point in having a target cache switch. Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_eu_emit.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 138c48e..a8577fa 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3067,10 +3067,8 @@ brw_svb_write(struct brw_codegen *p, bool send_commit_msg) { const struct intel_device_info *devinfo = p->devinfo; - const unsigned target_cache = - (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : - devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_WRITE); + assert(devinfo->ver == 6); + const unsigned target_cache = GFX6_SFID_DATAPORT_RENDER_CACHE; brw_inst *insn; gfx6_resolve_implied_move(p, &src0, msg_reg_nr); -- 2.7.4