From 2e5c516a3d6953edbc66072a82f88371ff668e9d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Tue, 2 Aug 2022 09:29:22 -0700
Subject: [PATCH] [RISCV] Add scheduler class to PseudoReadVLENB.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D130938
---
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 3 ++-
 llvm/lib/Target/RISCV/RISCVScheduleV.td         | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index fbe396d..8bae021 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4332,7 +4332,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
   def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
-                               [(set GPR:$rd, (riscv_read_vlenb))]>;
+                               [(set GPR:$rd, (riscv_read_vlenb))]>,
+                        Sched<[WriteRdVLENB]>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index bafcf47..6b648cb 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,6 +9,9 @@
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
+// 3.6 Vector Byte Length vlenb
+def WriteRdVLENB      : SchedWrite;
+
 // 7. Vector Loads and Stores
 // 7.4. Vector Unit-Stride Instructions
 def WriteVLDE8        : SchedWrite;
@@ -493,6 +496,9 @@ def ReadVMask         : SchedRead;
 multiclass UnsupportedSchedV {
 let Unsupported = true in {
 
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, []>;
+
 // 7. Vector Loads and Stores
 def : WriteRes<WriteVLDE8, []>;
 def : WriteRes<WriteVLDE16, []>;
-- 
2.7.4