From 2e4555b015de6b1429f70263633c622c06c5c6eb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:18 -0700 Subject: [PATCH] perf vendor events intel: Update free running alderlake events Fix the PMU name, event code and umask. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/alderlake/uncore-memory.json | 16 ++++++++++++---- .../pmu-events/arch/x86/alderlaken/uncore-memory.json | 16 ++++++++++++---- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json index 2ccd9cf..163d7e7 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json @@ -1,29 +1,37 @@ [ { "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_1" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_1" }, { "BriefDescription": "ACT command for a read request sent to DRAM", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json index 2ccd9cf..163d7e7 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json @@ -1,29 +1,37 @@ [ { "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_1" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_1" }, { "BriefDescription": "ACT command for a read request sent to DRAM", -- 2.7.4