From 2df41a8e38976de5a161b2cd06bc5d1e0136df74 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 4 Sep 2019 20:46:31 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Select G_BITREVERSE llvm-svn: 370980 --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 + llvm/lib/Target/AMDGPU/VOP1Instructions.td | 2 +- .../AMDGPU/GlobalISel/inst-select-bitreverse.mir | 53 ++++++++++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-bitreverse.mir | 31 +++++++++++++ 4 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index d0382bf..bffc3dd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1775,6 +1775,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_CTTZ_ZERO_UNDEF: case AMDGPU::G_CTPOP: case AMDGPU::G_BSWAP: + case AMDGPU::G_BITREVERSE: case AMDGPU::G_FABS: case AMDGPU::G_FNEG: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 6bc416e..e5890cb 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -227,7 +227,7 @@ defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>; } // End SchedRW = [WriteQuarterRate32] defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>; -defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>; defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>; defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>; defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32>; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir new file mode 100644 index 0000000..515ad6e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir @@ -0,0 +1,53 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s + +--- +name: bitreverse_i32_ss +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: bitreverse_i32_ss + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]] + ; CHECK: S_ENDPGM 0, implicit [[S_BREV_B32_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:sgpr(s32) = G_BITREVERSE %0 + S_ENDPGM 0, implicit %1 +... + +--- +name: bitreverse_i32_vv +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: bitreverse_i32_vv + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec + ; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = G_BITREVERSE %0 + S_ENDPGM 0, implicit %1 +... + +--- +name: bitreverse_i32_vs +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: bitreverse_i32_vs + ; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec + ; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = G_BITREVERSE %0 + S_ENDPGM 0, implicit %1 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir new file mode 100644 index 0000000..15f4711 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: bitreverse_i32_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: bitreverse_i32_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[BITREVERSE:%[0-9]+]]:sgpr(s32) = G_BITREVERSE [[COPY]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_BITREVERSE %0 +... + +--- +name: bitreverse_i32_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: bitreverse_i32_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[BITREVERSE:%[0-9]+]]:vgpr(s32) = G_BITREVERSE [[COPY]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_BITREVERSE %0 +... -- 2.7.4