From 2daaf5b0e4fbed1fa9524881272c9a956a0aaf78 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 26 Nov 2013 14:31:18 +1000 Subject: [PATCH] drm/nve0/fb/gddr5: fix behaviour of lp3 setting Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c | 3 +++ drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c index 34f9605..012c1ea 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c @@ -78,6 +78,9 @@ nouveau_gddr5_calc(struct nouveau_ram *ram) ram->mr[3] &= ~0x020; ram->mr[3] |= (rq & 0x01) << 5; + /*XXX: LP3, where's the bit? Let's hardcode to off for now */ + ram->mr[5] &= ~0x004; + if (!vo) vo = (ram->mr[6] & 0xff0) >> 4; if (ram->mr[6] & 0x001) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index bc86cfd..0fa983f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -528,7 +528,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); ram_nsec(fuc, 1000); ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); - ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5]); + ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); @@ -582,7 +582,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) /* MR5: (re)enable LP3 if necessary * XXX: need to find the switch, keeping off for now */ - ram_mask(fuc, mr[5], 0x00000004, 0x00000000); + ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5]); if (ram->mode != 2) { ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); -- 2.7.4